®

RT7291A/B

6A, 23V, 500kHz, ACOT® Synchronous Buck Converter

with LDO for System 5V
General Description Features
The RT7291A/B is a synchronous Buck converter with  5V to 23V Input Voltage Range
Advanced Constant On-Time (ACOT®) mode control. The  Up to 98% Duty for 2S Battery Application
main control loop of the RT7291A/B uses an ACOT® mode  PWM Frequency Fixed 500kHz
control which provides a very fast transient response with  ACOT® Mode Performs Fast Transient Response
no external compensators. The RT7291A/B operates from  Integrated MOSFETs
5V to 23V input voltage, provides a 5V LDO and a 300kHz  31mΩ Ω of High-Side MOSFET
CLK to drive an external charge pump. OCP, UVP and  20mΩ Ω of Low-Side MOSFET
OVP are included in the RT7291A/B. This IC also provides  Support Output MLCC Stable
a 1.5ms internal soft-start function and an open-drain power  Internal Soft-Start (1.5ms typ)
good indicator.  Built-in OVP/UVP/OCP
 Power Good Indicator
 Fixed 300kHz VCLK to Support Charge Pump
Applications  Individual EN for PWM and LDO
 Laptop Computers  Thermal Shutdown
 Tablet PCs
 Networking Systems
 Servers
 Personal Video Recorders
 Flat Panel Television and Monitors
 Distributed Power Systems

Simplified Application Circuit

D1 D2 D3 D4
VOUT VCP
C1 C2 C3 C4 C5

CLK RB
VIN VIN BOOT
CIN RT7291A/B CB L
EN
SW VOUT
VLDO LDO
CLDO COUT
VOUT
PGND
RBYP
VOUT VBYP RPGOOD
CBYP PGOOD VCC
VCC
ENLDO AGND CVCC

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RT7291A/B
Ordering Information Pin Configuration
RT7291A/B (TOP VIEW)

ENLDO
Package Type

AGND

BOOT
VCC
QUF : UQFN-16L 3x3 (FC) (U-Type)

EN
Lead Plating System 14 13 12 11 10

G : Green (Halogen Free and Pb Free)

VIN 1
Output Voltage 15 9 SW
A : 5V PGND 2 SW
16
Note : B : 5.1V 8 SW
SW
Richtek products are : 3 4 5 6 7

VBYP

CLK

VOUT
LDO
PGOOD
 RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
 Suitable for use in SnPb or Pb-free soldering processes. UQFN-16L 3x3 (FC)

Marking Information
RT7291AGQUF RT7291BGQUF
39= : Product Code 4M= : Product Code
39=YM YMDNN : Date Code 4M=YM YMDNN : Date Code
DNN DNN

Functional Pin Description

Pin No. Pin Name Pin Function
1 VIN Power input connect to high-side MOSFET drain.
2 PGND Power ground.
Switch over source voltage for VCC. A low pass filter should be connected to
3 VBYP AGND, if VBYP is applied. If VBYP is not used, then connect to AGND. Do not
connect to VCC pin.
This pin should be connected to a pull high voltage with a 100k resistor.
4 PGOOD Recommend to pull high by VCC (5V). DO NOT pull high to external voltage which
is higher than VCC (5V).
5 CLK 300kHz clock output to drive the external charge pump.
6 LDO 5V linear regulator output. Decouple with a minimum 4.7F ceramic capacitor.
7 VOUT Output voltage sense input. An internal discharging circuit is connected to this pin.
8, 9, 15, 16 SW Switch node.
Bootstrap supply for high-side gate driver. A capacitor is needed to drive the power
10 BOOT switch's gate above the supply voltage. It is connected between the SW and
BOOT pins to form a floating supply across the power switch driver.
5V linear regulator output for internal control circuit. A capacitor (typical 2.2F)
11 VCC should be connected to AGND. VCC can only supply internal circuits. Do not
connect to external loads.
Enable control input for linear regulator. This pin is internally pulled up to high by
12 ENLDO
10A.
13 EN Enable control input. Do not leave this pin floating.
14 AGND Analog ground.
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 RT7291A/B
Functional Block Diagram
VCC VBYP

VIN
POR &
Soft-Start VCC BSTREG BOOT
Reference
Switch-Over VIN
VOUT

+
VREF + On-Time
- One shot Gate
VFB SW
Control
Min off Time Logic VCC
EN

VOUT PGND

OCP
SW +
120% x VREF PGOOD
VOC -
- OVP Fault
+ Logic
90% x VREF - POK
AGND
+ UVP
60% x VREF +
-
VOUT
VCC VOUT
CLK LDO
CLK VCC LDO
Generator Control
Regulator Switch-Over

VIN ENLDO LDO

Operation
Overall OCP
The RT7291A/B is a synchronous step-down converter The inductor valley current is monitored via the internal
with advanced constant on-time control mode. Using the switches in cycle-by-cycle. Once the output voltage drops
ACOT® control mode can reduce the output capacitance below UV threshold, the device enters latch mode.
and provide fast transient response. It can minimize the
component size without additional external compensation Power Good
network. After soft-start is finished, the power good function will be
activated. The PGOOD pin is an open-drain output.
Internal VCC Regulator
The regulator provides 5V power to supply the internal CLK Generator
control circuit. Connecting a 2.2μF ceramic capacitor for Provide a 300kHz clock to drive external charge pump.
decoupling and stability is required.
VCC Switch-Over
Soft-Start The internal regulator output will switch over to VBYP if
In order to prevent the converter output voltage from VBYP level is higher than 4.6V.
overshooting during the startup period, the soft-start
LDO
function is necessary. The soft-start time is internal setting
and the duration is around 1.5ms Built-in 5V, 100mA LDO with 1% accuracy. The LDO output
will switch over to VOUT once PGOOD goes high.

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RT7291A/B
Absolute Maximum Ratings (Note 1)
 Supply Input Voltage, VIN ---------------------------------------------------------------------------------- −0.3V to 27V
 Switch Voltage, SW ----------------------------------------------------------------------------------------- −0.3V to (V IN + 0.3V)
<30ns ----------------------------------------------------------------------------------------------------------- −5V to 28V
 BOOT Switch Voltage --------------------------------------------------------------------------------------- (VSW − 0.3V) to (VSW + 6V)
 EN, ENLDO Pin Voltages ---------------------------------------------------------------------------------- −0.3V to 27V
 Other I/O Pin Voltages -------------------------------------------------------------------------------------- −0.3V to 6V
 Power Dissipation, PD @ TA = 25°C
UQFN-16L 3x3 (FC) ------------------------------------------------------------------------------------------ 1.4W
 Package Thermal Resistance (Note 2)
UQFN-16L 3x3 (FC), θJA ------------------------------------------------------------------------------------ 70°C/W
UQFN-16L 3x3 (FC), θJC ------------------------------------------------------------------------------------ 15°C/W
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
 Junction Temperature ---------------------------------------------------------------------------------------- 150°C
 Storage Temperature Range ------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------- 2kV
MM (Machine Model) ---------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

 Supply Input Voltage, VIN ---------------------------------------------------------------------------------- 5V to 23V
 Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Current
Shutdown Current VEN = VENLDO = 0V -- 2.5 5 A
Quiescent Current VEN = 2V, VENLDO = 2V, no switching -- 100 130 A
VEN = 0V, VENLDO = 2V, LDO load
Standby Current -- 35 45 A
current = 0A
Switch On-Resistance
RDS(ON)_H VBOOT – VSW = 5V -- 31 --
Switch On-Resistance m
RDS(ON)_L -- 20 --
Current Limit
Current Limit IOC Valley current of low-side switch 7.6 -- 11.4 A
Switching Frequency and Minimum Off Timer
Switching Frequency f SW 450 500 550 kHz
Minimum Off-Time tOFF_MIN -- 200 -- ns
Protections
OVP Trip Threshold VOVP With respect to output voltage 115 120 125 %
OVP Propagation Delay TOVPDLY -- 5 -- s

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 RT7291A/B
Parameter Symbol Test Conditions Min Typ Max Unit
UVP Trip Threshold VUVP With respect to output voltage 55 60 65 %
UVP Propagation Delay TUVPDLY -- 5 -- s
Reference and Soft-Start
RT7291A 4.95 5 5.05
Output Voltage Valley VOUT V
RT7291B 5.049 5.1 5.151
Soft-Start Time TSS From EN high to PGOOD high 1 1.5 2 ms
Enable and UVLO
RT7291A 1.25 1.35 1.45
EN Input High Voltage VENH V
RT7291B 1.3 1.4 1.5
EN Hysteresis VENHYS -- 200 -- mV
VEN = 2V -- 1 --
EN Input Current IEN A
VEN = 0V -- 0 --
VCC UVLO Rising VCCUVLO -- 4.2 -- V
VCC UVLO Hysteresis VCCHYS -- 400 -- mV
CLK Output
RT7291A -- -- 5.05
CLK Output High-Level VCLKH IVCLK = 10mA
RT7291B -- -- 5.151 V
Voltage
Low-Level VCLKL IVCLK = 10mA 0 0.1 0.2
CLK Frequency f CLK -- 300 -- kHz
LDO Regulator
RT7291A 4.95 5 5.05
LDO Regulator VLDO V
RT7291B 5.049 5.1 5.151
EN = GND,
-- 1 --
LDO load current = 5mA
LDO Load Regulation %
EN = GND,
-- 5 --
LDO load current = 100mA
Switch On-Resistance RSW -- 3 5 
VCC Regulator
RT7291A 4.805 5 5.295
VCC Regulator VVCC V
RT7291B 4.905 5.1 5.395

VCC Switch Over Threshold to RT7291A 4.45 4.6 4.75

VBYP rising edge V
VBYP RT7291B 4.542 4.692 4.842
VCC Switch Over Hysteresis VBYP falling edge -- 200 -- mV
Switch Over On-Resistance -- 3 5 

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RT7291A/B
Parameter Symbol Test Conditions Min Typ Max Unit
Power Good Indicator
PGOOD Threshold From Lower VOUT rising 85 90 95 %
PGOOD Low Hysteresis VOUT falling -- 10 -- %
PGOOD Low to High Delay TPGDLY -- 0.5 -- ms
PGOOD Sink Current Capability VPGSINK Sink 4mA -- -- 0.4 V
PGOOD Leakage Current IPGLEAK VPGOOD = 5V -- -- 100 nA
Thermal Shutdown
Thermal Shutdown Threshold TSD 135 150 -- °C
Thermal Shutdown Hysteresis -- 25 -- °C

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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 RT7291A/B
Typical Application Circuit

D1 D2 D3 D4
VOUT VCP
C1 C2 C3 C4 C5
100nF 100nF 100nF 100nF 100nF
/ 50V / 50V / 50V / 50V / 50V

5 RB
VIN CLK 2.2
1 BOOT 10
VIN
5.2V to 23V CIN CB
RT7291A/B
10µF 13 0.1µF / 50V
/25V x 2 EN
L
8, 9, 15, 16 VOUT
VLDO 6 SW
LDO 1.5µH 5V/6A
5V CLDO COUT
4.7µF /10V VOUT 7 22µF /
2 6.3V x 4
PGND
RBYP
5.1 3 14
VOUT VBYP AGND
CBYP
2.2µF / RPGOOD
10V 100k
PGOOD 4 VCC
12 ENLDO VCC 11
CVCC
2.2µF /
10V

Figure 1. Typical Application Circuit with Pure MLCC Solution

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RT7291A/B
Typical Operating Characteristics
Efficiency vs. Load Current Efficiency vs. Load Current
100 100
VIN = 7.4V, EN = 2V, ENLDO = floating VIN = 12V, EN = 2V, ENLDO = floating

95
95

Efficiency (%)
Efficiency (%)

90

90 85

80
85
75

80 70
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Load Current (A) Load Current (A)

Efficiency vs. Load Current Switching Frequency vs. Load Current

100 550
VIN = 19V, EN = 2V, ENLDO = floating VIN = 7.4V, EN = 2V, ENLDO = floating
Switching Frequency (kHz)1

500
95 450
400
Efficiency (%)

90
350
300
85
250
200
80
150

75 100
50
70 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Load Current (A) Load Current (A)

Switching Frequency vs. Load Current Switching Frequency vs. Load Current
550 550
VIN = 12V, EN = 2V, ENLDO = floating VIN = 19V, EN = 2V, ENLDO = floating
Switching Frequency (kHz)1

500 500
Switching Frequency (kHz)1

450 450
400 400
350 350
300 300
250 250
200 200
150 150
100 100
50 50
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Load Current (A) Load Current (A)

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 RT7291A/B

Quiescent Current vs. Input Voltage Standby Current vs. Input Voltage
100 80
90 70
Quiescent Current (µA) 1

80

Standby Current (µA)

60
70
60 50

50 40
40 30
30
20
20
10 10
EN = 2V, ENLDO = floating, No Switching EN = 0V, ENLDO = 2V, ILDO = 0A
0 0
5 7 9 11 13 15 17 19 21 23 5 7 9 11 13 15 17 19 21 23
Input Voltage (V) Input Voltage (V)

Shutdown Current vs. Input Voltage Output Voltage vs. Load Current
10 5.25

9 5.20
Shutdown Current (µA)1

8 5.15
Output Voltage (V)

7 5.10

6 5.05

5 5.00

4 4.95

3 4.90
2 4.85

1 4.80
EN = ENLDO = 0V VIN = 12V, EN = 2V, ENLDO = floating
0 4.75
5 7 9 11 13 15 17 19 21 23 0.001 0.01 0.1 1 10
Input Voltage (V) Load Current (A)

LDO Output Voltage vs. Input Voltage Start Up Through EN

5.25
5.20
VOUT
LDO Output Voltage (V)

5.15
(5V/Div)
5.10
5.05
V CC
5.00 (5V/Div)
4.95 PGOOD
(5V/Div)
4.90
ILDO = 0mA
4.85 ILDO = 50mA EN
4.80 ILDO = 100mA (5V/Div)
VIN = 12V, ENLDO = GND, No Load
4.75
4 6 8 10 12 14 16 18 20 22 24 Time (500μs/Div)
Input Voltage (V)

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RT7291A/B

Start Up Through ENLDO Power Off Through EN

VLDO
(5V/Div) VOUT
(5V/Div)

V CC V CC
(5V/Div) (5V/Div)
VCP
(5V/Div)
PGOOD
(5V/Div)
ENLDO EN
(5V/Div) (5V/Div)
VIN = 12V, EN = GND, No Load VIN = 12V, ENLDO = GND, No Load

Time (500μs/Div) Time (500μs/Div)

Power Off Through ENLDO Load Transient Response

VLDO VOUT
(5V/Div) (30mV/Div)

V CC
(5V/Div)
VCP SW
(5V/Div) (20V/Div)

ENLDO IL
(5V/Div) (5A/Div)
VIN = 12V, EN = GND, No Load VIN = 12V, EN = ENLDO = High

Time (500μs/Div) Time (50μs/Div)

UVP OVP
VIN = 12V, EN = ENLDO = High

VOUT VOUT
(5V/Div) (5V/Div)

PGOOD PGOOD
(5V/Div) (5V/Div)

VIN
(10V/Div)
SW IL
(10V/Div) (5A/Div)
VIN = 12V, VOUT = 6V, EN = ENLDO = High

Time (50μs/Div) Time (50μs/Div)

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 RT7291A/B
Application Information
The RT7291A/B is high-performance 500kHz 6A step-down the actual output voltage, potentially saving one pin
regulators with internal power switches and synchronous connection. The ACOT® uses this method, measuring
rectifiers. It features an Advanced Constant On-Time the actual switching frequency and modifying the on-time
(ACOT®) control architecture that provides stable operation with a feedback loop to keep the average switching
for ceramic output capacitors without complicated external frequency in the desired range.
compensation, among other benefits. The input voltage
range is from 5V to 23V, and the output voltage is fixed ACOT® One-shot Operation
5V. The RT7291A/B control algorithm is simple to understand.
The feedback voltage, with the virtual inductor current ramp
The proprietary ACOT ® control scheme improves
added, is compared to the reference voltage. When the
conventional constant on-time architectures, achieving
combined signal is less than the reference, the on-time
nearly constant switching frequency over line, load, and
one-shot is triggered, as long as the minimum off-time
output voltage ranges. Since there is no internal clock,
one-shot is clear and the measured inductor current
response to transients is nearly instantaneous and inductor
(through the synchronous rectifier) is below the current
current can ramp quickly to maintain output regulation
limit. The on-time one-shot turns on the high-side switch
without large bulk output capacitance.
and the inductor current ramps up linearly. After the on-
ACOT® Control Architecture time, the high-side switch is turned off and the synchronous
In order to achieve good stability with low-ESR ceramic rectifier is turned on and the inductor current ramps down
capacitors, ACOT® uses a virtual inductor current ramp linearly. At the same time, the minimum off-time one-shot
generated inside the IC. This internal ramp signal replaces is triggered to prevent another immediate on-time during
the ESR ramp normally provided by the output capacitor's the noisy switching time and allow the feedback voltage
ESR. The ramp signal and other internal compensations and current sense signals to settle. The minimum off-time
are optimized for low-ESR ceramic output capacitors. is kept short (200ns typical) so that rapidly-repeated on-
times can raise the inductor current quickly when needed.
Making the on-time proportional to VOUT and inversely
proportional to VIN is not sufficient to achieve good Diode Emulation Mode
constant-frequency behavior for several reasons. First, In diode emulation mode, the RT7291A/B automatically
voltage drops across the MOSFET switches and inductor reduces switching frequency at light load conditions to
cause the effective input voltage to be less than the maintain high efficiency. This reduction of frequency is
measured input voltage and the effective output voltage to achieved smoothly. As the output current decreases from
be greater than the measured output voltage as sensing heavy load conditions, the inductor current is also reduced,
input and output voltage. When the load changes, the and eventually comes to the point that its current valley
switch voltage drops change causing a switching touches zero, which is the boundary between continuous
frequency variation with load current. Also, at light loads conduction and discontinuous conduction modes. To
if the inductor current goes negative, the switch dead- emulate the behavior of diodes, the low-side MOSFET
time between the synchronous rectifier turn-off and the allows only partial negative current to flow when the
high-side switch turn-on allows the switching node to rise inductor free wheeling current becomes negative. As the
to the input voltage. This increases the effective on-time load current is further decreased, it takes longer and longer
and causes the switching frequency to drop noticeably. time to discharge the output capacitor to the level that
One way to reduce these effects is to measure the actual requires the next “ON” cycle. In reverse, when the output
switching frequency and compare it to the desired range. current increases from light load to heavy load, the
This has the added benefit eliminating the need to sense switching frequency increases to the preset value as the

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RT7291A/B
inductor current reaches the continuous conduction. The When VOUT is powered on and PGOOD is pulled high,
transition load point to the light load operation is shown in an internal 3Ω P-MOSFET switch connects VOUT to the
Figure 2 and can be calculated as follows : LDO pin while the internal linear regulator is simultaneously
IL turned off.
The RT7291A/B also includes a 5V linear regulator (VCC).
Slope = (VIN - VOUT) / L
IPEAK The VCC regulator steps down input voltage to supply
both internal circuitry and gate drivers. Do not connect
the VCC pin to external loads. When PGOOD is pulled
ILOAD = IPEAK / 2
high and BYP pin voltage is above 4.6V, an internal 3Ω
P-MOSFET switch connects VCC to the BYP pin while
t
the VCC linear regulator is simultaneously turned off.
tON

Figure 2. Boundary Condition of CCM/DEM Current Limit

The RT7291A/B current limit is a cycle-by-cycle “valley”
(V  VOUT ) type, measuring the inductor current through the
ILOAD  IN  tON
2L synchronous rectifier during the off-time while the inductor
where tON is the on-time.
current ramps down. The current is determined by
The switching waveforms may appear noisy and measuring the voltage between Source and Drain of the
asynchronous when light load causes diode emulation synchronous rectifier, adding temperature compensation
operation. This is normal and results in high efficiency. for greater accuracy. If the current exceeds the current
Trade offs in DEM noise vs. light load efficiency is made limit, the on-time one-shot is inhibited until the inductor
by varying the inductor value. Generally, low inductor values current ramps down below the current limit. Thus, only
produce a broader efficiency vs. load curve, while higher when the inductor current is well below the current limit,
values result in higher full load efficiency (assuming that another on-time is permitted. If the output current exceeds
the coil resistance remains fixed) and less output voltage the available inductor current (controlled by the current
ripple. Penalties for using higher inductor values include limit mechanism), the output voltage will drop. If it drops
larger physical size and degraded load transient response below the output under-voltage protection level (see next
(especially at low input voltage levels). section), the IC will stop switching to avoid excessive
During discontinuous switching, the on-time is immediately heat.
increased to add “hysteresis” to discourage the IC from The RT7291A/B also features a negative current limit to
switching back to continuous switching unless the load protect the IC against sinking excessive current and
increases substantially. The IC returns to continuous possibly damage. If the voltage across the synchronous
switching as soon as an on-time is generated before the rectifier indicates the negative current is too high, the
inductor current reaches zero. The on-time is reduced back synchronous rectifier turns off.
to the length needed for 500kHz switching and encouraging
the circuit to remain in continuous conduction, preventing Output Over-Voltage Protection and Under-Voltage
repetitive mode transitions between continuous switching Protection
and discontinuous switching. The RT7291A/B features an output Over-Voltage Protection
(OVP). If the output voltage rises above the regulation
Linear Regulators (LDO & VCC) level, the IC stops switching and is latched off. The
The RT7291A/B includes a 5V linear regulator (LDO). The RT7291A/B also features an output Under-Voltage
LDO regulator can supply up to 100mA for external loads. Protection (UVP). If the output voltage drops below the
Bypass LDO with a minimum 4.7μF ceramic capacitor. UVP trip threshold for longer than 2μs (typical), the UVP

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 RT7291A/B
is triggered, and the IC will shut down. The IC stops Soft-Start
switching and is latched off. To restart operation, toggle The RT7291A/B provides an internal soft-start function to
EN or power the IC off and then on again. prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
Input Under-Voltage Lockout
automatically begins once the chip is enabled. During soft-
In addition to the enable function, the RT7291A/B features start, it clamps the ramp of internal reference voltage which
an Under-Voltage Lockout (UVLO) function that monitors is compared with FB signal. The typical soft-start duration
the input voltage. To prevent operation without fully- is 1.5ms.
enhanced internal MOSFET switches, this function inhibits
switching when input voltage drops below the UVLO-falling Power Off
threshold. The IC resumes switching when input voltage When VEN is pulled to GND or lower than the logic-low
exceeds the UVLO-rising threshold. level of 1.15V, there is an internal discharging resistor to
discharge the residual charge inside the output capacitors.
Over-Temperature Protection
Besides, the value of discharging resistor is about twenty
The RT7291A/B features an Over-Temperature Protection ohms.
(OTP) circuitry to prevent overheating due to excessive
power dissipation. The OTP shuts down switching Power Good Output (PGOOD)
operation when the junction temperature exceeds 150°C. The power good output is an open-drain output that requires
Once the junction temperature cools down by a pull-up resistor. When the output voltage is 20% (typical)
approximately 25°C the IC resumes normal operation with below its set voltage, PGOOD will be pulled low. It is held
a complete soft-start. For continuous operation, provide low until the output voltage returns to 90% of its set voltage
adequate cooling so that the junction temperature does once more. During soft-start, PGOOD is actively held low
not exceed 150°C. Note that the VCC and LDO regulator and only allowed to be pulled high after soft-start is over
remains on as the OTP is triggered. and the output reaches 90% of its set voltage. There is a
2μs delay built into PGOOD circuitry to prevent false
Enable and Disable
transition.
The enable input (EN) has a logic-low level of 1.15V. When
In addition, the PGOOD open drain driver is supplied by
VEN is below this level, the IC enters shutdown mode and
VCC power source or VBYP pin voltage source in switch-
supply current drops to less than 5μA (typical). When
over mode. When both EN and ENLDO are pulled low, the
VEN exceeds its logic-high level of 1.35V, the IC is fully
VCC starts to discharge, and the pull-low strength of
operational. The logics of EN and ENLDO to control the
PGOOD open drain driver decreases after VCC voltage is
VOUT, CLK, LDO and VCC are stated in Table 1.
lower than VCC_POR threshold (typ. = 3.8V). As a result,
Table 1. EN/ENLDO Control Logics the PGOOD pin is floated and pulled up by external voltage
EN ENLDO VOUT/CLK LDO VCC source. In consideration of PGOOD status after EN &
ENLDO power off, it is recommended that connecting
1 1 ON ON ON
PGOOD pin with a 100kΩ resistor to VCC (5V). DO NOT
1 0 ON ON ON
pull high to external voltage which is higher than VCC
0 1 OFF ON ON (5V).
0 0 OFF OFF OFF
External Bootstrap Capacitor (CBOOT)
Connect a 0.1μF low ESR ceramic capacitor between the
BOOT and SW pins. This bootstrap capacitor provides
the gate driver supply voltage for the high-side N-MOSFET
switch.

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RT7291A/B
The internal power MOSFET switch gate driver is maintain control of inductor current in overload and short-
optimized to turn the switch on fast enough for low power circuit conditions, some applications may desire current
loss and good efficiency, and slow enough to reduce EMI. ratings up to the current limit value. However, the IC's
Switch turn-on is when most EMI occurs since VSW rises output under-voltage shutdown feature make this
rapidly. During switch turn-off, SW is discharged relatively unnecessary for most applications.
slowly by the inductor current during the dead-time For best efficiency, choose an inductor with a low DC
between high-side and low-side switch on-times. In some resistance that meets the cost and size requirements.
cases it is desirable to reduce EMI further, at the expense For low inductor core losses some type of ferrite core is
of some additional power dissipation. The switch turn-on usually best and a shielded core type, although possibly
can be slowed by placing a small (<10Ω) resistance larger or more expensive, it will probably give fewer EMI
between BOOT and the external bootstrap capacitor. This and other noise problems.
will slow the high-side switch turn-on and VSW's rise.
Input Capacitor Selection
Inductor Selection
High quality ceramic input decoupling capacitor, such as
Selecting an inductor involves specifying its inductance X5R or X7R, with values greater than 20μF are
and also its required peak current. The exact inductor value recommended for the input capacitor. The X5R and X7R
is generally flexible and is ultimately chosen to obtain the ceramic capacitors are usually selected for power regulator
best mix of cost, physical size, and circuit efficiency. capacitors because the dielectric material has less
Lower inductor values benefit from reduced size and cost capacitance variation and more temperature stability.
and they can improve the circuit's transient response. Voltage rating and current rating are the key parameters
However, they increase the inductor ripple current and when selecting an input capacitor. Generally, selecting an
output voltage ripple and reduce the efficiency due to the input capacitor with voltage rating 1.5 times greater than
resulting higher peak currents. Conversely, higher inductor the maximum input voltage is a conservatively safe design.
values increase efficiency, but the inductor will either be The input capacitor is used to supply the input RMS
physically larger or have higher resistance since more current, which can be approximately calculated using the
turns of wire are required and transient response will be following equation :
slower since more time is required to change current (up
VOUT  V I 2 
or down) in the inductor. A good compromise between IRMS   (1  OUT )  IOUT 2  L 
VIN  VIN 12 
size, efficiency, and transient response is to use a ripple
The next step is to select a proper capacitor for RMS
current (ΔIL) about 20-50% of the desired full output load
current rating. One good design uses more than one
current. Calculate the approximate inductor value by
capacitor with low Equivalent Series Resistance (ESR) in
selecting the input and output voltages, the switching
parallel to form a capacitor bank. The input capacitance
frequency (fSW), the maximum output current (IOUT(MAX))
value determines the input ripple voltage of the regulator.
and estimating a ΔIL as some percentage of that current.
The input voltage ripple can be approximately calculated
V  (VIN  VOUT )
L  OUT using the following equation :
VIN  fSW  IL
IOUT  VIN V
VIN   (1  OUT )
Once an inductor value is chosen, the ripple current (ΔIL) CIN  fSW  VOUT VIN
is calculated to determine the required peak inductor The typical operating circuit is recommended to use two
current. 10μF low ESR ceramic capacitors on the input.
V  (VIN  VOUT ) I
IL  OUT and IL(PEAK)  IOUT(MAX)  L
VIN  fSW  L 2 Output Capacitor Selection
To guarantee the required output current, the inductor The RT7291A/B is optimized for ceramic output capacitors
needs a saturation current rating and a thermal rating that and best performance will be obtained by using them. The
exceeds IL(PEAK). These are minimum requirements. To total output capacitance value is usually determined by

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 RT7291A/B
the desired output voltage ripple level and transient response (neglecting parasitics) and maximum duty cycle for a given
requirements for sag (undershoot on positive load steps) input and output voltage as :
and soar (overshoot on negative load steps). VOUT t ON
tON  and DMAX 
VIN  fSW tON  tOFF_MIN
Output ripple at the switching frequency is caused by the
The actual on-time will be slightly longer as the IC
inductor current ripple and its effect on the output
compensates for voltage drops in the circuit, but we can
capacitor's ESR and stored charge. These two ripple
neglect both of these since the on-time increases
components are called ESR ripple and capacitive ripple.
compensations for the voltage losses. Calculate the output
Since ceramic capacitors have extremely low ESR and
voltage sag as :
relatively little capacitance, both components are similar
in amplitude and both should be considered if ripple is L  (IOUT )2
VSAG 
critical. 2  COUT  ( VIN(MIN)  DMAX  VOUT )
VRIPPLE  VRIPPLE(ESR)  VRIPPLE(C) The amplitude of the capacitive soar is a function of the
VRIPPLE(ESR)  IL  RESR load step, the output capacitor value, the inductor value
IL and the output voltage :
VRIPPLE(C) 
8  COUT  fSW L  ( IOUT )2
VSOAR 
In addition to voltage ripple at the switching frequency, 2  COUT  VOUT
the output capacitor and its ESR also affect the voltage Most applications never experience instantaneous full load
sag (undershoot) and soar (overshoot) when the load steps steps and the RT7291A/B's high switching frequency and
up and down abruptly. The ACOT® transient response is fast transient response can easily control voltage regulation
very quick and output transients are usually small. at all times. Therefore, sag and soar are seldom an issue
However, the combination of small ceramic output except in very low-voltage CPU core or DDR memory
capacitors (with little capacitance), low output voltages supply applications, particularly for devices with high clock
(with little stored charge in the output capacitors), and frequencies and quick changes into and out of sleep
low duty cycle applications (which require high inductance modes. In such applications, simply increasing the amount
to get reasonable ripple currents with high input voltages) of ceramic output capacitor (sag and soar are directly
increases the size of voltage variations in response to proportional to capacitance) or adding extra bulk
very quick load changes. Typically, load changes occur capacitance can easily eliminate any excessive voltage
slowly with respect to the IC's 500kHz switching frequency. transients.
However, some modern digital loads can exhibit nearly In any application with large quick transients, it should
instantaneous load changes and the following section calculate soar and sag to make sure that over-voltage
shows how to calculate the worst-case voltage swings in protection and under-voltage protection will not be triggered.
response to very fast load steps.
The amplitude of the ESR step up or down is a function of Thermal Considerations
the load step and the ESR of the output capacitor : For continuous operation, do not exceed absolute
VESR_STEP  IOUT  RESR maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
The amplitude of the capacitive sag is a function of the
package, PCB layout, rate of surrounding airflow, and
load step, the output capacitor value, the inductor value,
difference between junction and ambient temperature. The
the input-to-output voltage differential, and the maximum
maximum power dissipation can be calculated by the
duty cycle. The maximum duty cycle during a fast transient
following formula :
is a function of the on-time and the minimum off-time since
the ACOT® control scheme will ramp the current using PD(MAX) = (TJ(MAX) − TA) / θJA
on-times spaced apart with minimum off-times, which is where TJ(MAX) is the maximum junction temperature, TA is
as fast as allowed. Calculate the approximate on-time the ambient temperature, and θJA is the junction to ambient

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RT7291A/B
thermal resistance. Layout Considerations
For recommended operating condition specifications, the Layout is very important in high frequency switching
maximum junction temperature is 125°C. The junction to converter design. The PCB can radiate excessive noise
ambient thermal resistance, θJA, is layout dependent. For and contribute to converter instability with improper layout.
UQFN-16L 3x3 (FC) package, the thermal resistance, θJA, Certain points must be considered before starting a layout
is 70°C/W on a standard JEDEC 51-7 four-layer thermal using the RT7291A/B.
test board. The maximum power dissipation at TA = 25°C  Make traces of the main current paths as short and wide
can be calculated by the following formula : as possible.
P D(MAX) = (125°C − 25°C) / (70°C/W) = 1.4W for  Put the input capacitor as close as possible to the device
UQFN-16L 3x3 (FC) package pins (VIN and PGND).
The maximum power dissipation depends on the operating  SW node encounters high frequency voltage swings so
ambient temperature for fixed T J(MAX) and thermal it should be kept in a small area. Keep sensitive
resistance, θJA. The derating curve in Figure 3 allows the components away from the SW node to prevent stray.
designer to see the effect of rising ambient temperature
 The PGND pin should be connected to a strong ground
on the maximum power dissipation.
plane for heat sinking and noise protection.
2.0
Avoid using vias in the power path connections that have
Maximum Power Dissipation (W)1


Four-Layer PCB
switched currents (from CIN to PGND and CIN to VIN)
1.6
and the switching node (SW).

1.2

0.8

0.4

0.0
0 25 50 75 100 125
Ambient Temperature (°C)

Figure 3. Derating Curve of Maximum Power Dissipation

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 RT7291A/B

GND
VIN CVCC

ENLDO
AGND

BOOT
VCC
EN
1 1 1 1 1
The input capacitor must
4 3 2 1 0
be placed as close to the
IC as possible. CBOOT The output capacitor must
be placed near the IC
VIN 1
L VOUT
15 9 SW
CIN SW
PGND 2
16 COUT
8 SW
SW

SW should be connected to
3 4 5 6 7
inductor by wide and short
trace.
PGOOD
VBYP

LDO

VOUT
CLK

GND VOUT Keep sensitive components

away from this trace.
CLDO

Impedance between PGND and AGND should be as small as possible for unified ground voltage.

Figure 4. Layout Guide

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RT7291A/B
Outline Dimension

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.500 0.600 0.020 0.024
A1 0.000 0.050 0.000 0.002
A3 0.100 0.200 0.004 0.008
D 2.900 3.100 0.114 0.122
E 2.900 3.100 0.114 0.122
b 0.150 0.250 0.006 0.010
b1 0.100 0.200 0.004 0.008
L 0.350 0.450 0.014 0.018
L1 0.750 0.850 0.030 0.033
L2 0.550 0.650 0.022 0.026
e 0.400 0.016
K 0.975 0.038
K1 1.335 0.053
K2 1.675 0.066
K3 1.935 0.076
K4 0.975 0.038
K5 1.675 0.066

U-Type 16L QFN 3x3 (FC) Package

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 RT7291A/B

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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