Digital IC Design Practicum (EE519P)

Lab Report

Submitted to:
Dr. Rahul Shrestha
School of Computing and Electrical Engineering
Indian Institute of Technology Mandi

Submitted by:
GAURAV SHARMA
Roll Number: T23212
CHANDAN SINGH
Roll Number: T23219

December 5, 2023

1
 Table of Contents

1. I-V Characteristics of NMOS and PMOS

2. Study and analysis of CMOS Inverter

3. Delay Optimization using Chain of Inverter
4. Design and Analysis of CMOS NAND & AND gate

5. Design and Analysis of CMOS NOR & OR gate

6. Design and Analysis of CMOS XOR & XNOR gate
7. Design of Logic Gates Using Pseudo NMOS Logic
8. Design of Logic Gates using DCVSL

9. Design of Logic Gates using PTL

10. Design of Logic Gates using CPL
11. Design and Analysis of a Custom 4-Transistor XOR Gate

12. Transmission Gate Logic Design

13. Design of Static D Latch and Master-Slave Flip-Flop
14. TG and PTL Based Dynamic Sequential Logic

1
Design a NMOS and PMOS transistor circuit using
virtuoso cadence and plot I-V characteristics of
PMOS and NMOS for different gate and drain
voltages
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: To Determine Various Parameter Of NMOS And B. PMOS:

PMOS Transistors.
In PMOS technology, holes are the dominant carriers and
Abstract—This study involves the simulation of NMOS electrons are the minority, and the device works in the
and PMOS transistor circuits using the Cadence Virtuoso tool, same way as an n-channel device, with positive vsg and vsd
focusing on the analysis of the current-voltage diagram of the values and a negative threshold voltage VTH. Current, Id,
transistors. The study involves determining the threshold voltage enters through the source terminal and exits through the drain
and drain current behavior.
terminal. PMOS was originally the preferred technology for
Index Terms—THRESHOLD VOLTAGE,PMOS, LINEAR RE- MOS fabrication, but faster and smaller NMOS devices, which
GION,NMOS require lower voltages, have become more common. However,
it is still important to understand PMOS transistors for two
reasons.
I. I NTRODUCTION
A PMOS Transistor Symbol is shown in Figure 2.
A. NMOS:
The Metal-Oxide-Semiconductor Field-Effect Transistor
(MOSFET) is a device with four terminals referred to as Gate
(G), Drain (D), Source (S), and Bulk (B).

A N-type MOS Symbol is given in Figure 1.

Fig. 2.

C. TRANSISTORS SCHEMATICS
1) NMOS TRANSISTOR CIRCUIT:: NMOS Circuit is shown
in Fig.3
Fig. 1.
2) PMOS TRANSISTOR CIRCUIT: NMOS Circuit is shown
An NMOS transistor, a type of MOSFET, has four terminals in Fig.4
called drain, gate, source and body which are symmetrical
II. WORKING PRINCIPLE
in nature. Its body consists of p-type semiconductor material
and drain, source consists of n-type semiconductor material. A. CURRENT VOLTAGE PLOTS OF NMOS and PMOS
When a higher voltage is applied to the gate, the electrons in 1) NMOS Ids v/s Vds plot for different values of Vgs .: N type
the semiconductor substrate are attracted to the gate, resulting transistor can be observed by analyzing its current-voltage
in the formation of a conducting channel. (I − V ) characteristics. These characteristics indicate how
 Fig. 3. NMOS schematic

Fig. 5. NMOS I-V curve for different Vgs in cadence virtuoso

Fig. 4. PMOS schematic

the (Id ) varies with (Vgs ) and (Vds ). The I-V characteris-
tics can be divided into four regions: cutoff, subthreshold,
triode/ohmic, and saturation. When transistor operate in cutoff
region it is in off state and there is no drain current. In the
subthreshold region, the transistor is still off, but there is a
small leakage current. The triode/ohmic region is where the
transistor operates in a linear mode, acting as a variable resistor Fig. 6. PMOS I-V curve with different Vsd in cadence virtuoso
and suitable for amplification. The saturation region is where
the transistor is fully turned on, acting as a current source and
used for switching and maintaining a constant current. These 3) SATURATION REGION:: When(VDS > VGS − Vth ) then
characteristics are crucial for optimizing circuit performance the transistor will operates in this region and the current
and functionality. equation is given bellow
B. Transfer Characteristics 1 W
IDS,sat = µn Cox (VGS − V th)2 (1 + λVDS ) (3)
The transfer characteristics of an NMOS can be derived by 2 L
plotting a curve between the drain current Ids and gate-source FOR PMOS TRANSISTOR:
voltage Vgs . This curve indicates that when Vgs is below the
threshold voltage Vth , no channel is induced and the drain
4) CUT-OFF REGION:: The current equation in
current is zero.
cutoff(|VGS | < Vth given by
C. Equations ID = 0 (4)
FOR NMOS TRANSISTOR:
5) TRIODE/LINEAR REGION:: The current equation in tri-
1) CUT-OFF REGION:: The current equation in cutoff ode region given by
2
 
VGS < Vth given by W VSD
ID = 0 (1) ISD = µp Cox 2 (VSG − V th) VSD − (5)
L 2
2) TRIODE/LINEAR REGION:: The current equation for this 6) SATURATION REGION:: The current equation in satura-
region is given below tion region(VDS > VGS − Vth ) given by
1 W 2 1 W
IDS = µn Cox (VGS − V th) (2) ISD = µp Cox (VSG − V th)2 (1 + λVSD ) (6)
2 L 2 L
 Fig. 9. PMOS I-V curve for different Vsg in cadence virtuoso
Fig. 7. NMOS I-V curve for different Vds in cadence virtuoso

5) Transconductance (Gm ):
1 W
IDS,sat = µn Cox (VGS − V th)2 (1 + λVDS ) (11)
2 L
6) Threshold Voltage(Vtho ):
(12)

NMOS µn Cox RON λ gm ro

Simulated 187.93 µA V−2 3.244 kΩ 0.229 V−1 0.198 mA/V 50.90 kΩ

PMOS µp Cox RON λ gm ro

Simulated 108.097 µA V−2 3.513 kΩ 0.374 V−1 0.1405 mA/V 42.35 kΩ

Fig. 8. NMOS I-V curve with Vth plot

III. SIMULATION RESULTS

1) LINEAR ON RESISTANCE(RON ):
∂VDS
RON = (7)
∂ID
2) Channel Length Modulation Resistance(rO ):
∂VDS
ro = (8)
∂ID
3) Channel Length Modulation(λ):
1 W
IDS,sat = µn Cox (VGS − V th)2 (1 + λVDS ) (9)
2 L
4) Process Parameter(µn Cox ): Fig. 10. NMOS I-V curve for different Vsg with gm in cadence virtuoso

1 W 2
IDS = µn Cox (VGS − V th) (10)
2 L
 Fig. 11. NMOS I-V curve for different Vds with Ron and ro .

Fig. 12. PMOS I-V curve for different Vds with Ron and ro .

IV. C ONCLUSION :
• The layout for both NMOS and PMOS has been success-
fully created using the Cadence Virtuoso tool.
• We used TSMCN28nm Technology in CADENCE VIR-
TUOSO TOOL
• We Analyzed and calculated various parameter of NMOS
and PMOS Transistors
V. REFERENCES
[1] Weste, Neil HE, and David Harris. CMOS VLSI design:
a circuits and systems perspective. Pearson Education India,
2015.
[2] Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje
Nikoli´ c. Digital integrated circuits: a design perspective. Vol.
7. Upper Saddle River, NJ: Pearson education, 2003.
 Study and Analysis Of CMOS Inverter
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: The purpose of this study is to examine the properties 1) Propagation Delay (tp ):
of a CMOS inverter by means of simulations and analysis. This is the time taken for the output voltage to change
This includes exploring the VTC, delay, noise margin, and from 50 % of its final value to 50% of the new value
power consumption.
in response to a step change in the input voltage.
Abstract—This report presents a comprehensive analysis Propagation delay is a critical metric for assessing the
of inverter performance, focusing on key parameters such as speed of digital circuits.
delay, noise margin and power consumption. Inverters are the 2) Rise Time (tr ):
main building blocks of digital circuits and their efficiency Rise time is the time taken for the output voltage to
is critical to the overall efficiency of electronic systems. The
reference characteristics of inverters are investigated in terms of transition from 20% to 80% of its final value during
rise time, fall time and propagation delay. The study examines a rising input signal. It is an important parameter in
how changes in transistor size, load capacitance, and technology determining how fast the output voltage rises in response
scaling affect these delay meters. Noise margin, another critical to an input change.
aspect of inverter performance, is analyzed to assess the 3) Fall Time (tf ):
resistance of the circuit to external disturbances and variations
in input signals. Power consumption is a major concern in Fall time is the time taken for the output voltage to
today’s electronic equipment, and this study examines the power transition from 80% to 20% of its final value during
characteristics of inverters. The effect of different design choices a falling input signal. Similar to rise time, fall time is
on static and dynamic energy consumption is examined. crucial for evaluating the speed of the inverter during a
Index Terms—voltage transfer characteristics(VTC), inverter falling input transition.
delay, noise margin, Power.

I. INTRODUCTION
A. VTC of inverter:
The Voltage-Transfer Characteristic (VTC) of an inverter C. Power Consumption:
is a graphical representation of its input and output voltage
relationship. It illustrates how the output voltage of the in- The power consumption of a CMOS (Complementary
verter changes in response to variations in the input voltage. Metal-Oxide-Semiconductor) inverter consists of two main
Typically, a VTC is a plot of the output voltage against the components: static power (or standby power) and dynamic
input voltage for the inverter. power.
For a standard CMOS (Complementary Metal-Oxide-
Semiconductor) inverter, the VTC exhibits a characteristic 1) Static Power (Pstatic ):
shape. The inverter operates in two regions on the VTC: the Static power consumption occurs when the inverter is in
”low” state and the ”high” state. In the low state, the input a stable state, and there is no change in the input signal.
voltage is low, and the output voltage is high. It is primarily due to leakage currents in the transistors.
In the high state, the input voltage is high, and the output As technology scales down, static power becomes a
voltage is low. There is a transition region between these two more significant portion of the total power consumption.
states where the inverter is transitioning between the high and To minimize static power, designers often use techniques
low states. such as power gating or other low-leakage transistor
technologies.
B. Delay of inverter:
2) Dynamic Power (Pdynamic ):
The delay of an inverter is a crucial parameter that char- Dynamic power consumption occurs during the
acterizes how quickly the inverter responds to changes in its transition of the inverter output from one logic state
input signal. It is the time taken for the output voltage of the to another. It is proportional to the capacitance being
inverter to change from one logic state to another in response switched and the square of the voltage swing.
to a change in the input voltage.
The delay of an inverter is typically divided into three 1 2
components: Pdynamic = CL VDD f
2
 II. S IMULATION
A. Graphs: 1.0

Y
0.5

0.0

Vdc
0.0 20.0n 40.0n 60.0n 80.0n
+
− Output Time

1.0

Vdc

A
0.5

+
−
0.0

0.0 20.0n 40.0n 60.0n 80.0n

Time

Fig. 1. Circuit diagram of Inverter Fig. 4. V BIT input on Inverter

1.00

0.75
1.0
Vout (V)

0.50
Y

0.5

0.25

0.0

0.00

22.50f
Energy (J)

0.00 0.25 0.50 0.75 1.00

Vin (V) 15.00f

7.50f

Fig. 2. VTC curve of Inverter 0.00

1.0
A

0.5

Vdc 0.0

+
11.40µ
− Output
Power (W)

7.60µ

Vbit 3.80µ

+
− 0.00

0.0 20.0n 40.0n 60.0n 80.0n

Time (sec)

Fig. 3. Circuit diagram of Inverter for V BIT input Fig. 5. Energy and Power Curve
B. Calculations:
Various parameters values of Inverter upon calculation and
simulation are stated as follows:

Parameter Value
Wp(at VM = V DD/2) 143.2 nm
Delay 6p sec
VIL 401.84 mV
VIL 618.01 mV
N MH 381.99 mV
N ML 401.83 mV
Average Power 2.8 * 10−7 uW.
Energy 1.1 *10−7 uJ

C. Result and Discussion:

We have studied Inverter and its various characteristics with
different aspects which affect its nature and have successfully
understood them all.

III. CONCLUSION
In this experiment we successfully done analysis of CMOS
inverter using cadence virtuoso. We used TSMC-28 nm model
library provided by the institute. All the stated points have
been studied and all parameters have been succesfully calcu-
lated.
IV. REFERENCES
[1] Weste, Neil HE, and David Harris. CMOS VLSI design:
a circuits and systems perspective. Pearson Education India,
2015.
[2] Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje
Nikoli´ c. Digital integrated circuits: a design perspective. Vol.
7. Upper Saddle River, NJ: Pearson education, 2003.
 Delay Optimization using Chain of Inverters
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

Abstract—This report analyses the propagation delay of a

chain of inverters, to observe the strong relationship between
no. of stages of inverters and the delay of this chain tp . The
schematic and simulation were created using Cadence Virtuoso,
utilizing a library based on the 28nm technology process.

I. I NTRODUCTION

For a chain of inverters, sizing of the inverters in the chain

should be done in such a way that we obtain a minimum
propagation delay for the chain. The minimum delay for the
chain of inverter is given as:
Fig. 1
√
N
F For input bitstream A:
tp = N tpo (1 + ) (1)
γ

tpo is the intrinsic delay of an inverter.

F is the overall effective fanout.
√
f = N F , where f is the effective fanout, i.e the ratio
between its external load capacitance and input capacitance
f = CL /Cint .
Cint = γCg , where Cg is the gate capacitance and γ is the
proportionality factor.
N is the no. of stages in the chain of inverters. Fig. 2
It is observed that to get minimum delay optimum size for each
Output:
inverter is the geometric mean of the size of the neighbouring
inverters, this relation applies to gate capacitance of each
inverter and is given as:
p
Cg,j = Cg,j−1 Cg,j+1 (2)

II. S IMULATION R ESULTS

A. Transient Analysis

Delay optimization using 4 stages of inverter:

Effective fan-out = 2.83 Fig. 3
Overall effective fan-out = 64
The size of PMOS and NMOS of each inverter is taken 2.83 Power dissipation:
times the preceding inverter with the first inverter of reference
size.
 Fig. 7
Output:

Fig. 4
Energy:

Fig. 8
Power dissipation:

Fig. 5
Delay optimization using 6 stages of inverter:
Effective fan-out = 2
Overall effective fan-out = 64 Fig. 9
The size of PMOS and NMOS of each inverter is taken 2
times the preceding inverter with the first inverter of reference Energy:
size.

Fig. 10
III. C ONCLUSION
Fig. 6 The following observations were made for 4-stage and 6-
stage chain of inverters:
For input bitstream A:
TABLE I: Performance of Chain of Inverters
Number of Stages tplh (ps) tphl (ps) Average Power (µ W)
4 21.16 21.2 130.9
6 25.97 26.1 168.4

[1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital

Integrated Circuits - A Design Perspective, 2nd Edition,
Indian Edition. Prentice Hall, © 2016.
 Design and Analysis of CMOS NAND & AND
Gates In Cadence Virtuoso
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

Abstract—This report explores the utilization of Cadence III. S IMULATION

Virtuoso for the design, simulation, and analysis of CMOS NAND
and AND gates. The investigation involves pre-layout simulations
for delay and power determination, layout design creation, A. Prelayout Simulations
post-layout simulations, and a comprehensive examination of
outcomes. The delay and power characteristics of the designed gates
are analyzed through prelayout simulations. Cadence Virtuoso
I. I NTRODUCTION is employed to define the necessary parameters, including
Modern electronics heavily relies on CMOS technology, transistor sizes and supply voltage.
foundational to integrated circuits. This experiment focuses on
analyzing and designing NAND and AND gates, fundamental
to digital circuitry. B. Layout Design
A. Background Layout design involves physically placing and connecting
The utilization of CMOS technology is extensive due to its transistors on the chip, following various design rules. In this
ability to consume low power, possess high noise margins, experiment, the layout design adheres to the TSMC 28nm
and be compatible with various fabrication processes. Gaining technology.
a grasp on the construction and effectiveness of fundamental
CMOS gates is crucial for the development of intricate digital
circuitry. C. Postlayout Simulations
B. Objectives Postlayout simulations are crucial for validating the ac-
The experiment’s main goals involve the creation of CMOS tual performance of the designed gates. The layout files are
NAND and AND gates, the analysis of their behavior through extracted and simulated to observe any deviations from the
pre-layout simulations, the development of layouts, and the prelayout expectations. This phase also involves a detailed
validation of the design through post-layout simulations. analysis of power consumption and signal delay.
II. W ORKING P RINCIPLE
A. CMOS NAND Gate IV. R ESULTS AND D ISCUSSION
The CMOS NAND gate is designed with NMOS transistors
in series at the pull-up network and PMOS transistors in A. Prelayout Results
parallel at the pull-down network. When any of the inputs is
at a low state, the corresponding NMOS transistor conducts, The prelayout simulations provide insights into the expected
allowing the output to rise to a high logic level. Only when all behavior of the CMOS NAND and AND gates. The delay and
inputs are high, the NMOS transistors are off, and the PMOS power characteristics are critical parameters that influence the
transistors conduct, resulting in a low output. overall performance of digital circuits. The results from these
simulations serve as a benchmark for the postlayout analysis.
B. CMOS AND Gate
The CMOS AND gate utilizes NMOS transistors in parallel
for the pull-up network and PMOS transistors in series for B. Layout Analysis
the pull-down network. It generates a high output only when
both inputs are high, effectively performing the logical AND The postlayout simulations reveal the true performance of
operation. When any input is low, the corresponding NMOS the designed gates. Potential variations due to layout parasitics
transistor conducts, pulling the output down. Only when both and manufacturing processes are considered. Power consump-
inputs are high, the NMOS transistors are off, and the PMOS tion, signal delay, and other relevant metrics are analyzed to
transistors conduct, resulting in a high output. ensure that the gates meet the desired specifications.
 V. S CHEMATIC AND L AYOUT D IAGRAMS B. CMOS AND Gate
A. CMOS NAND Gate

Fig. 3. Schematic diagram for CMOS AND gate.

Fig. 1. Schematic diagram for CMOS NAND gate.

Fig. 4. Layout diagram for CMOS AND gate.

VI. C OMPARISON B ETWEEN P OST- LAYOUT AND

S CHEMATIC S IMULATIONS

A. Delay Comparison

1) NAND Gate Delay Comparison: The delay comparison

graph for the NAND gate is shown in Figure

Fig. 2. Layout diagram for CMOS NAND gate. Fig. 5. Prelayout delay of NAND.
 fundamental digital circuit components. The successful
achievement of proper functionality and alignment with
design specifications underscores the effectiveness of the
undertaken tasks.
A. Key Findings
The pre-layout simulations, layout design, and post-layout
simulations were instrumental in characterizing the CMOS
Fig. 6. Post-layout delay Of Nand. NAND and AND gates. The study focused on critical
parameters such as delay, power consumption, and overall
2) AND Gate Delay Comparison: The delay comparison circuit performance. The results offered a detailed
graph for the AND gate is shown in Figure beginfigure understanding of the gates’ responses under various
conditions, forming a foundation for further developments.
B. Significance of Results
The inclusion of schematic and layout diagrams, coupled
with the comparison between pre-layout and post-layout
simulations, highlights the reliability and accuracy of the
design. The significance of this experiment extends to the
core principles of digital circuitry, where NAND and AND
Prelayout delay of AND. gates serve as building blocks for complex logical operations
and digital systems.
C. Future Considerations
While the experiment successfully met its objectives, there
are avenues for future exploration. Subsequent studies could
focus on optimizing specific aspects, such as minimizing
power consumption while maintaining performance or
exploring different technology nodes for enhanced efficiency.

Fig. 7. Post-layout delay OF AND. IX. REFERENCES

[1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
VII. R ESULTS AND C ALCULATION Integrated circuits- A Design Perspective, 2nd Edition,
A. NAND Gate Indian Edition. Prentice Hall, © 2016

TABLE I
R ESULTS AND C ALCULATION FOR CMOS NAND G ATE

Parameter Prelayout Post-layout

Area 2.821 µm2 2.821µm2
tplh 2.489 ps 5.687 ps
tphl 3.311 ps 6.468 ps
Power 1.698 uW 3.564 uW

B. AND Gate

TABLE II
R ESULTS AND C ALCULATION FOR CMOS AND G ATE

Parameter Prelayout Post-layout

Area 4.2315 µm2 4.2315 µm2
tplh 6.766 ps 16.11 ps
tphl 6.364 ps 15.99 ps
Power 2.693 uW 6.422 uW

VIII. C ONCLUSION
The comprehensive exploration of CMOS NAND and AND
gates through design, layout, and analysis has provided
valuable insights into the behavior and performance of these
 Design and Analysis of CMOS NOR & OR Gates
In Cadence Virtuoso
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: To design and analyze the characteristics of the NOR When any input is high, the corresponding NMOS transistor
and OR gates using CMOS style with Cadence Virtuoso using conducts, allowing the output to rise to a high logic level. Only
TSMC 28nm technology. when all inputs are low, the NMOS transistors are off, and the
Abstract—This report explores the utilization of Cadence PMOS transistors conduct, resulting in a low output.
Virtuoso for the design, simulation, and analysis of CMOS NOR
and OR gates. The investigation involves pre-layout simulations III. S IMULATION
for delay and power determination, layout design creation,
A. Prelayout Simulations
post-layout simulations, and a comprehensive examination of
outcomes. The delay and power characteristics of the designed gates
are analyzed through prelayout simulations. Cadence Virtuoso
I. I NTRODUCTION is employed to define the necessary parameters, including
Modern electronics heavily relies on CMOS technology, transistor sizes and supply voltage.
foundational to integrated circuits. This experiment focuses
B. Layout Design
on analyzing and designing NOR and OR gates, fundamental
to digital circuitry. Layout design involves physically placing and connecting
transistors on the chip, following various design rules. In this
A. Background experiment, the layout design adheres to the TSMC 28nm
The utilization of CMOS technology is extensive due to its technology.
ability to consume low power, possess high noise margins, C. Postlayout Simulations
and be compatible with various fabrication processes. Gaining
Postlayout simulations are crucial for validating the ac-
a grasp on the construction and effectiveness of fundamental
tual performance of the designed gates. The layout files are
CMOS gates is crucial for the development of intricate digital
extracted and simulated to observe any deviations from the
circuitry.
prelayout expectations. This phase also involves a detailed
B. Objectives analysis of power consumption and signal delay.
The experiment’s main goals involve the creation of CMOS IV. S CHEMATIC AND L AYOUT D IAGRAMS
NOR and OR gates, the analysis of their behavior through A. CMOS NOR Gate
pre-layout simulations, the development of layouts, and the
validation of the design through post-layout simulations.
II. W ORKING P RINCIPLE
A. CMOS NOR Gate
The CMOS NOR gate is constructed with NMOS transistors
in parallel at the pull-up network and PMOS transistors in
series at the pull-down network. When any of the inputs is
at a high state, the corresponding NMOS transistor conducts,
pulling the output down to a low logic level. Only when all
inputs are low, the NMOS transistors are off, and the PMOS
transistors conduct, resulting in a high output.
B. CMOS OR Gate
The CMOS OR gate utilizes NMOS transistors in series
for the pull-up network and PMOS transistors in parallel for
the pull-down network. It generates a high output when any
input is high, effectively performing the logical OR operation. Fig. 1. Schematic diagram for CMOS NOR gate.
 Fig. 4. Layout diagram for CMOS OR gate.

V. C OMPARISON B ETWEEN P OST- LAYOUT AND

S CHEMATIC S IMULATIONS
A. Delay Comparison
1) NOR Gate Delay Comparison: The delay comparison
graph for the NOR gate is shown in Figure

Fig. 2. Layout diagram for CMOS NOR gate.

B. CMOS OR Gate Fig. 5. Prelayout delay of NOR.

Fig. 6. Post-layout delay Of NOR.

2) OR Gate Delay Comparison: The delay comparison

graph for the OR gate is shown in Figure beginfigure

Fig. 3. Schematic diagram for CMOS OR gate. Prelayout delay of OR.

 analysis of CMOS NOR and OR gates. The gates exhibit
Fig. 7. Post-layout delay OF 0R. proper functionality and adhere to the designated design
specifications. The knowledge acquired from this experiment
VI. R ESULTS AND C ALCULATION forms a robust foundation for understanding and applying
A. NOR Gate CMOS technology in the realm of digital integrated circuits.
VIII. REFERENCES
TABLE I
R ESULTS AND C ALCULATION FOR CMOS NOR G ATE [1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated circuits- A Design Perspective, 2nd Edition,
Parameter Prelayout Post-layout
Area 2.821 µm2 2.821µm2
Indian Edition. Prentice Hall, © 2016
tplh 4.982 ps 4.982 ps
tphl 8.508 ps 8.508 ps
Power 4.085 uW 4.085 uW

B. OR Gate

TABLE II
R ESULTS AND C ALCULATION FOR CMOS OR G ATE

Parameter Prelayout Post-layout

Area 4.2315 µm2 4.2315µm2
tplh 5.804 ps 14.52 ps
tphl 8.072 ps 18.9 ps
Power 3.735 uW 8.938 uW

VII. C ONCLUSION
The thorough exploration of CMOS NOR and OR gates,
encompassing design, layout, and analysis, has proven to be
a successful endeavor. This comprehensive study resulted in
achieving proper functionality and ensuring alignment with
the specified design criteria.
A. Key Outcomes
The combination of pre-layout simulations, layout design,
and post-layout simulations played a crucial role in
characterizing the behavior of CMOS NOR and OR gates.
Essential parameters like delay, power consumption, and
overall circuit performance were meticulously examined,
providing detailed insights into the gates’ responses across
various scenarios.
B. Implications of Results
The inclusion of schematic and layout diagrams, along with
a comparative analysis between pre-layout and post-layout
simulations, underscores the reliability and precision of the
design. The significance of this experiment extends to the
core principles of digital circuitry, where NOR and OR gates
contribute to the foundation of logical operations and the
construction of digital systems.
C. Future Prospects
While the experiment successfully accomplished its
objectives, potential future endeavors could focus on
optimizing specific aspects, such as further minimizing power
consumption without compromising performance. Exploring
alternative technology nodes may also be considered for
potential efficiency enhancements. In summary, the
experiment has effectively showcased the design, layout, and
 Design and Analysis of CMOS XOR & XNOR
Gates In Cadence Virtuoso
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: To design and analyze the characteristics of the XOR B. CMOS XNOR Gate
and XNOR gates using CMOS style with Cadence Virtuoso
using TSMC 28nm technology. The CMOS XNOR gate, or the exclusive NOR gate, gen-
Abstract—This report explores the utilization of Cadence Vir-
tuoso for the design, simulation, and analysis of CMOS XOR and
erates a high output when the number of high inputs is
XNOR gates. The investigation involves pre-layout simulations even. It utilizes a similar configuration of NMOS and PMOS
for delay and power determination, layout design creation, transistors to achieve its logic function. When one input is
post-layout simulations, and a comprehensive examination of high, the corresponding NMOS transistor conducts, pulling
outcomes. the output down. At the same time, the high input activates
the PMOS transistor in the series path, pulling the output up.
I. I NTRODUCTION This combined action results in a low output for odd numbers
Modern electronics heavily relies on CMOS technology, of high inputs and a high output for even numbers.
foundational to integrated circuits. This experiment focuses on
analyzing and designing XOR and XNOR gates, fundamental
to digital circuitry.
III. S IMULATION
A. Background
The utilization of CMOS technology is extensive due to its A. Prelayout Simulations
ability to consume low power, possess high noise margins,
and be compatible with various fabrication processes. Gaining
a grasp on the construction and effectiveness of fundamental The delay and power characteristics of the designed gates
CMOS gates is crucial for the development of intricate digital are analyzed through prelayout simulations. Cadence Virtuoso
circuitry. is employed to define the necessary parameters, including
transistor sizes and supply voltage.
B. Objectives
The experiment’s main goals involve the creation of CMOS
XOR and XNOR gates, the analysis of their behavior through B. Layout Design
pre-layout simulations, the development of layouts, and the
validation of the design through post-layout simulations.
Layout design involves physically placing and connecting
transistors on the chip, following various design rules. In this
II. W ORKING P RINCIPLE
experiment, the layout design adheres to the TSMC 28nm
A. CMOS XOR Gate technology.
The CMOS XOR gate, also known as the exclusive OR
gate, produces a high output only when the number of high
inputs is odd. It employs a combination of NMOS and PMOS
transistors arranged in a specific configuration to achieve C. Postlayout Simulations
this functionality. When one input is high, the corresponding
NMOS transistor conducts, pulling the output down. Simulta- Postlayout simulations are crucial for validating the ac-
neously, the high input activates the PMOS transistor in the tual performance of the designed gates. The layout files are
parallel path, pulling the output up. This dual action results extracted and simulated to observe any deviations from the
in a high output for odd numbers of high inputs and a low prelayout expectations. This phase also involves a detailed
output for even numbers. analysis of power consumption and signal delay.
 IV. S CHEMATIC AND L AYOUT D IAGRAMS

A. CMOS XOR Gate

Fig. 4. Layout diagram for CMOS XNOR gate.

V. C OMPARISON B ETWEEN P OST- LAYOUT AND

S CHEMATIC S IMULATIONS

A. Delay Comparison

1) XOR Gate Delay Comparison: The delay comparison

graph for the XOR gate is shown in Figure

Fig. 1. Schematic diagram for CMOS XOR gate.

Fig. 5. Prelayout delay of XOR.

Fig. 2. Layout diagram for CMOS XOR gate.

B. CMOS XNOR Gate

Fig. 6. Post-layout delay.

2) XNOR Gate Delay Comparison: The delay comparison

graph for the XNOR gate is shown in Figure beginfigure

Fig. 3. Schematic diagram for CMOS XNOR gate. Prelayout delay of XNOR.
 C. Future Considerations
While the experiment has achieved its objectives, there are
potential areas for further exploration. Future studies could
delve into optimizing specific parameters, such as reducing
delay or minimizing power consumption. Exploring the
impact of different technology nodes or fabrication processes
could also contribute to the advancement of CMOS gate
design.
Fig. 7. Post-layout delay OF XNOR.
VIII. REFERENCES
VI. R ESULTS AND C ALCULATION [1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
A. XOR Gate Integrated circuits- A Design Perspective, 2nd Edition,
Indian Edition. Prentice Hall, © 2016
TABLE I
R ESULTS AND C ALCULATION FOR CMOS XOR G ATE

Parameter Prelayout Post-layout

Area 11.284 µm2 11.284µm2
tplh 9.616 ps 19.47 ps
tphl 15.25 ps 38.39 ps
Power 9.526 uW 22.52 uW

B. XNOR Gate

TABLE II
R ESULTS AND C ALCULATION FOR CMOS XNOR G ATE

Parameter Prelayout Post-layout

Area 11.284 µm2 11.284µm2
tplh 7.113 ps 18.63 ps
tphl 10.58 ps 20.11 ps
Power 7.454 uW 16.37 uW

VII. C ONCLUSION
The comprehensive exploration of CMOS XOR and XNOR
gates through design, layout, and analysis has yielded
valuable insights into the behavior and performance of these
fundamental digital circuit components. The successful
achievement of proper functionality and alignment with
design specifications underscores the effectiveness of the
undertaken tasks.
A. Key Findings
The Voltage Transfer Characteristics (VTC), delay analysis,
noise margins, and power consumption were thoroughly
investigated through simulations and post-layout validations.
The results provided a detailed understanding of how the
XOR and XNOR gates respond to different input conditions
and their overall efficiency in terms of speed and power
utilization.
B. Significance of Results
The accurate representation of schematic and layout
diagrams, coupled with the comparison between post-layout
and schematic simulations, showcases the reliability and
robustness of the design. The significance of this experiment
extends to the broader context of digital circuitry, where
XOR and XNOR gates play pivotal roles in numerous
applications, including arithmetic and logical operations.
 AIM: This experiment aims to design and analyze the technology. In Pseudo NMOS logic, both n-type and p-type
characteristics of various gates using Pseudo NMOS logic style transistors are used to implement a logic gate.
with Cadence Virtuoso using TSMC 28nm technology. The advantages of Pseudo NMOS logic, including Pseudo
NAND gates, include simplicity of design and potentially
Abstract—This research conducts a comprehensive compar- faster operation in certain conditions. However, it is associated
ative analysis between Pseudo NMOS (Negative Metal-Oxide-
Semiconductor) and CMOS (Complementary Metal-Oxide- with higher static power consumption due to the use of
Semiconductor) implementations, exploring their respective per- resistive pull-up networks.
formances, energy efficiencies, and design considerations.
Design considerations, challenges, and trade-offs associated with
integrating Pseudo NMOS and CMOS into digital circuits are +
discussed. The study provides insights into the factors that de- −
signers must consider when selecting between these technologies
based on application requirements, performance goals, and power Output
constraints.

I. INTRODUCTION A
+ Vbit
−
A. VTC of PSEUDO NMOS :
The Voltage-Transfer Characteristic (VTC) of a Pseudo B V
NMOS (Negative Metal-Oxide-Semiconductor) inverter refers + bit
−
to the graphical representation of its input and output voltage
relationship.
When analyzing the VTC of a Pseudo NMOS inverter with
changing transistor size, several key observations can be made: Fig. 2. Circuit of Pseudo NAND
1) Threshold Voltage Shift: Altering the size of the tran-
sistors in the Pseudo NMOS configuration affects the
threshold voltage of the inverter. C. Pseudo NOR
2) Transition Region Slope: The slope of the transition
”Pseudo NOR” typically refers to a logic gate constructed
region in the VTC is influenced by the size of the transis-
using Pseudo NMOS (Negative Metal-Oxide-Semiconductor)
tors. Larger transistors generally lead to steeper slopes,
technology. Similar to the concept of Pseudo NAND, Pseudo
resulting in faster transitions between logic states.
NOR gates are implemented using a combination of n-type and
3) Input Voltage Range: The range of input voltages over
p-type transistors in a configuration that deviates from stan-
which the Pseudo NMOS inverter operates effectively is
dard CMOS (Complementary Metal-Oxide-Semiconductor)
influenced by the transistor size.
designs.
4) Signal Swing and Noise Margins: Changing the tran-
It produces a low output only when both of its inputs are
sistor size affects the output voltage swing and, conse-
high. In Pseudo NOR gates, this logic is realized using a
quently, the noise margins.
combination of n-type and p-type transistors.

Vdc
+
Vdc −
+ A Vbit Output
+
− Output −

Vbit B
+ + Vbit
− −

Fig. 3. Circuit of Pseudo NOR

Fig. 1. Circuit of Pseudo Inverter

D. Pseudo XOR
an XOR gate (exclusive OR gate) produces a high output
B. Pseudo NAND (1) when the number of high inputs is odd.
”Pseudo NAND” typically refers to a logic gate constructed 1) XOR Operation: Utilize a combination of n-type tran-
using Pseudo NMOS (Negative Metal-Oxide-Semiconductor) sistors to create a parallel path that produces a low
 output (0) when the number of high inputs is even. This II. S IMULATION
configuration emulates the XOR operation.
2) Pseudo Inverter Operation: Introduce a p-type transistor
(l=3.3e-07)
in series with the XOR operation. This p-type transistor 1.1 (l=2.7e-07)

functions as a pseudo inverter, inverting the output of 1.0

(l=2.1e-07)

(l=1.5e-07)

the XOR stage. The inversion ensures that the output is 0.9
(l=9e-08)

(l=3e-08)
high (1) when the number of high inputs is odd. 0.8

0.7

Vout(V)
0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

Vin(V)

Fig. 6. VTC characteristics on varying size

Fig. 4. Circuit of Pseudo XOR

E. Pseudo XNOR

A Pseudo XNOR gate, or an XOR followed by an inverter,

is a logical circuit constructed using Pseudo NMOS (Negative Fig. 7. Output curve of Pseudo NAND
Metal-Oxide-Semiconductor) technology
1) XOR Operation: Use a combination of n-type transistors
to create a parallel path that produces a low output (0)
when an odd number of high inputs is present. This
emulates the XOR (exclusive OR) operation.
2) Pseudo Inverter Operation: Introduce a p-type transistor
in series with the XOR operation. This p-type transistor
functions as a pseudo inverter, inverting the output of
the XOR stage.

Fig. 8. Output curve of Pseudo NOR

Vdc
+
−

A Output
+ Vbit
−

B
+ Vbit
−

Fig. 5. Circuit of Pseudo XNOR Fig. 9. Output curve of Pseudo XNOR

 Fig. 10. Output curve of Pseudo XOR

A. Result and Discussion:

We have implemented NAND, NOR, XOR, XNOR using
Pseudo logic and studied the effect on inverter characteristics
on varying size.

III. CONCLUSION
In this experiment we successfully implemented all the
single stage MOS amplifier using Cadence Virtuoso. We used
TSMC-28 nm model library provided by the institute. All the
stated points have been studied and all parameters have been
successfully calculated.
R EFERENCES
[1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated circuits- A Design Perspective, 2nd Edition, Indian
Edition. Prentice Hall, © 2016
 Design of Logic Gates using DCVSL
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

Aim: The aim of this experiment is to design and compare devices and are mutually exclusive (this is, when PDN1 con-
DCVSL logic gates (NAND, NOR, XOR, XNOR) with CMOS ducts, PDN2 is off, and when PDN1 is off, PDN2 conducts),
implementation, taking into consideration their performance such that the required logic function and its inverse are simul-
and drawbacks. taneously implemented.The resulting circuit exhibits a rail-to-
Abstract—This project explores the functionality and analysis rail swing, and the static power dissipation is eliminated.
of DCVSL logic gates and compares them to CMOS implementa-
tion for logic gates such as NAND, NOR, OR, XNOR. It discusses
the characteristics of DCVSL gates, including their advantages,
drawbacks, and trade-offs when compared to CMOS logic.

I. I NTRODUCTION
In order to eliminate static power dissipation and achieve
rail-to-rail swing, DCVSL is utilized. This circuit provides the
output and its complementary format when given an input. It
III. S IMULATION
incorporates positive feedback to switch off the unconditional
load and eliminate static power consumption. DCVSL offers
high-speed operation due to its differential structure, and its
performance is further enhanced by the cascode configuration.
A. Objectives
The primary objectives of this project include designing A. DCVSL Simulation
DCVSL NAND, NOR, XOR, and XNOR gates, conducting
simulations to analyze their performance, and comparing the
results with CMOS implementations.
Simulations for DCVSL gates involve analyzing their delay,
II. W ORKING P RINCIPLE power consumption, and other performance metrics. Differen-
DCVSL circuits typically consist of a pair of differential tial operation and ratioless design contribute to these charac-
pairs in a cascode configuration. The differential structure teristics.
of DCVSL enables high-speed operation, and the cascode
configuration further improves its performance.
• NAND Gate using DCVSL and its output waveform.

Vdc
+
−

Vdd

Vbit A INVERTER Y NAND AND

GND

Vbit
Vdd

B INVERTER Y

GND

Figure : Basic structure Circuit

Above Figure consists of the basic DCVSL structure, which
contains pull-down networks PDN1 and PDN2 use NMOS Figure 1 : NAND Gate using DCVSL
 0.99
0.99

0.66

0.66
A

NOR
0.33

0.33

0.00

0.00
0.99

0.99
0.66
B

0.66
0.33

A
0.00 0.33

0.99
0.00
NAND

0.66
0.99

0.33

0.66

B
0.00

0.33
0 20n 40n 60n 80n 100n

NAND using DCVSL

0.00

0 20n 40n 60n 80n 100n

NOR using DCVSL

Figure 2 : Waveform of NAND Gate using PTL

Figure 4 : Waveform of NOR Gate using PTL
• NOR Gate using DCVSL and its output waveform.
• XOR-XNOR Gate using DCVSL and its output wave-
form.

Vdc
Vdc +
+ −
−

Vdd
Vdd
Vbit A INVERTER Y
Vbit A INVERTER Y NAND AND
GND
GND

Vbit
Vdd
Vbit
Vdd
B INVERTER Y

B INVERTER Y GND

GND

Figure 5 : XOR-XNOR Gate using DCVSL

Figure 3 : NOR Gate using DCVSL

 V. C ONCLUSION
This experiment successfully demonstrates the design, sim-
ulation, and comparison of DCVSL logic gates.
0.99
In the realm of digital circuit design, it is essential to
acknowledge the disadvantages in order to make informed
0.66 choices. Designers must diligently assess compromises to
A

identify the logic style that best suits a specific application.

0.33

R EFERENCES
0.00
[1] Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2016). Digital Inte-
grated Circuits - A Design Perspective, 2nd Edition. Prentice Hall, Indian
0.99
Edition.

0.66
B

0.33

0.00

0.99
XOR

0.66

0.33

0.00

0.99
XNOR

0.66

0.33

0.00

0 20n 40n 60n 80n 100n

XOR-XNOR using DCVSL

Figure 6 : Waveform of XOR-XNOR Gate using PTL

IV. R ESULT AND D ISCUSSION

Logic tpH L tpLH Avgp ower Peakp owerEnergy
NAND 40ps 425.3ps 780nW 94.84uW 70.28fJ
NOR 286.2ps 291.6ps 723nW 62.5uW 67.9fJ
XOR 384ps 386.3ps 996nW 45.7uW 80.28fJ
XNOR 382ps 395.3ps 996nW 45.7uW 80.28fJJ

A. DCVSL Characteristics
The results from DCVSL simulations showcase its benefits,
including low power consumption, high speed, and improved
noise margins.

B. Comparison with CMOS

Comparing DCVSL with CMOS, it may require more
transistors, impacting area and complexity.
 Design of Logic Gates using PTL
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

Aim: To design and compare PTL logic gates (NAND,

NOR, XOR, XNOR) with CMOS implementation.
Abstract—This project presents an examination of PTL logic
gates and their comparison with CMOS implementation for
NAND, NOR, OR, and XNOR gates. It discusses the charac-
teristics of PTL gates, including their advantages, drawbacks,
and trade-offs when compared to CMOS logic.

I. I NTRODUCTION
Pass-transistor logic (PTL) is a popular alternative to com-
plementary CMOS. PTL utilizes transistors as switches to
either pass or block a signal. The output node is consistently
driven to logic low or logic high through a low-resistance path Figure 2 : Waveform of NAND Gate using PTL
provided by a PMOS or NMOS transistor.
• NOR Gate using PTL and and its output waveform.
A. Objectives
B
The primary objectives of this project include designing
B
PTL NAND, NOR, XOR, and XNOR gates, performing simu-
lations to analyze their performance, and comparing the results Y= A+B
B_bar
with CMOS implementations. A_bar
A
II. W ORKING P RINCIPLE
A. PTL Logic Gates Figure 3 : NOR Gate using PTL
PTL gates use pass transistors to transmit signals. NMOS
transistors pass a strong ’1’ and a weak ’0’, while PMOS
transistors pass a strong ’0’ and a weak ’1’. PTL aims to
reduce the number of transistors needed for logic implemen-
tation by allowing the primary inputs to drive gate terminals as
well as source/drain terminals. This leads to fewer transistors,
resulting in reduced area and load capacitances.

III. S IMULATION
A. PTL Simulation
Simulations for PTL NAND, NOR, XOR, and XNOR gates
involve analyzing their delay, power consumption, and other Figure 4 : Waveform of NOR Gate using PTL
performance metrics.
• XOR Gate using PTL and and its output waveform.
• NAND Gate using PTL and and its output waveform.
B_BAR
B_bar
B
A

B Y= AB

A A_bar B F = A xor B

A_BAR
Figure 1 : NAND Gate using PTL
 Figure 5 : XOR Gate using PTL 1) Advantages of PTL over CMOS:
• Reduced Transistor Count: When compared with CMOS
style,PTL uses less number of transistors which results
in lesser area and load capacitances.
• We can also obtain true and complementary outputs using
Differential PTL logic.

2) Drawbacks of PTL compared to CMOS:

• PTL circuits are susceptible to charge sharing between
nodes, especially when multiple transistors are connected
to the same node which may lead to incorrect logic gates.
• PTL circuits may consume more DC power compared to
static CMOS, particularly in scenarios with a high fan-
Figure 6 : Waveform of XOR Gate using PTL out.
• XNOR Gate using PTL and its output waveform. • Reduced Noise Margins: PTL gates often exhibit reduced
noise margins compared to CMOS, impacting their ro-
B bustness in noisy environments.
• Not Rail-to-Rail Switches: PTL gates may not achieve
rail-to-rail switching, limiting their output voltage range.
A
V. A PPLICATION
PTL is commonly used in situations where area efficiency
and speed are crucial, particularly in high-performance digital
circuits. However, it may not be the best choice for low-
B_bar power applications due to the potential for higher static power
consumption.
A_bar VI. C ONCLUSION
A. Achievements
Figure 7 : XNOR Gate using PTL The experiment successfully demonstrated the design, simu-
lation, and comparison of PTL logic gates. Understanding the
B advantages and disadvantages of PTL gates is essential for
making informed decisions in digital circuit design. Design-
A ers must carefully consider trade-offs to determine the most
appropriate logic style for a given application.
R EFERENCES
[1] Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2016). Digital Inte-
grated Circuits - A Design Perspective, 2nd Edition. Prentice Hall, Indian
B_bar Edition.

A_bar
Figure 8 : Waveform of XNOR Gate using PTL

IV. R ESULT AND D ISCUSSION

A. PTL Characteristics
The results from PTL simulations showcase potential ad-
vantages, including reduced transistor count and potentially
lower power consumption.

B. Comparison with CMOS

Comparing PTL with CMOS, the report discusses the the-
oretical advantages and drawbacks of PTL logic gates.
 DESIGN of Logic gates USING CPL
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM:Design NAND/AND,NOR/OR,XOR/XNOR GATE and drain terminals set to V DD. Let’s call the NMOS pass
USING PASS TRANSISTOR LOGIC in TSMC 28nm tech- transistor’s source x. Node x will charge V DD − V T n(V x)
nology with the help of Cadence Virtuoso tool and plot the
wave forms of given input output to both the gates and also
find power consumption .Also draw the schematic used in this q q
report Vx = Vdd − (Vtn0 + γ(( |2ϕf + Vx | − |2ϕf |))
Abstract—this report consists of working and analysis of
NAND,NOR,XOR,XNOR GATE using the PASS TRANSISTOR
LOGIC. CPL logic reduces the number of transistors required
to implement logic by allowing the primary inputs to drive the A. Circuit daigram of CPL logic gates
gate terminals as well as source drain terminal.Here we also have
calculated the power consumed. • CPL NAND AND GATE
I. I NTRODUCTION
Complementary Pass logic is a popular and commonly
used alternative to complementary CMOS logic that seeks B
to decrease the number of transistors necessary to implement
logic by enabling the major inputs to drive gate terminals as B_bar
B Y=(AB)_bar
well as source/drain terminals. This is in contrast to the logic vbit +
− B
families we’ve covered so far, which
Only enable main inputs to drive the gate terminals of MOS- A B_bar
FETS. Figure demonstrates an implementation of the AND + vbit
− B_bar Y_bar=AB
function built in this manner using only NMOS transistors.
If the B input is high, the top transistor in this gate turns
on and replicates the input A to the output F. When B is
low, the bottom pass transistor turns on and passes a 0. At
first inspection, the switch controlled by B appears to be Fig. 1. CPL NAND AND GATE
superfluous. Its existence is required to guarantee that the gate
is static, which means that a low-impedance path to the supply
rails exists under all conditions, or, in this example, when B • CPL NOR OR GATE
is low.
The promise of this method is that it requires fewer tran-
sistors to implement a given function. For example, the AND
gate requires four transistors (including the inverter needed B_bar

to invert B), but a corresponding CMOS counterpart would B

require six transistors. The reduced number of devices has the B
Y_bar=(A+B)_bar
vbit +
added benefit of lowering capacitance. −

II. W ORKING P RINCIPLE A

B_bar Y=(A+B)
+ vbit
−
Unfortunately, as previously stated, an NMOS device is
good at passing a 0 but not so good in pulling a node to
V DD. When a node is pulled high by the pass transistor, the fig:CPL NOR
output only charges up to V DD−V T n Actually, the dilemma
is exacerbated by the fact that the gadgets Fig. 2. CPL NOR OR GATE
When pulling high, there is a substantial source-to-body
voltage, which causes body effect. Consider the situation in
which a pass transistor is charging a node with the gate • CPL XNOR XOR GATE
 B_bar

B Y=exor
B
vbit +
−

A
+ Y_bar=exnor
−
vbit

fig:EXOR-EX-NOR Fig. 5. CPL NOR OR GATE

Fig. 3. CPL XNOR XOR GATE • CPL XNOR XOR GATE

B. Parameters to be analysed

In this report we have analyzed the following and plotted

following things:
1) input output waveforms for different gates
2) power consumed by each of them.

C. Use Cases for CPL Logic

Fig. 6. CPL XNOR XOR GATE
The decision to adopt CPL logic depends on specific re-
quirements and design goals. It can be particularly beneficial in B. Performance Analysis
scenarios where low power consumption and compact design
are crucial, and the sensitivity to process variations can be Through simulation, we gain insights into how CPL logic
managed effectively. addresses the challenges posed by CMOS, providing a practi-
cal assessment of its advantages and limitations.

III. S IMULATION 1) CPL NAND AND GATE Calculations::

• tpl h : 6.986 ps
A. Simulation Goals • tph l : 7.902 ps
−6
• Averge power: 21.92 ∗ 10 watt
The simulation aims to evaluate the performance of CPL −6
• Peak power: 251.6 ∗ 10 watt
logic gates under different conditions, emphasizing factors −15
• Energy: 17.75 ∗ 10 joule
such as power consumption, delay, and area utilization. Ca-
dence Virtuoso, utilizing TSMC 28nm node technology, is
2) CPL NOR OR GATE Calculations::
employed for accurate characterization.
• tpl h : 7.705 ps
• CPL NAND AND GATE • tph l : 7.052 ps
−6
• Averge power: 10.26 ∗ 10 watt
−6
• Peak power: 257.7 ∗ 10 watt
−15
• Energy: 8.307 ∗ 10 joule

3) CPL XNOR XOR GATE Calculations::

• tpl h : 6.793 ps
• tph l : 15.207 ps
−6
• Averge power: 9.393 ∗ 10 watt
−6
• Peak power: 233.8 ∗ 10 watt
−15
• Energy: 7.576 ∗ 10 joule
Fig. 4. CPL NAND AND GATE IV. C ONCLUSION
The main advantages of CPL logic are increase speed
• CPL NOR OR GATE and reduced implementation area.The fewer the devices to
implement a given logic function means that over all load
capacitance is much smaller,glitching does not occur in CPL
logic hence, over all We can say ,it is the best situated for the
high speed circuits.
V. R EFERENCES
[1] Weste, Neil HE, and David Harris. CMOS VLSI design:
a circuits and systems perspective. Pearson Education India,
2015.
[2] Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje
Nikoli´ c. Digital integrated circuits: a design perspective. Vol.
7. Upper Saddle River, NJ: Pearson education, 2003.
 Custom 4-Transistor XOR Gate Design and
Comparison
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: Explore the design and characteristics of a custom III. S IMULATION

4-transistor XOR gate and compare it with CMOS implemen-
tation. A. Simulation Setup
Abstract—This report presents the design, simulation, and
analysis of a customized 4-transistor XOR gate, highlighting In the simulation section, the setup is described in detail,
its unique design features and advantages. The performance is
specifying the tools and technology used. This includes the
compared to a CMOS implementation.
use of Cadence Virtuoso, TSMC28nm node technology, and
I. I NTRODUCTION other relevant information.

A. Custom 4-Transistor XOR Gate

A B
The goal of the custom XOR gate is to provide a more
efficient and high-performing alternative to traditional XOR B A
gate designs. The custom 4 XOR gate incorporates specific
design features that aim to improve power efficiency and +
Vdd − Y
overall performance. These features may include transistor
arrangement, logic configuration, and unique circuitry.
A A
B. Design Features +
− Vbit
The custom XOR gate introduces a novel design with
specific features aimed at improving power efficiency and
overall performance. These features may include transistor B
arrangement, logic configuration, and unique circuitry. +
− Vbit
C. Motivation for Custom Design
The development of the custom XOR gate is motivated
by the need to address challenges or limitations observed in Fig. 1. 4 Transistor XOR gate using PTL logic
existing XOR gate designs, such as power consumption, area
utilization, or speed.

II. W ORKING P RINCIPLE

A. Custom XOR Logic B. Analysis of Simulation Results

The custom 4-transistor XOR gate operates using a unique The simulation results are then presented and analyzed
logic configuration, where each transistor has a specific role extensively. The performance of the custom XOR gate is
in achieving XOR functionality. The report provides a detailed compared to the CMOS implementation under different
explanation of the logic operations and highlights the distinc- conditions, providing valuable insights into its advantages.
tive aspects of the custom design. The output results of the XOR gates are shown in Figure
2.Simulation results are presented and analyzed in detail.The
B. Comparison with CMOS XOR performance of the custom XOR gate is compared with
The paper presents an analysis that highlights the differ- CMOS implementation under various conditions, providing
ences in working principles between a custom XOR gate and insights into its advantages.
traditional CMOS XOR gates. Special attention is given to the
advantages offered by the custom design. 1) Output results of XOR gates:
 Fig. 2. Output Custom XOR gate

2) Calculations:
• tpl h : 2.8669 ps

• tph l : 1.775 ps

• Averge power: 911.9 nW

• Peak power: 82.1867 ∗ 10−6 watt

• Energy: 738.6 ∗ 10−18 joule

IV. C ONCLUSION
A. Advantages of Custom XOR Gate
the advantages demonstrated by the custom 4-transistor
XOR gate are summarized. This includes improvements in
power efficiency, performance, and other key metrics.
V. REFERENCES
Digital integrated circuits: Rabaey, Jan M., Anantha and
Borivoje Nikolic Pearson education, 2006.
 Transmission Gate Logic Design
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: Explore the design and characteristics of Transmis- A. TGL Nand Gate
sion Gate (TG) logic gates (2:1 Mux, NAND, AND, NOR,
XOR) and compare them with other logic implementations.
Abstract—This report presents the design, simulation, and
characteristics analysis of Transmission Gate (TG) logic gates
using TSMC 28nm node technology in Cadence Virtuoso. Special A
emphasis is placed on the unique advantages of TG logic,
including rail-to-rail switching and fast transitions. Simulation Bbar
results are examined to verify these characteristics and compare
TG logic gates with other logic families.
Abar OUT
I. I NTRODUCTION
A. Why Transmission Gate Logic?
Transmission Gate (TG) logic presents a compelling alter-
native to traditional logic families, offering unique advantages
that address specific challenges. One notable feature is the A
ability to achieve rail-to-rail switching, ensuring that the output
voltage can reach both power supply rails (VDD and VSS ). Fig. 1. TGL Nand circuit
This characteristic is particularly advantageous in scenarios
where the full swing of logic levels is crucial for reliable
circuit operation.
B. Rail-to-Rail Switching advantage:
In TG logic, the concurrent operation of both PMOS and
NMOS transistors during the charging or discharging process
enables rail-to-rail switching. Unlike some other logic families,
TG logic ensures that the output voltage can reach the power
0.72
supply rails (VDD and VSS ), providing a full and reliable logic
NAND Y

swing. 0.54

0.36
C. Application in 2:1 Mux and Logic Gates:
0.18
These advantages make TG logic well-suited for various
0.99
digital circuit applications. In the design of a 2:1 Mux and
logic gates (NAND, AND, NOR, XOR), the rail-to-rail switch- 0.66
B

ing and fast transition features play a key role in achieving 0.33

efficient and high-performance circuitry.

0.00

D. Simulation Verification: 0.99

To practically verify these characteristics, Cadence Virtuoso 0.66

simulation with TSMC 28nm node technology is employed.

A

0.33
By analyzing the simulation results, which include power
consumption, delay, and area utilization, we can gain valuable 0.00

insights into the superior performance of TG logic in achieving 0.0 200.0p 400.0p 600.0p 800.0p

Time(sec)
rail-to-rail switching and rapid transitions.
II. S IMULATION
Fig. 2. TGL NAND Simulation
The simulation of the designed gates with their circuits are
shown below:
B. TGL AND Gate C. Nor Gate

A
0

A Abar
B

Abar OUT
Bbar
A
Fig. 5. TGL Nor circuit

Fig. 3. TGL And circuit

0.8

0.6
NOR Y

0.4

0.2

0.99

0.66

A
B

B 0.33

0.00

0.99

Abar OUT
0.66
A

0.33

0.00

0.0 200.0p 400.0p 600.0p 800.0p

A Time (sec)

Fig. 4. TGL NAND Simulation Fig. 6. TGL NOR Simulation

D. Xor Gate E. 2:1 Mux using TG

A
Bbar

Abar OUT

Fig. 7. TGL Xor circuit

Fig. 9. TG Multiplexer

0.76
0.76

0.57
Y

0.57
XOR Y

0.38

0.38
0.19

0.19 0.99

0.66
S0

0.99

0.33

0.66
0.00
B

0.99
0.33

0.66
B

0.00
0.33

0.99
0.00

0.99
0.66
A

0.66
A

0.33
0.33

0.00
0.00

0.0 200.0p 400.0p 600.0p 800.0p 0.0 200.0p 400.0p 600.0p 800.0p

Time (Sec) TIme(sec)

Fig. 8. TGL XOR Simulation Fig. 10. TGL MUX Simulation

 III. R ESULTS AND C ONCLUSION IV. R EFERENCES
[1] Weste, Neil HE, and David Harris. CMOS VLSI design:
A. Results
a circuits and systems perspective. Pearson Education India,
The key parameters for TGL-nand gate are as follows: 2015.
[2] Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje
Nikoli´ c. Digital integrated circuits: a design perspective. Vol.
Results Schematic Value
7. Upper Saddle River, NJ: Pearson education, 2003.
TPHL 1.51p s
TPLH 1.92p s
Avg. Power 2.98mW
The key parameters for TGL-and gate are as follows:

Results Schematic Value

TPHL 5.509p s
TPLH 1.78p s
Avg. Power 2.09mW
The key parameters for TGL-nor gate are as follows:

Results Schematic Value

TPHL 1.49p s
TPLH 1.88p s
Avg. Power 2.99mW
The key parameters for TGL-Xor gate are as follows:

Results Schematic Value

TPHL 4.73p s
TPLH 1.88p s
Avg. Power 2.47mW

B. Key Findings
The simulation results confirm the unique advantages of
Transmission Gate (TG) logic, showcasing its ability to
achieve rail-to-rail switching and fast transitions. These fea-
tures position TG logic as a promising choice in applications
where full swing and high-speed operation are crucial.

C. Comparison with Other Logics

In comparison to other logic families, TG logic stands out
in terms of its rail-to-rail capabilities. The reduced propagation
delay contributes to its suitability for high-speed applications,
making it a compelling alternative to traditional logic imple-
mentations.

D. Considerations for Adoption

While TG logic presents clear advantages, designers should
carefully assess its suitability based on specific application
requirements. Factors such as power consumption, area utiliza-
tion, and sensitivity to process variations should be considered
for optimal circuit performance.
 Design of Static D Latch and Master-Slave Flip
Flop
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: To design and analyze the characteristics of a Static B. Master-Slave Flip-Flop

D-Latch using Transmission Gate and Inverter, and a Master- The Master-Slave Flip-Flop consists of two latches (master
Slave Flip-Flop in a positive or negative edge-triggered and slave) connected in series. The master latch captures
configuration. Simulations will be performed in Cadence the data during the positive or negative edge of the clock
Virtuoso using TSMC 28nm node technology. signal, and the slave latch stores the data until the next clock
transition.
Abstract—This experiment aims to explore the characteristics
and design of a Static D-Latch and a Master-Slave Flip-Flop using
Cadence Virtuoso simulation software and TSMC 28nm node III. S IMULATION
technology. The Static D-Latch is constructed using Transmission A. Simulation Setup
Gates and Inverters, while the Flip-Flop can operate in either
positive or negative edge-triggered modes. The report will delve Simulations were conducted in Cadence Virtuoso using
into the working principles, simulation setup, and analysis of TSMC 28nm node technology. The design parameters, input
critical parameters such as setup time, clock-to-Q delay, and conditions, and environmental factors were considered to
hold time. These simulations will provide valuable insights into
the performance and reliability of these digital circuits in modern
evaluate the performance of both the Static D-Latch and the
semiconductor technology. Master-Slave Flip-Flop.

I. I NTRODUCTION B. Static D-Latch Simulation

We all know that combinational logic circuits have the Simulation results for the Static D-Latch were analyzed
property that the output of a logic block is only a function for stability, speed, and power consumption. The output
of the current input values. Yet virtually all useful systems characteristics were observed concerning various input
require storage of state information, leading to another class conditions.
of circuits called sequential logic circuits. In these circuits, the
output not only depends upon the current values of the inputs,
but also upon preceding input values. There are two types of
sequential logic circuits Static and Dynamic. The basic circuit
diagram of static latch is shown in Fig 1. When CLK is high,
the bottom transmission gate is on and the latch is transparent
- that is, the D input is copied to the Q output. During this
phase, the feedback loop is open since the top transmission
gate is off. When CLK is high, the latch samples the D input,
while a low clock-signal enables the feedback-loop, and puts
the latch in the hold mode. The set-up time (t su) is the time
that the data inputs (D input) must be valid before the clock
transition (this is, the 0 to 1 transition for a positive edge-
triggered register). The hold time (thold) is the time the data
input must remain valid after the clock edge. The time taken
for Data D to reach at output after clock edge is called tc−q .
Fig. 1. Static D Latch circuit Daigram
II. W ORKING P RINCIPLE
A. Static D-Latch using TG and Inverter C. Master-Slave Flip-Flop Simulation
The Static D-Latch utilizes a Transmission Gate (TG) and The Master-Slave Flip-Flop was simulated in positive
an Inverter to store and latch data. The TG acts as a switch, and negative edge-triggered modes. Clock-to-Q delays, setup
allowing data to be latched when the latch enable signal is times, and hold times were measured to assess the performance
asserted. The Inverter ensures stable output states. of the Flip-Flop.
 /Q_bar Y

/Q_bar X
6
/Q Y

/Q X
5
/CLK_bar Y

/CLK_bar X

Offset Y values
4 /CLK Y

/CLK X

Fig. 2. Master slave flipflop circuit 3

/D Y

D. Equivalent Circuit daigram for Calculation of setup, hold

time and clock to Q delay 0
9
×10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

/D X

Fig. 5. characteristic of static D latch

B. Master-Slave Flip-Flop Analysis

Analyze the simulation results of the Master-Slave Flip-

Flop, focusing on clock-to-Q delays, setup times, and hold
times in positive and negative edge-triggered configurations.

Fig. 3. Equiavalent circuit fo calculation of clock to Q delay

1) clock to Q delay calculation result waveform:

/D Y

/D X
each wave form logic level range from 0 to 1 ( in volts )

3.5
/CLK Y

/CLK X
3.0
/Q Y

2.5

2.0

1.5

Fig. 4. Equiavalent circuit fo calculation of setup time 1.0

0.5

0.0

IV. R ESULT AND D ISCUSSION 0.0 200.0p 400.0p 600.0p 800.0p 1.0n 1.2n 1.4n

X(in seconds)

Fig. 6. clock to Q delay calculation result

A. Static D-Latch Analysis

1) output characteristic of d latch: 2) setup time calculation result waveform:

 /CLK Y
3.75
/CLK X
3.5
logic level of each wave range from 0 to 1(in volts)

/D Y

/D X
3.0
/Q Y

2.5

2.0

1.5

1.0

0.5

0.0

-0.25

0.0 200.0p 400.0p 600.0p 800.0p 1.0n 1.2n 1.4n

X (time in sec)

Fig. 7. setup time calculation result

V. C ONCLUSION
In this report the design of D-Latch, Master Slave Flip Flop
has been implemented using transistors. The schematic and
simulations has beenn performed in cadence virtuoso. The D-
latch and Master Slave Flip Flop have been implemented using
transmission gate. The setup time which is the time before
which the input must be stable before the clock arrives is
evaluated. Similarly the hod time, which is the time for which
the data should be held stable after the clock arrives is also
calculated. After that the worst case propagation delay of the
Data to output Q after clock arrives (tc−q ) is also calculated.
All the results are shown in the respective section.
R EFERENCES
[1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated Circuits - A Design Perspective, 2nd Edition,
Indian Edition. Prentice Hall, © 2016.
 TG and PTL Based Dynamic Sequential Logic
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in

AIM: To design the dynamic Transmission Gate (TG) and

PTL(Pass transistor logic) based edge triggered flipflop and to VDD S_BAR
VDD
calculate the timing parameters like setup time,hold time and +
− VDC=1
VDD

A INVERTER Y
A Y A INVERTER Y

clock-to-Q delay. GND GND

GND S

+
Abstract—This report presents the investigation and −

VDD
assessment of dynamic Transmission Gate (TG) and PTL +
− A INVERTER Y

(Pass transistor logic) based flipflop using TSMC 28nm node GND

technology in Cadence Virtuoso. The timing parameters, such

as setup time, hold time, and clock-to-Q delay, are the main
GND
focus.To validate these features and to compare the static and
dynamic sequential logic, the simulation results are carefully
examined. Fig. 1. TG-Based Dynamic Flip-Flop Circuit Daigram

1) Equivalent Circuit for Setup-Time: The analysis of the

I. I NTRODUCTION setup-time equivalent circuit delves into the interplay among
the clock signal, data input, and output stability within the
Information is stored and transferred by dynamic flip-flops us- setup period. This entails comprehending the timing limitations
ing dynamic circuit techniques like charge sharing and dynamic necessary for dependable data retention.
nodes. Within digital circuits, more precisely sequential logic, a 2) Equivalent Circuit for TC-Q Calculation: The equivalent
rising (positive) clock signal causes a positive edge-triggered flip- circuit for Clock-to-Q delay (TC-Q) calculation determines the
flop to respond to changes in input signals. Flip-flop Q and Q’ time it takes for the output to respond to a clock transition,
outputs are only updated when the clock signal changes from a influencing the Flip-Flop’s speed.
low to a high state (0 to 1).
3) Analysis for Hold-Time: Hold-time analysis ensures the
A. TG based positive edge flipflop data input remains stable for a minimum duration after the clock
transition, preventing data corruption.
An edge-triggered dynamic flip-flop with transfer gates com-
bines the concepts of dynamic functionality and efficient data flow
control. This component is crucial in digital systems because it B. PTL-Based Dynamic Flip-Flop
plays a significant role in the reliability and overall efficiency of
sequential logic circuits. Exact performance data, transistor sizes
and placement will vary depending on the technology chosen and The PTL-based dynamic Flip-Flop employs Pass-Transistor
the desired characteristics of the flip-flop. Logic for storage, providing an alternative approach to dynamic
storage.
B. PTL based positive edge flipflop
A positive-edge-triggered flip-flop based on pass-transistor
logic uses the dynamic behavior of pass-transistors to both store
and process binary data. Its positive edge triggering ensures
synchronization with clock transitions, while the inclusion of
PTL offers potential advantages in terms of simplicity and speed.
However, specific implementation aspects and trade-offs must be
thoroughly evaluated according to the needs of the digital system.

II. W ORKING P RINCIPLE Fig. 2. PTL-Based Dynamic Flip-Flop circuit diagram

A. TG-Based Dynamic Flip-Flop

1) Equivalent Circuit for Setup-Time: Similar to the TG-
The TG-based dynamic Flip-Flop uses Transmission Gates based Flip-Flop, the PTL-based Flip-Flop involves an equivalent
for storage. Transmission Gates act as switches during clock circuit for setup-time calculation, ensuring reliable data storage.
transitions, facilitating dynamic information storage.
 Fig. 6. waveforms for calculation of clock to Q delay
Fig. 3. Equivalent Circuit for Setup-Time calculation
B. PTL-Based Dynamic Flip-Flop Simulation
2) Equivalent Circuit for TC-Q Calculation: The equivalent Simulations for the PTL-based Flip-Flop evaluated its perfor-
circuit for TC-Q calculation in PTL Flip-Flop considers the mance in terms of stability, speed, and power consumption under
specific characteristics of Pass-Transistor Logic, affecting the different input conditions.
Flip-Flop’s speed. 1) setup time graph:

Fig. 4. Equivalent Circuit for Setup-Time calculation

Fig. 7. waveforms for calculation of setup time
3) Analysis for Hold-Time: Hold-time analysis for the PTL
Flip-Flop focuses on ensuring stable data input after the clock 2) clock to Q delay graph:
transition, analogous to the TG-based Flip-Flop.

III. S IMULATION

A. TG-Based Dynamic Flip-Flop Simulation

Simulation results for the TG-based Flip-Flop were
analyzed for stability, speed, and power consumption. Output
characteristics were observed under various input conditions.

1) setup time graph:

Fig. 8. waveforms for calculation of clock to Q delay

IV. R ESULT AND D ISCUSSION

A. TG-Based Flip-Flop Analysis

Discussion of the TG-based Flip-Flop’s simulation results

includes output characteristics, and stability. Insights into the
Flip-Flop’s performance provide a comprehensive understanding
of its behavior.
Fig. 5. waveforms for calculation of setup time 1) calculated value of setup time and tcq delay:

2) clock to Q delay graph: • tcq delay :9.412 ps

 • tsetup : 7.672 ps

B. PTL-Based Flip-Flop Analysis

Analysis of the PTL-based Flip-Flop’s simulation results focuses

on output characteristics, power consumption, and stability,
offering a comparative study with the TG-based Flip-Flop.

1) calculated value of setup time and tcq delay:

• tcq delay : 12.24 ps

• tsetup : 3.88 ps

V. C ONCLUSION
R EFERENCES
[1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated Circuits - A Design Perspective, 2nd Edition, Indian
Edition. Prentice Hall, © 2016.