74AUP1G74

Low-power D-type flip-flop with set and reset; positive-edge

trigger
Rev. 8 — 23 January 2013 Product data sheet

1. General description
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F Class 3A exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP1G74DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
74AUP1G74GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1  1.95  0.5 mm
74AUP1G74GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1089
8 terminals; body 1.35  1  0.5 mm
74AUP1G74GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3  2  0.5 mm
74AUP1G74GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; SOT902-2
8 terminals; body 1.6  1.6  0.5 mm
74AUP1G74GN 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1116
8 terminals; body 1.2  1.0  0.35 mm
74AUP1G74GS 40 C to +125 C XSON8 extremely thin small outline package; no leads; SOT1203
8 terminals; body 1.35  1.0  0.35 mm

4. Marking
Table 2. Marking codes
Type number Marking code[1]
74AUP1G74DC p74
74AUP1G74GT p74
74AUP1G74GF 54
74AUP1G74GD p74
74AUP1G74GM p74
74AUP1G74GN 54
74AUP1G74GS 54

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

SD

SD
D Q
D Q
CP S
CP
FF C1
Q
Q 1D
RD
R
RD 001aah725 001aah726

Fig 1. Logic symbol Fig 2. IEC logic symbol

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 2 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Q
C

C
C
C
D
Q

C C
RD

SD
001aae087

CP C

Fig 3. Logic diagram

6. Pinning information

6.1 Pinning

74AUP1G74

CP 1 8 VCC

D 2 7 SD

74AUP1G74
Q 3 6 RD
CP 1 8 VCC
D 2 7 SD
GND 4 5 Q
Q 3 6 RD
GND 4 5 Q 001aae323

001aae322 Transparent top view

Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089,

SOT1116 and SOT1203

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 3 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

74AUP1G74
terminal 1

VCC
index area

8
SD 1 7 CP
74AUP1G74

CP 1 8 VCC
RD 2 6 D
D 2 7 SD

Q 3 6 RD Q 3 5 Q

4
GND 4 5 Q

GND
001aae324
001aai217

Transparent top view Transparent top view

Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2

6.2 Pin description

Table 3. Pin description
Symbol Pin Description
SOT765-1, SOT833-1, SOT1089, SOT902-2
SOT996-2, SOT1116 and SOT1203
CP 1 7 clock input
D 2 6 data input
Q 3 5 complement output
GND 4 4 ground (0 V)
Q 5 3 true output
RD 6 2 asynchronous reset input (active LOW)
SD 7 1 asynchronous set input (active LOW)
VCC 8 8 supply voltage

7. Functional description
Table 4. Function table for asynchronous operation[1]
Input Output
SD RD CP D Q Q
L H X X H L
H L X X L H
L L X X H H

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 4 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 5. Function table for synchronous operation[1]

Input Output
SD RD CP D Qn+1 Qn+1
H H  L L H
H H  H H L

[1] H = HIGH voltage level;

L = LOW voltage level;
X = don’t care;
 = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.

8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI < 0 V 50 - mA
VI input voltage [1] 0.5 +4.6 V
IOK output clamping current VO < 0 V 50 - mA
VO output voltage Active mode and Power-down mode [1] 0.5 +4.6 V
IO output current VO = 0 V to VCC - 20 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [2] - 250 mW

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.

9. Recommended operating conditions

Table 7. Operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.8 3.6 V
VI input voltage 0 3.6 V
VO output voltage Active mode 0 VCC V
Power-down mode; VCC = 0 V 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 0.8 V to 3.6 V - 200 ns/V

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 5 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

10. Static characteristics

Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70  VCC - - V
VCC = 0.9 V to 1.95 V 0.65  VCC - - V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30  VCC V
VCC = 0.9 V to 1.95 V - - 0.35  VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.75  VCC - - V
IO = 1.7 mA; VCC = 1.4 V 1.11 - - V
IO = 1.9 mA; VCC = 1.65 V 1.32 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V
II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A
IOFF additional power-off VI or VO = 0 V to 3.6 V; - - 0.2 A
leakage current VCC = 0 V to 0.2 V
ICC supply current VI = GND or VCC; IO = 0 A; - - 0.5 A
VCC = 0.8 V to 3.6 V
ICC additional supply current VI = VCC  0.6 V; IO = 0 A; [1] - - 40 A
VCC = 3.3 V; per pin
CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.6 - pF
CO output capacitance VO = GND; VCC = 0 V - 1.3 - pF

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 6 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 8. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70  VCC - - V
VCC = 0.9 V to 1.95 V 0.65  VCC - - V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30  VCC V
VCC = 0.9 V to 1.95 V - - 0.35  VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.7  VCC - - V
IO = 1.7 mA; VCC = 1.4 V 1.03 - - V
IO = 1.9 mA; VCC = 1.65 V 1.30 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V
II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off VI or VO = 0 V to 3.6 V; - - 0.6 A
leakage current VCC = 0 V to 0.2 V
ICC supply current VI = GND or VCC; IO = 0 A; - - 0.9 A
VCC = 0.8 V to 3.6 V
ICC additional supply current VI = VCC  0.6 V; IO = 0 A; [1] - - 50 A
VCC = 3.3 V; per pin

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 7 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 8. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 0.8 V 0.75  VCC - - V
VCC = 0.9 V to 1.95 V 0.70  VCC - - V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25  VCC V
VCC = 0.9 V to 1.95 V - - 0.30  VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.11 - - V
IO = 1.1 mA; VCC = 1.1 V 0.6  VCC - - V
IO = 1.7 mA; VCC = 1.4 V 0.93 - - V
IO = 1.9 mA; VCC = 1.65 V 1.17 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V
II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A
IOFF additional power-off VI or VO = 0 V to 3.6 V; - - 0.75 A
leakage current VCC = 0 V to 0.2 V
ICC supply current VI = GND or VCC; IO = 0 A; - - 1.4 A
VCC = 0.8 V to 3.6 V
ICC additional supply current VI = VCC  0.6 V; IO = 0 A; [1] - - 75 A
VCC = 3.3 V; per pin

[1] One input at VCC  0.6 V, other input at VCC or GND.

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 8 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

11. Dynamic characteristics

Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
(85 C) (125 C)
CL = 5 pF
tpd propagation CP to Q, Q; see Figure 8 [2]

delay VCC = 0.8 V - 25.4 - - - - - ns

VCC = 1.1 V to 1.3 V 2.9 6.7 14.0 2.6 14.2 2.6 14.2 ns
VCC = 1.4 V to 1.6 V 2.4 4.5 7.6 2.3 8.3 2.3 8.6 ns
VCC = 1.65 V to 1.95 V 1.9 3.5 5.7 1.7 6.5 1.7 6.8 ns
VCC = 2.3 V to 2.7 V 1.7 2.6 3.8 1.4 4.4 1.4 4.7 ns
VCC = 3.0 V to 3.6 V 1.5 2.2 3.1 1.2 3.4 1.2 3.7 ns
SD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 19.6 - - - - - ns

VCC = 1.1 V to 1.3 V 2.7 5.6 11.0 2.5 11.4 2.5 11.5 ns
VCC = 1.4 V to 1.6 V 2.4 4.0 6.3 2.2 6.9 2.2 7.3 ns
VCC = 1.65 V to 1.95 V 2.0 3.3 4.9 1.7 5.6 1.7 5.9 ns
VCC = 2.3 V to 2.7 V 1.9 2.7 3.7 1.7 4.0 1.7 4.2 ns
VCC = 3.0 V to 3.6 V 1.8 2.5 3.2 1.5 3.6 1.5 3.8 ns
RD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 19.2 - - - - - ns

VCC = 1.1 V to 1.3 V 2.6 5.5 11.0 2.5 11.3 2.5 11.5 ns
VCC = 1.4 V to 1.6 V 2.3 3.9 6.3 2.2 6.8 2.2 7.3 ns
VCC = 1.65 V to 1.95 V 1.9 3.2 5.0 1.8 5.6 1.8 5.9 ns
VCC = 2.3 V to 2.7 V 1.9 2.6 3.6 1.7 4.1 1.7 4.3 ns
VCC = 3.0 V to 3.6 V 1.8 2.4 3.3 1.5 3.6 1.5 3.8 ns
fmax maximum CP; see Figure 9
frequency VCC = 0.8 V - 53 - - - - - MHz
VCC = 1.1 V to 1.3 V - 203 - 170 - 170 - MHz
VCC = 1.4 V to 1.6 V - 347 - 310 - 300 - MHz
VCC = 1.65 V to 1.95 V - 435 - 400 - 390 - MHz
VCC = 2.3 V to 2.7 V - 550 - 490 - 480 - MHz
VCC = 3.0 V to 3.6 V - 619 - 550 - 510 - MHz

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 9 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
(85 C) (125 C)
CL = 10 pF
tpd propagation CP to Q, Q; see Figure 8 [2]

delay VCC = 0.8 V - 28.9 - - - - - ns

VCC = 1.1 V to 1.3 V 3.1 7.5 15.8 2.9 16.1 2.9 16.1 ns
VCC = 1.4 V to 1.6 V 2.7 5.1 8.7 2.4 9.4 2.4 9.8 ns
VCC = 1.65 V to 1.95 V 2.5 4.1 6.5 2.2 7.2 2.2 7.6 ns
VCC = 2.3 V to 2.7 V 2.0 3.2 4.6 1.8 5.3 1.8 5.6 ns
VCC = 3.0 V to 3.6 V 1.8 2.8 3.8 1.6 4.1 1.6 4.4 ns
SD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 23.2 - - - - - ns

VCC = 1.1 V to 1.3 V 2.9 6.5 12.9 2.8 13.3 2.8 13.5 ns
VCC = 1.4 V to 1.6 V 2.7 4.6 7.5 2.3 7.9 2.3 8.3 ns
VCC = 1.65 V to 1.95 V 2.6 3.9 5.6 2.3 6.3 2.3 6.6 ns
VCC = 2.3 V to 2.7 V 2.3 3.2 4.4 2.0 4.8 2.0 5.2 ns
VCC = 3.0 V to 3.6 V 2.2 3.0 3.9 1.9 4.2 1.9 4.4 ns
RD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 22.7 - - - - - ns

VCC = 1.1 V to 1.3 V 2.8 6.4 12.8 2.7 13.2 2.7 13.4 ns
VCC = 1.4 V to 1.6 V 2.6 4.5 7.5 2.3 8.1 2.3 8.4 ns
VCC = 1.65 V to 1.95 V 2.5 3.3 5.8 2.3 6.3 2.3 6.7 ns
VCC = 2.3 V to 2.7 V 2.2 3.2 4.4 2.0 4.9 2.0 5.2 ns
VCC = 3.0 V to 3.6 V 2.0 2.9 4.0 1.9 4.3 1.9 4.5 ns
fmax maximum CP; see Figure 9
frequency VCC = 0.8 V - 52 - - - - - MHz
VCC = 1.1 V to 1.3 V - 192 - 150 - 150 - MHz
VCC = 1.4 V to 1.6 V - 324 - 280 - 230 - MHz
VCC = 1.65 V to 1.95 V - 421 - 310 - 250 - MHz
VCC = 2.3 V to 2.7 V - 486 - 370 - 360 - MHz
VCC = 3.0 V to 3.6 V - 550 - 410 - 360 - MHz

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 10 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
(85 C) (125 C)
CL = 15 pF
tpd propagation CP to Q, Q; see Figure 8 [2]

delay VCC = 0.8 V - 32.4 - - - - - ns

VCC = 1.1 V to 1.3 V 3.5 8.3 17.6 3.3 17.8 3.3 18.0 ns
VCC = 1.4 V to 1.6 V 3.2 5.6 9.5 2.8 10.5 2.8 11.1 ns
VCC = 1.65 V to 1.95 V 2.7 4.6 7.2 2.5 8.1 2.5 8.6 ns
VCC = 2.3 V to 2.7 V 2.4 3.6 5.2 2.2 5.8 2.2 6.2 ns
VCC = 3.0 V to 3.6 V 2.2 3.2 4.4 2.0 4.9 2.0 5.2 ns
SD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 26.7 - - - - - ns

VCC = 1.1 V to 1.3 V 3.3 7.3 14.7 3.1 15.2 3.1 15.4 ns
VCC = 1.4 V to 1.6 V 3.2 5.2 8.3 2.9 9.0 2.9 9.5 ns
VCC = 1.65 V to 1.95 V 2.8 4.3 6.4 2.5 7.1 2.5 7.5 ns
VCC = 2.3 V to 2.7 V 2.8 3.7 5.1 2.2 5.5 2.2 5.8 ns
VCC = 3.0 V to 3.6 V 2.5 3.5 4.6 2.4 5.0 2.4 5.2 ns
RD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 26.1 - - - - - ns

VCC = 1.1 V to 1.3 V 3.2 7.2 14.5 3.1 15.0 3.1 15.2 ns
VCC = 1.4 V to 1.6 V 3.1 5.1 8.4 2.7 9.2 2.7 9.7 ns
VCC = 1.65 V to 1.95 V 2.7 4.3 6.5 2.6 7.3 2.6 7.7 ns
VCC = 2.3 V to 2.7 V 2.6 3.6 5.0 2.4 5.5 2.4 5.8 ns
VCC = 3.0 V to 3.6 V 2.4 3.4 4.6 2.3 5.0 2.3 5.2 ns
fmax maximum CP; see Figure 9
frequency VCC = 0.8 V - 50 - - - - - MHz
VCC = 1.1 V to 1.3 V - 181 - 120 - 120 - MHz
VCC = 1.4 V to 1.6 V - 301 - 190 - 160 - MHz
VCC = 1.65 V to 1.95 V - 407 - 240 - 190 - MHz
VCC = 2.3 V to 2.7 V - 422 - 300 - 270 - MHz
VCC = 3.0 V to 3.6 V - 481 - 320 - 300 - MHz

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NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
(85 C) (125 C)
CL = 30 pF
tpd propagation CP to Q, Q; see Figure 8 [2]

delay VCC = 0.8 V - 42.7 - - - - - ns

VCC = 1.1 V to 1.3 V 4.2 10.6 22.5 4.0 23.0 4.0 23.3 ns
VCC = 1.4 V to 1.6 V 3.7 7.2 12.0 3.7 13.3 3.7 14.0 ns
VCC = 1.65 V to 1.95 V 3.5 5.8 9.2 3.4 10.4 3.4 11.0 ns
VCC = 2.3 V to 2.7 V 3.3 4.7 6.6 3.0 7.3 3.0 7.8 ns
VCC = 3.0 V to 3.6 V 3.0 4.3 5.8 2.8 6.8 2.8 7.3 ns
SD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 37.0 - - - - - ns

VCC = 1.1 V to 1.3 V 4.0 9.5 19.8 3.8 20.8 3.8 21.1 ns
VCC = 1.4 V to 1.6 V 3.8 6.7 10.9 3.7 12.0 3.7 12.7 ns
VCC = 1.65 V to 1.95 V 3.7 5.6 8.4 3.5 9.3 3.5 9.9 ns
VCC = 2.3 V to 2.7 V 3.7 4.8 6.6 3.2 7.2 3.2 7.6 ns
VCC = 3.0 V to 3.6 V 3.4 4.6 6.0 3.1 6.8 3.1 7.1 ns
RD to Q, Q; see Figure 9 [2]

VCC = 0.8 V - 36.4 - - - - - ns

VCC = 1.1 V to 1.3 V 3.9 9.4 19.5 3.8 20.2 3.8 20.5 ns
VCC = 1.4 V to 1.6 V 3.6 6.6 10.9 3.7 12.0 3.7 12.6 ns
VCC = 1.65 V to 1.95 V 3.5 5.5 8.5 3.5 9.5 3.5 10.1 ns
VCC = 2.3 V to 2.7 V 3.5 4.7 6.5 3.2 7.1 3.2 7.6 ns
VCC = 3.0 V to 3.6 V 3.3 4.4 6.1 3.1 7.1 3.1 7.5 ns
fmax maximum CP; see Figure 9
frequency VCC = 0.8 V - 28 - - - - - MHz
VCC = 1.1 V to 1.3 V - 145 - 70 - 70 - MHz
VCC = 1.4 V to 1.6 V - 185 - 120 - 110 - MHz
VCC = 1.65 V to 1.95 V - 270 - 150 - 120 - MHz
VCC = 2.3 V to 2.7 V - 290 - 190 - 170 - MHz
VCC = 3.0 V to 3.6 V - 315 - 200 - 190 - MHz

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Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
(85 C) (125 C)
CL = 5 pF, 10 pF, 15 pF and 30 pF
tsu set-up time D to CP HIGH;
see Figure 8
VCC = 0.8 V - 3.4 - - - - - ns
VCC = 1.1 V to 1.3 V - 0.6 - 1.2 - 1.2 - ns
VCC = 1.4 V to 1.6 V - 0.3 - 0.6 - 0.6 - ns
VCC = 1.65 V to 1.95 V - 0.4 - 0.5 - 0.5 - ns
VCC = 2.3 V to 2.7 V - 0.2 - 0.4 - 0.4 - ns
VCC = 3.0 V to 3.6 V - 0.3 - 0.4 - 0.4 - ns
D to CP LOW;
see Figure 8
VCC = 0.8 V - 3.0 - - - - - ns
VCC = 1.1 V to 1.3 V - 0.5 - 1.2 - 1.2 - ns
VCC = 1.4 V to 1.6 V - 0.3 - 0.7 - 0.7 - ns
VCC = 1.65 V to 1.95 V - 0.4 - 0.7 - 0.7 - ns
VCC = 2.3 V to 2.7 V - 0.5 - 0.7 - 0.7 - ns
VCC = 3.0 V to 3.6 V - 0.6 - 0.8 - 0.8 - ns
th hold time D to CP; see Figure 8
VCC = 0.8 V - 1.9 - - - - - ns
VCC = 1.1 V to 1.3 V - 0.3 - 0.5 - 0.5 - ns
VCC = 1.4 V to 1.6 V - 0.2 - 0.2 - 0.2 - ns
VCC = 1.65 V to 1.95 V - 0.2 - 0.1 - 0.1 - ns
VCC = 2.3 V to 2.7 V - 0.2 - 0.1 - 0.1 - ns
VCC = 3.0 V to 3.6 V - 0.2 - 0.1 - 0.1 - ns
trec recovery time RD; see Figure 9
VCC = 1.1 V to 1.3 V - 0.5 - 0.9 - 0.9 - ns
VCC = 1.4 V to 1.6 V - 0.2 - 0.6 - 0.6 - ns
VCC = 1.65 V to 1.95 V - 0.2 - 0.4 - 0.4 - ns
VCC = 2.3 V to 2.7 V - 0.1 - 0.1 - 0.1 - ns
VCC = 3.0 V to 3.6 V - 0.1 - 0.1 - 0.1 - ns
SD; see Figure 9
VCC = 1.1 V to 1.3 V - 0.5 - 0.3 - 0.3 - ns
VCC = 1.4 V to 1.6 V - 0.4 - 0.1 - 0.1 - ns
VCC = 1.65 V to 1.95 V - 0.3 - 0 - 0 - ns
VCC = 2.3 V to 2.7 V - 0.2 - 0.1 - 0.1 - ns
VCC = 3.0 V to 3.6 V - 0.1 - 0.1 - 0.1 - ns

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Low-power D-type flip-flop with set and reset; positive-edge trigger

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
(85 C) (125 C)
tW pulse width CP HIGH or LOW;
see Figure 8
VCC = 1.1 V to 1.3 V - 2.1 - 2.7 - 2.7 - ns
VCC = 1.4 V to 1.6 V - 1.1 - 1.5 - 1.5 - ns
VCC = 1.65 V to 1.95 V - 0.9 - 1.6 - 1.6 - ns
VCC = 2.3 V to 2.7 V - 0.6 - 1.7 - 1.7 - ns
VCC = 3.0 V to 3.6 V - 0.6 - 1.9 - 1.9 - ns
SD or RD LOW;
see Figure 9
VCC = 1.1 V to 1.3 V - 4.2 - 11.3 - 11.5 - ns
VCC = 1.4 V to 1.6 V - 2.3 - 6.2 - 6.4 - ns
VCC = 1.65 V to 1.95 V - 1.8 - 4.8 - 5.0 - ns
VCC = 2.3 V to 2.7 V - 1.2 - 3.3 - 3.5 - ns
VCC = 3.0 V to 3.6 V - 1.1 - 2.6 - 2.8 - ns
CPD power fi = 1 MHz; [3]

dissipation VI = GND to VCC

capacitance VCC = 0.8 V - 2.8 - - - - - pF
VCC = 1.1 V to 1.3 V - 2.9 - - - - - pF
VCC = 1.4 V to 1.6 V - 3.0 - - - - - pF
VCC = 1.65 V to 1.95 V - 3.0 - - - - - pF
VCC = 2.3 V to 2.7 V - 3.5 - - - - - pF
VCC = 3.0 V to 3.6 V - 3.9 - - - - - pF

[1] All typical values are measured at nominal VCC.

[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.

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Low-power D-type flip-flop with set and reset; positive-edge trigger

12. Waveforms

tW
VI

CP input VM

GND

1/fmax
VI

D input VM

GND
th th
t su t su
t PHL t PLH
VOH

Q output VM

VOL

VOH

Q output VM

VOL
t PLH t PHL
001aae365

Measurement points are given in Table 10.

The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the data input (D) to clock input (CP) set-up and
hold times and the clock input (CP) pulse width and maximum frequency

Table 10. Measurement points

Supply voltage Output Input
VCC VM VM VI tr = tf
0.8 V to 3.6 V 0.5  VCC 0.5  VCC VCC  3.0 ns

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Low-power D-type flip-flop with set and reset; positive-edge trigger

VI

CP input VM

GND
t rec
VI

SD input VM

GND t rec
tW tW
VI

RD input VM

GND
t PLH t PHL
VOH

Q output VM

VOL

VOH

Q output VM

VOL
t PHL t PLH 001aae366

Measurement points are given in Table 10.

VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The set input (SD) and reset input (RD) to output (Q, Q) propagation delays, the set input (SD) and reset
input (RD) pulse widths and the reset input (RD) to clock input (CP) recovery time

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NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

VCC VEXT

5 kΩ
VI VO
G DUT

RT CL RL

001aac521

Test data is given in Table 11.

Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times

Table 11. Test data

Supply voltage Load VEXT
VCC CL RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2  VCC

[1] For measuring enable and disable times RL = 5 k

For measuring propagation delays, setup and hold times and pulse width RL = 1 M.

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Low-power D-type flip-flop with set and reset; positive-edge trigger

13. Package outline

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1

D E A
X

y HE v M A

8 5

A2
A
A1
(A3)
pin 1 index

θ
Lp

L
1 4 detail X

e w M
bp

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ
max.
0.15 0.85 0.27 0.23 2.1 2.4 3.2 0.40 0.21 0.4 8°
mm 1 0.12 0.5 0.4 0.2 0.13 0.1
0.00 0.60 0.17 0.08 1.9 2.2 3.0 0.15 0.19 0.1 0°

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

SOT765-1 MO-187 02-06-07

Fig 11. Package outline SOT765-1 (VSSOP8)

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Product data sheet Rev. 8 — 23 January 2013 18 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1

b
1 2 3 4

4×
L (2)
L1

8 7 6 5
e1 e1 e1

8× A
(2)

A1

terminal 1
index area

0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)

UNIT A(1) A1 b D E e e1 L L1
max max
0.25 2.0 1.05 0.35 0.40
mm 0.5 0.04 0.6 0.5
0.17 1.9 0.95 0.27 0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

07-11-14
SOT833-1 --- MO-252 ---
07-12-07

Fig 12. Package outline SOT833-1 (XSON8)

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Product data sheet Rev. 8 — 23 January 2013 19 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1 x 0.5 mm SOT1089

terminal 1
index area

D A
A1

detail X

(4×)(2)
e

L
(8×)(2)

b 4 5

e1

1 8

terminal 1
index area L1 X
0 0.5 1 mm

Dimensions scale

Unit A(1) A1 b D E e e1 L L1

max 0.5 0.04 0.20 1.40 1.05 0.35 0.40

mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35
min 0.12 1.30 0.95 0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology. sot1089_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
10-04-09
SOT1089 MO-252
10-04-12

Fig 13. Package outline SOT1089 (XSON8)

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Low-power D-type flip-flop with set and reset; positive-edge trigger

XSON8: plastic extremely thin small outline package; no leads;

8 terminals; body 3 x 2 x 0.5 mm SOT996-2

D B A

E A A1

detail X

terminal 1
index area

e1
C
v C A B
L1 e b
w C y1 C y
1 4

L2

8 5
X

0 1 2 mm
scale

Dimensions (mm are the original dimensions)

Unit(1) A A1 b D E e e1 L L1 L2 v w y y1

max 0.05 0.35 2.1 3.1 0.5 0.15 0.6

mm nom 0.5 0.5 1.5 0.1 0.05 0.05 0.1
min 0.00 0.15 1.9 2.9 0.3 0.05 0.4
sot996-2_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
07-12-21
SOT996-2
12-11-20

Fig 14. Package outline SOT996-2 (XSON8)

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NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

XQFN8: plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2

D B A

terminal 1
index area

E A

A1

detail X

e
C
v C A B
b
w C y1 C y
4

3 5
e1

2 6

1 7

terminal 1 8
index area L metal area
not for soldering

L1

0 1 2 mm

Dimensions scale

Unit(1) A A1 b D E e e1 L L1 v w y y1

max 0.5 0.05 0.25 1.65 1.65 0.35 0.15

mm nom 0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.1 0.05 0.05 0.05
min 0.00 0.15 1.55 1.55 0.25 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot902-2_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
10-11-02
SOT902-2 --- MO-255 ---
11-03-31

Fig 15. Package outline SOT902-2 (XQFN8)

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Product data sheet Rev. 8 — 23 January 2013 22 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116

b
1 2 3 4 (4×)(2)

L1 L

8 7 6 5

e1 e1 e1

(8×)(2)
A1 A

terminal 1
index area

0 0.5 1 mm

Dimensions scale

Unit A(1) A1 b D E e e1 L L1

max 0.35 0.04 0.20 1.25 1.05 0.35 0.40

mm nom 0.15 1.20 1.00 0.55 0.3 0.30 0.35
min 0.12 1.15 0.95 0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology. sot1116_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
10-04-02
SOT1116
10-04-07

Fig 16. Package outline SOT1116 (XSON8)

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Product data sheet Rev. 8 — 23 January 2013 23 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203

b
1 2 3 4 (4×)(2)

L1 L

8 7 6 5
e1 e1 e1

(8×)(2)
A1 A

terminal 1
index area

0 0.5 1 mm

Dimensions scale

Unit A(1) A1 b D E e e1 L L1

max 0.35 0.04 0.20 1.40 1.05 0.35 0.40

mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35
min 0.12 1.30 0.95 0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology. sot1203_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
10-04-02
SOT1203
10-04-06

Fig 17. Package outline SOT1203 (XSON8)

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NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

14. Abbreviations
Table 12. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model

15. Revision history

Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AUP1G74 v.8 20130123 Product data sheet - 74AUP1G74 v.7
Modifications: • For type number 74AUP1G74GD XSON8U has changed to XSON8.
74AUP1G74 v.7 20120522 Product data sheet - 74AUP1G74 v.6
74AUP1G74 v.6 20111128 Product data sheet - 74AUP1G74 v.5
74AUP1G74 v.5 20100726 Product data sheet - 74AUP1G74 v.4
74AUP1G74 v.4 20080603 Product data sheet - 74AUP1G74 v.3
74AUP1G74 v.3 20080207 Product data sheet - 74AUP1G74 v.2
74AUP1G74 v.2 20070515 Product data sheet - 74AUP1G74 v.1
74AUP1G74 v.1 20060825 Product data sheet - -

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Product data sheet Rev. 8 — 23 January 2013 25 of 28

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Low-power D-type flip-flop with set and reset; positive-edge trigger

16. Legal information

16.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
16.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 26 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

Export control — This document as well as the item(s) described herein product for such automotive applications, use and specifications, and (b)
may be subject to export control regulations. Export might require a prior whenever customer uses the product for automotive applications beyond
authorization from competent authorities. NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
Non-automotive qualified products — Unless this data sheet expressly
liability, damages or failed product claims resulting from customer design and
states that this specific NXP Semiconductors product is automotive qualified,
use of the product for automotive applications beyond NXP Semiconductors’
the product is not suitable for automotive use. It is neither qualified nor tested
standard warranty and NXP Semiconductors’ product specifications.
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
16.4 Trademarks
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.

Product data sheet Rev. 8 — 23 January 2013 27 of 28

NXP Semiconductors 74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger

18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17 Contact information. . . . . . . . . . . . . . . . . . . . . 27
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2013. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 January 2013
Document identifier: 74AUP1G74