VCO with low supply sensitivity

Rachana Shidramshettar Arpita Bonageri Rakshita P Salageri

Electronics and Communication Electronics and Communication Electronics and Communication
Engineering Engineering Engineering
KLE Technological University KLE Technological University KLE Technological University
Hubli, India Hubli, India Hubli, India
rachanashidramshettar@gmail.com arpitabonageri30@gmail.com rakshitasalageri@gmail.com

Sanjana Madiwalar Dr.Sujata Kotabagi Bharat A Gunhalkar

Electronics and Communication Electronics and Communication Electronics and Communication
Engineering Engineering Engineering
KLE Technological University KLE Technological University KLE Technological University
Hubli, India Hubli, India Hubli, India
sanjanashiv@gmail.com sujatask@kletech.ac.in bharatgunhalkar8@gmail.com

Abstract—This paper presents a study of the design and anal- noise. The proposed VCO architecture employs innovative
ysis of voltage-controlled ring oscillators (VCOs) with minimal techniques to ensure stable operation regardless of power
sensitivity to power supply noise. The proposed approach uses supply variations, thereby enhancing overall integrated circuit
a three-stage ring oscillator architecture implemented using 180
nm CMOS technology. For this VCO, a frequency of 10 MHz performance and efficiency.
with a 51.1% duty cycle is achievable. The main idea is to
develop a voltage-controlled ring oscillator (VCO) that operates The study commences with implementing and scrutinizing
independently of the power supply on the application of 1.8 ± basic three-stage inverter-based ring oscillator architecture,
10% volt, thereby reducing the sensitivity of the VCO. followed by current-starved ring oscillator configurations.
Index Terms—Voltage Controlled Oscillator,Ring Oscilla-
tor,Phase Noise,Supply sensitivity
These initial implementations serve as benchmarks for
evaluating the performance of the final Voltage-Controlled
Ring Oscillator (VCO) architecture. Through comparative
analysis, the merits and drawbacks of each architecture are
I. I NTRODUCTION
systematically assessed, providing valuable insights into their
Voltage-Controlled Ring Oscillators (VCOs) play a critical suitability for diverse applications.
role in integrated circuit design, serving purposes from
clock generation to frequency synthesis. Their performance Additionally, the research incorporates comprehensive
significantly impacts electronic system functionality and PVT (Process, Voltage, Temperature) analysis to evaluate
reliability. In contemporary electronic devices, the ability the robustness and stability of the final VCO design.
to operate stably amidst power supply noise is paramount. By systematically varying process parameters, supply
Therefore, developing VCO architectures with minimal voltages(1.72V to 1.98V), and temperature conditions(),
sensitivity to power supply variations is imperative for the study quantifies the influence of environmental factors
enhancing overall integrated circuit performance and on VCO performance. This thorough analysis ensures that
efficiency. VCOs are electronic circuits that generate the proposed VCO architecture maintains stable operation
oscillatory signals whose frequency is modulated by an across a broad range of operating conditions, maintaining its
applied voltage. Typically, these circuits comprise a series reliability in practical applications.
of inverter stages connected in a loop, where the oscillation
frequency is dictated by the delay through each stage. Following is the paper arrangement
Past research in VCO design has explored various circuit 1) Section I introduces the study.:
topologies, optimization strategies, and performance analysis 2) Section II outlines the objectives.:
methodologies. However, traditional VCO architectures like 3) Section III reviews the literature.:
CMOS inverter-based and current-starved ring oscillators 4) Section IV details the specifications.:
have shown susceptibility to power supply variations, posing 5) Section V describes the different architectures.:
challenges in maintaining stable operation. This paper fills a 6) Section VI presents the final architecture.:
gap in the literature by presenting a study on designing and 7) Section VII showcases the results.:
analyzing VCOs with minimal sensitivity to power supply 8) Section VIII concludes the analysis.:
 II. O BJECTIVES The current flow through each branch of the inverter is
• Supply voltage varies from 1.72V to 1.98V. The circuit controlled through the temperature compensation circuit and
should handle this variation. is designed to have a sustained oscillation of 1MHz for
• To compare the performance metrics, such as frequency system-on-chip applications. The effects of temperature on
stability of the proposed VCO configuration with other the flow of current through the Mosfet and the mobility of the
architectures performed. mosfet are discussed. A frequency variation of ±2.5 across a
range of temperature -40°Cto 125°C is achieved through this
• To explore the frequency response characteristics and
design. The average drawn current from the voltage regulator
phase noise performance
is less than 42µA for all conditions. The overall frequency
variation achieved is ±3.5 percent [5].
III. LITERATURE SURVEY
In paper [1], different methods are explored to design The design of an Ultra-low frequency CMOS ring oscillator
VCOs with high power supply rejection ratios to minimize using a CMOS thyristor. The design proposed improves the
the impact of supply noise on the VCO frequency. The use output frequency of the sinusoidal waveform and reduces
of current-controlled oscillators and the problems associated static power dissipation. The 250nm technology is used. The
with their Power Supply Rejection Ratio are discussed. It also current through the transistors is controlled using pairs of
discusses some methods for generating a reference voltage current mirrors and the charging and discharging time of
and a level shifter to improve the Power Supply Rejection the load capacitor is increased. Further, the frequency of the
Ratio. The paper talks about Ring Oscillatorsand examples output waveform is reduced by using another pair of current
are provided for using replica circuits with local feedback mirrors. The effect of voltage and temperature variation on
and mainly focuses on VCOs with low sensitivityto power the time period of the output waveform is also discussed [6].
supply noise.
The design of a voltage-controlled ring oscillator based
Voltage Controlled Ring Oscillator for the reduction of on MOS transistor capacitance. The voltage-controlled ring
supply noise is discussed. The method discussed here includes oscillator is designed using a conventional 3-stage ring
the use of a bias current controller with a voltage-swing oscillator. The frequency range of VCO operates in the range
controller to maintain a constant oscillation frequency with the of 2.36-2.85 GHz with 6.99mW of power consumption. The
presence of supply noise and process variation. The 0.13µm phase noise is -76.27dBc/Hz. It has an application in wireless
CMOS technology is used with an operating frequency of communication [7].
4GHz.The oscillation frequency difference between different
process corners is about 6% of the frequency of oscillation in The literature review underscores several noteworthy
the nominal corner [2]. trends in Voltage-Controlled Oscillator (VCO) design. It
explores methods to enhance the Power Supply Rejection
A self-regulating resistor-free CMOS ring oscillator is Ratio (PSRR), including current-controlled oscillators
designed which is insensitive to supply noise variations. To and bias current controllers equipped with voltage-swing
improve noise immunity and stability of frequency across- controllers. Strategies for on-chip compensation are discussed
coupled dual latch-based system is designed and this paper to uphold stable oscillation frequencies despite supply noise
also discusses the drawback of a simple inverter design. The and process variation. Fresh approaches in CMOS ring
supply noise sensitivity is reduced by around 40% through oscillator design seek to diminish sensitivity to supply noise
the implementation of a five-stage ring oscillator. The 0.09µm fluctuations, often integrating cross-coupled dual latch-based
process technology is used and the results are simulated with systems. Diverse enhancements like stacked inverters, CMOS
the required output [3]. thyristors, and MOS capacitance-based configurations are
proposed to attain elevated frequencies and curtail Process,
The improved design of a ring oscillator using a stacked- Voltage, and Temperature (PVT) fluctuations. Furthermore,
inverter whose output has a high-frequency range with fewer methods for temperature compensation ensure steady
variations in PVT ie process, voltage, and temperature. The operation across varying temperature ranges, thereby reducing
paper gives an overview of different oscillator architectures frequency variations. Lastly, ring oscillators emerge as pivotal
and describes the design, and results of the proposed components in wireless communication systems, furnishing
architecture with future scope. The main focus is on the specific frequency ranges, minimal power consumption,
stacked inverter which improves delay and also reduces and favorable phase noise characteristics tailored for GHz
leakage current whereas the voltage-controlled ring oscillator frequency operation.
uses a voltage-controlled switch to accomplish high frequency
and low power consumption. A buffer circuit is used to obtain
square wave and rail-to-rail outputswing. The design works
at 1MHz frequency with a supply voltage of 1.8V [4].
 IV. S PECIFICATIONS and power consumption of the transistor also rise. The value
at which the output voltage of a CMOS inverter changes from
Parameter Symbol Min Typ Max Unit high to low (or low to high) in response to changes in the
Frequency F - 10 - MHz
Duty cycle DS - 50% - %
input voltage is known as the switching point. The threshold
Supply current I - - ¡100 µA voltages and relative sizes of the NMOS and PMOS transistors
Power supply VDD 1.72 1.8 1.98 V affect the switching point of a CMOS inverter. The switching
Leakage current Ileak - 0 ¡5 nA threshold was managed and tuned for the desired performance
Temperature range Temp -40C 27C 125C C
TABLE I parameters required for the project by designing the NMOS
S PECIFICATIONS and PMOS transistors accordingly. Each inverter’s output is
connected to the input one after the other, this produces a
feedback loop that keeps the oscillation going.
V. DIFFERENT ARCHITECTURES B. Current Starved Ring Oscillator
A. Inverter based 3-Stage Ring Oscillator

Fig. 3. Current starved ring oscillator

It is a type of Ring Oscillator made up of an odd number

Fig. 1. 3-STAGE RING OSCILLATOR of inverter stages connected in a ring configuration. The
formation of inverter stages is by CMOS transistors. The
It is a specific configuration of a ring oscillator consisting transistors in each stage are restricted in the amount of current
of 3 CMOS inverter stages with feedback in the loop. A which influences the speed of the transistors and the frequency
ring oscillator uses an odd number of inverters to achieve of the oscillator. The limited current ensures a controlled and
higher gain than a single inverting amplifier. Each inverter predictable delay through each stage to get a stable oscillation
adds a delay, so increasing the number of inverters lowers frequency. This design helps in reducing power consumption
the oscillator frequency. Thus, the desired frequency depends and has a good phase noise performance. For this architecture,
on the number of inverter stages. The reciprocal of the total we used the same inverter that we used for the 3-stage ring
propagation delay through three stages gives the frequency of oscillator.
the oscillator.
VI. F INAL A RCHITECTURE
VCOs are utilized in feedback systems to produce oscilla-
tory signals with frequencies that can be adjusted by an input
control voltage. This feature is crucial for tuning frequencies
in diverse signal processing and communication applications.
A. Functional Block Diagram

Fig. 2. CMOS INVERTER

Fig. 4. Block diagram
Sizing is a very important step that helps in achieving the
desired duty cycle required i.e., ideally 50%. The transconduc- 1) Replica-Circuit: It accepts an input voltage vcoin. This
tance (gm) of a MOSFET is determined by its width-to-length circuit is primarily utilized to generate a control voltage
ratio (W/L ratio), which in turn controls its driving strength (denoted as vgsf). It serves to provide a stable control voltage
and speed. Higher transconductance and drive strength are the for the oscillators in the subsequent stage.
outcomes of larger W/L ratios, but the parasitic capacitance
 2) 3-Stage Ring Oscillator: The 3-Stage Ring Oscillator
comprises three Differential Inverter stages. Below is a de-
tailed explanation of the components and their functionality:
• Differential Inverters: These inverters function differ-
entially, meaning they produce complementary outputs
(denoted vo and von). Differential inverters are often
employed for their superior noise immunity and enhanced
performance at high frequencies.
• Stage Connections: The output of one inverter (both vo
and von) is connected to the input of the next inverter
stage. The output of the first inverter connects to the
Fig. 5. Differential inverter
second inverter, the second connects to the third, and the
third loops back to the first, forming a closed loop.
• Control Voltage Inputs: Each inverter stage also receives transistors M8, M9, and M10 shown in Fig.6, generates a
the control voltages vgsf and vcoin generated by the reference voltage at node A. Local feedback, facilitated by an
replica circuit, which can adjust the oscillation frequency. operational amplifier (opamp), is employed to set the voltage
The ring oscillator generates oscillations as the signal at the gate of the source follower (Vgsf). The feedback
traverses through the inverters, with the frequency of these signal is derived from the drain of transistor M10, ensuring
oscillations being determined by the delay introduced by each the opamp input remains unaffected by Vdd. This feedback
inverter stage and the control voltages. mechanism significantly enhances the output impedance of
the n-channel source follower.
3) Buffer Circuit: The Buffer Circuit processes the oscilla-
tions generated by the ring oscillator and conditions them for
the final output. The primary functions of the buffer circuit
are:
• Signal Conditioning: It ensures that the oscillations have
the correct amplitude and waveform. In this context, it
converts the oscillations into a square wave.
• Driving Capability: It provides adequate drive strength
to transmit the signal to the next stage or to the output
without being influenced by the load.
• Isolation: It isolates the oscillator from the output,
preventing any load variations from impacting the Fig. 6. Replica circuit
oscillator’s performance.
The output impedance of the circuit with feedback (Ro) is
4) Output: The final output is a 10 MHz square wave determined by Ro = ro*(1+gm*R*Av), where ro denotes the
oscillation, as specified. This indicates that the buffer circuit output impedance of the n-channel transistor, gm represents
processes the oscillations from the ring oscillator (sinusoidal the transconductance, and Av indicates the opamp gain. As a
waves) to generate a stable square wave output at the targeted result, the impedance observed at the drain of the n-channel
frequency. source follower with feedback is substantially higher than
without feedback, diminishing the impact of power supply
variations on node A voltage and reducing sensitivity to power
B. Methodology supply changes. As the feedback is taken from the drain of
In this subsection, we outline the methodology utilized to M10, node voltage at A will be the same as Vref i.e., the
develop and assess the Voltage-Controlled Ring Oscillator same voltage as at the non-inverting terminal of the opamp
(VCO) circuit, with a focus on minimizing sensitivity to which is connected to vcoin. Thus the voltage at node n1 is
power supply noise. Each VCO cell as shown in the block the same as vcoin which is set to 0.8V. This is because the
diagram comprises a differential inverter featuring p-channel voltage at node A drops to 1.6V. As the non- inverting input
inputs and n-channel loads, with the VCO-in signal applied to terminal of the opamp is connected to Vcoin, the voltage at
the n-channel loads and diode-connected transistors (shown node n1 equals Vcoin. The integration of diode- connected
in Fig.5). transistors with differential amplifiers featuring n- channel
inputs enables exceptional Power Supply Rejection Ratio
To maintain the voltage at node A independent of Vdd, (PSRR), particularly at higher frequencies. This methodology
an n-channel transistor configured as a source follower minimizes the influence of power supply variations on the
isolates Vdd from node A. A replica circuit, comprising VCO frequency, ensuring low sensitivity to power supply
fluctuations. It facilitates the design and realization of a VCO B. PVT Analysis
circuit with minimal sensitivity to power supply noise, thereby PVT Analysis was performed for the final design and
enhancing the stability and reliability of integrated circuits the following results are obtained for output voltage Vout1
across various applications. The effectiveness of this approach (Fig 9) and Vout2 (Fig 10). Fig.11 shows the frequency
is validated through simulations and measurements, ensuring plot for tt. Fig.12 shows the change of frequency w.r.t the
robust performance under diverse operating conditions. change in voltage and temperature. The provided PVT analysis
graphs illustrate the VCO’s performance under varying supply
voltage (1.62V to 1.98V), temperature (-40°C to 125°C), and
typical process conditions. The VCO maintains its oscillatory
behavior, although with some expected variations in frequency
due to the specified PVT conditions. This analysis confirms
the robustness of the VCO design, ensuring reliable operation
across a broad spectrum of environmental and operational
scenarios. There was a 2% change in frequency when Vdd
was varied from 1.62 V to 1.98 V (Table III).

Fig. 7. Final architecture

VII. RESULTS AND DISCUSSION

A. Frequency Analysis

Fig. 9. PVT Result for Vout1

Fig. 8. Output waveforms of Final architecture

Fig 8 shows the output waveforms of the performed final

architecture. The first two waveforms depicted are the differen-
Fig. 10. PVT Result for Vout2
tial outputs of the VCO, displaying a 180◦ phase shift. These
outputs are then processed by the buffer circuit, producing
square wave oscillations. Supply Voltage Frequency (MHz)
1.62 V 9.87
Frequency 10.07 1.8 V 10.07
Duty Cycle 51.1% 1.98 V 10.30
TABLE III
Phase Noise -46.3 dBc/Hz
F REQUENCY CHANGE W. R . T SUPPLY VOLTAGE VARIATION
TABLE II
O UTPUT RESULTS

The frequency of 10.07 MHZ, 51.1% duty cycle, and

phase noise of -46.3 dBc/Hz were obtained. These values are
mentioned in Table II.
 [7] R. Islam, A. N. K. Suprotik, S. M. Z. Uddin and M. T. Amin, ”Design and
analysis of 3 stage ring oscillator based on MOS capacitance for wireless
applications,” 2017 International Conference on Electrical, Computer and
Communication Engineering (ECCE), Cox’s Bazar, Bangladesh, 2017, pp.
723-727, doi: 10.1109/ECACE.2017.7912998.

Fig. 11. PVT result-Frequency plot For tt

Fig. 12. Frequency Response for Voltage and Temperature Variations

VIII. CONCLUSION AND FUTURE SCOPE

The study on voltage-controlled ring oscillators (VCOs)
has shown that stable oscillation frequencies can be achieved
with minimal sensitivity to power supply noise. The fre-
quency deviation is only 2% under varying power conditions,
outperforming traditional CMOS inverter-based and current-
starved designs. While these findings are significant, future
research should focus on exploring alternative noise immu-
nity techniques, optimizing the design for higher frequencies,
and testing scalability across different CMOS technologies.
Overall, this study advances VLSI design and enhances the
reliability of modern electronic devices.
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