MODULE 4

OPERATIONAL AMPLIFIER
(OP-AMP)
Operational Amplifier: OP - AMP is a solid state device capable of sensing and
amplifying dc and ac input signals.

The word “operational” is used because the amplifier can be used to perform a variety of
mathematical operations such as addition, subtraction, integration, differentiation etc.

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to
which feedback is added to control its overall response characteristic i.e. gain and bandwidth.
The op-amp exhibits the gain down to zero frequency.

Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since
these would reduce the amplification to zero at zero frequency. Large by pass capacitors may be
used but it is not possible to fabricate large capacitors on a IC chip. The capacitors fabricated are
usually less than 20 pf. Transistor, diodes and resistors are also fabricated on the same chip.

Differential amplifier is a basic building block

of an op-amp.

3
Types of Differential Amplifier:

The four differential amplifier configurations are following:

 Dual input, balanced output differential amplifier
OR Differential input, differential output differential amplifier
OR double ended input, double ended output differential amplifier
 Dual input, unbalanced output differential amplifier.
OR Differential input, single ended output differential amplifier
OR Double ended input, single ended output differential amplifier
 Single input, balanced output differential amplifier.
 Single input, unbalanced output differential amplifier.

4
Symbol of Operational Amplifier:

V+
V+ ↔ +VCC
V- ↔ -VEE or -Vcc
inverting input 
output
non-inverting input +

V
The Gain of OP-AMP is denoted by “A”.

A = (Output/Difference Between Two Input Signals)

= Vo /( V1 – V2 )

Where,
V1 = Voltage Applied at Non-Inverting input
V2 = Voltage Applied at Inverting input
Vo = Output Voltage

5
Block Diagram of OP-AMP:

Input stage: It consists of a dual input, balanced output differential amplifier. Its function is to amplify the
difference between the two input signals. It provides high differential gain, high input impedance and low
output impedance.

Intermediate stage: The overall gain requirement of an Op-Amp is very high. Since the input stage alone
cannot provide such a high gain. Intermediate stage is used to provide the required additional voltage gain.

It consists of another differential amplifier with dual input, and unbalanced ( single ended) output.

6
Block Diagram of OP-AMP:
Buffer and Level shifting stage: As the Op-Amp amplifies D.C signals also, the small D.C. quiescent voltage
level of previous stages may get amplified and get applied as the input to the next stage causing distortion
the final output.

Hence the level shifting stage is used to bring down the D.C. level to ground potential, when no signal is
applied at the input terminals. Buffer is usually an emitter follower used for impedance matching.

Output stage: It consists of a push-pull complementary amplifier which provides large A.C. output voltage
swing and high current sourcing and sinking along with low output impedance.

7
OP-AMP ICs:

OFFSET
(+) NULL
1 8 N.C. OUTPUT A 1 8 V+

-IN 2 7 V+ -IN A 2  7 OUTPUT B


+ -IN B
+IN 3 + 6 OUTPUT +IN A 3  6
OFFSET +
V 4 5 NULL (-) V 4 5 +IN B

DIP-741 Dual op-amp 1458 device

Notch DIP: Dual inline package

4
3
2
1

8
 Data--Converter Circuits
Data

Because digital integrated

circuits are economical and

8
accurate, it is convenient to
process signals in digital
form, for example, to
perform algebraic
manipulations, to transmit
or store signals.

Figure 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit. The switch closes for a small part
(tseconds) of every clock period (T). (b) Input signal waveform. (c) Sampling signal (control signal for the switch). (d) Output signal (to be
fed to A/D converter).
 Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters
as Functional Blocks

9
Figure 9.37 The A/D and D/A converters as circuit blocks.
 D/A Converter Circuits

• Binary-weighted registers

10
b1b2 ...bN

VREF VREF VREF

iO  b1  b2  ...  N 1 bN
R 2R 2 R

vO  iO R f

Figure 9.39 An N-bit D/A converter using a binary-weighted resistive ladder network.
 • R-2R ladders

11
b1b2 ...bN

VREF
iO  D
R
Figure 9.40 The basic circuit configuration of a DAC utilizing an R-2R ladder network.
 A/D Converter Circuits

• Feedback-type converter

12
Figure 9.43 A simple feedback-type A/D converter.
SMALL-SIGNAL HALF-WAVE RECTIFIERS:
i. Positive small-signal half-wave rectifier circuit:

A positive small-signal half-wave rectifier is shown in the figure.

 The resultant circuit can rectify signals with peak values down to a few
millivolts.
 D1 is used in the feedback path and the analysis can be done for input Vin >0V
and Vin < 0 V.
ACTIVE FIRST-ORDER LOW PASS FILTER
 Inverting Amp +  Identical frequency
Feedback Capacitor response with Passive
filter

Chap 0
 Very Low Output
impedance
 Negligible Loading
Effect

17
Active First-
First-order High Pass Filter
n Inverting Amp + Input n Identical frequency response
Capacitor with Passive filter
Very Low Output impedance

Chap 0
n

u Negligible Loading
Effect

18
ACTIVE HIGH-ORDER FILTERS
 Low Pass Filters

19
 High Pass Filters

Cha
p0
BANDPASS AND BAND-REJECT FILTERS
 Butterworth Filters
 Maximally Flat Magnitude response in pass band

20
 High Attenuation Rate
 Chebyshev Filters
 Maximum Attenuation Rate
 Ripple in pass band
 Bessel Filters
 Maximally flat time delay in response to step input
 Attenuation Rate is very gradual

Cha
p0
FILTER DESIGN TABLE
 C when 0 = R0 = 1

21
Cha
p0
FILTER DESIGN EXAMPLE
 Low pass five-pole Butterworth filter with a corner
frequency of 200Hz and input resistance of 50K
 Economic Solution = 3rd order + 2nd order
 Desired R and C ?

22
 C1A = (0 R0 C0 ) / ( R)
= 1x1x1.753 / 2x200x50K = 27.9 nF
 C2A = 21.6 nF, C3A = 6.7 nF, C1B = 51.5 nF, C2B = 4.9 nF

Cha
p0
 -

555

40
WHAT IS A 555 TIMER?

 The 555 timer is an 8-pin IC that is

capable of producing accurate time
delays and/or oscillators.
 In the time delay mode, the delay is
controlled by one external resistor and
capacitor.
 In the oscillator mode, the frequency of
oscillation and duty cycle are both
controlled with two external resistors
and one capacitor.
CAPACITOR

A capacitor is an electrical component that can

temporarily store a charge (voltage).
 The rate that the capacitor charges/discharges
is a function of the capacitor’s value and its
resistance.
 Tounderstand how the capacitor is used in the
555 Timer oscillator circuit, you must
understand the basic charge and discharge
cycles of the capacitor.
CAPACITOR CHARGE CYCLE

 Capacitor is initially
discharged.
 Switch is moved to position A.
 Capacitor will charge to +12 v.
 Capacitor will charge through
the 2 K resistor.
Equation for Charging Capacitor

VC  VFinal  VInitial   1 - e -t/RC

 V Initial
Where :
VC  The voltage across the capacitor
VFinal  The voltage across the capacitor that is fully charged
VInitial  Any initial voltage across the capacitor as it begins to charge
CAPACITOR DISCHARGE CYCLE

 Capacitor is initially charged.

 Switch is moved to position B.
 Capacitor will discharge to +0
v.
 Capacitor will discharge
through the 3 K resistor.
Equation for Discharging Capacitor

VC  VInitial  VFinal   e -t/RC 

Where :
VC  The voltage across the capacitor
VFinal  The voltage across the capacitor that is fully discharged
VInitial  Any initial voltage across the capacitor as it begins to discharge
CAPACITOR CHARGE & DISCHARGE

12 v
5V
VC
20 mSec

Time 0v

Switch has been at position B Switch is moved to position Switch is moved back to
for a long period of time. The A. The capacitor charges position B. The capacitor
capacitor is completely through the 2K resistor. discharges through the
discharged. 3K resistors.
BLOCK DIAGRAM FOR A 555 TIMER

Vcc (8) Discharge (7)

T1
COMP1 Flip-Flop
Control Voltage (5) -
Threshold Voltage (6) + RESET Q

+ COMP2
SET Q Output (3)
-
Trigger Voltage (2)

Ground (1) Reset (4)

SCHEMATIC OF A 555 TIMER IN OSCILLATOR MODE

5 Volts

RA
3.333 V
N/C
Discharge

RB Output
1.666 V

Threshold /
Trigger

C
Ground N/C
PIN DESCRIPTION OF NE555 TIMER IC
Pin1 : ground
Pin 2: trigger
Pin 3: output
Pin 4: reset: the timer can be reset by applying a negative pulse
to this pin. When not used, it is connected to +VCC.
Pin 5: Control voltage: This is used to change the threshold
voltage as well as trigger voltage. When not used, the control
pin should be bypassed to ground with 0.01uf capacitor to
prevent any noise problem.
Pin 6: threshold this is the non inverting terminal of the
comparator 1.
Pin 7: discharge: this pin is connected internally to the collector
of the transistor. When the output is high, transistor is OFF and
acts as a open circuit. When the output is low. the transistor will
be in saturation and acts as short circuit.
Pin 8: +VCC supply is connected w.r.t ground.
PIN DESCRIPTION OF NE555 TIMER IC
Voltages at VTH and VTL are 2/3VCC and 1/3VCC
respectively.
Comparators produce 0 and 1 for V- > V+ and V- < V+
respectively.

SR latch works on the following principle

S R Qn+1
0 0 Qn
01 0
1 0 1
1 1 NA

Output is available at 3
External triggers is generally applied at 2 no. pin of IC
555 Oscillator
Detail Analysis
DETAIL ANALYSIS OF A 555 OSCILLATOR

5v
3.333
v
1.666
Vc v

0v

HIGH
RESET LOW

HIGH
SET LOW

Q HIGH
LOW

ON
T1 OFF

HIGH
Q LOW
DETAIL ANALYSIS OF A 555 OSCILLATOR (CONTI…)

5v
3.333
v
1.666
Vc v

0v

HIGH
RESET LOW

HIGH
SET LOW

Q HIGH
LOW

ON
T1 OFF

HIGH
Q LOW
DETAIL ANALYSIS OF A 555 OSCILLATOR (CONTI…)

5v
3.333
v
1.666
Vc v

0v

HIGH
RESET LOW

HIGH
SET LOW

Q HIGH
LOW

ON
T1 OFF

HIGH
Q LOW
DETAIL ANALYSIS OF A 555 OSCILLATOR (CONTI…)

5v OUTPUT IS HIGH WHILE THE CAPACITOR IS

3.333 CHARGING THROUGH RA + RB.
v
1.666
Vc v

0v

HIGH
RESET LOW

HIGH
SET LOW

Q HIGH
LOW

ON
T1 OFF

OUTPUT IS LOW WHILE THE CAPACITOR

HIGH IS DISCHARGING THROUGH RB.
Q LOW
DETAIL ANALYSIS OF A 555 OSCILLATOR (CONTI…)

tHIGH : Calculations for the Oscillator’s HIGH Time

VC  VFinal  VInitial   1 - e RC   VInitial

  1 - e RC 

t t
 
1

   
2

 RC 
t

 
t
 
2
V  V  1
V   1 - e   31 VCC  21  e RC

 
3 CC CC 3 CC

ln 2   ln e RC 

t


VCC   VCC   1 - e RC   31 VCC


t 1

2 2
 
 
3 3

t
3 VCC  3 VCC
2 1
 
RC 
t
 0.693  
  1 - e  RC
2
V  
t HIGH  0.693 R C
3 CC

 1 - e RC 

t


t HIGH  0.693R A  RB C
1

 
2
DETAIL ANALYSIS OF A 555 OSCILLATOR (CONTI…)

tLOW: Calculations for the Oscillator’s LOW Time

VC  VInitial  VFinal    e RC 
   e RC 

t t
 
1

   
2

   RC 
ln 2   ln e RC 

t t
 
1
V  2
V  0   e  1

   
3 CC 3 CC

VCC   VCC    e RC 

t
 t
1 2
 0.693  
 
3 3
RC
1
VCC  RCt  t LOW  0.693 R
3
 e 
3 VCC
2
  t LOW  0.693 RBC
  e RC 

t

1

 
2
555 TIMER DESIGN EQUATIONS

tHIGH : Calculations for the Oscillator’s HIGH Time

THE OUTPUT IS HIGH WHILE THE CAPACITOR
IS CHARGING THROUGH RA + RB.

5v

3.333 v

Vc 1.666 v

0v

 tHIG 
H

HIGH

Output
LOW

t HIGH  0.693R A  RB C
555 TIMER DESIGN EQUATIONS (CONTI….)

tLOW : Calculations for the Oscillator’s LOW Time

THE OUTPUT IS LOW WHILE THE CAPACITOR
IS DISCHARGING THROUGH RB.

5v

3.333 v

Vc 1.666 v

0v

 tLO 
W

HIGH

Output
LOW

t LOW  0.693R BC
555 TIMER – PERIOD / FREQUENCY / DC

Period: Duty Cycle:

t HIGH  0.693 R A  RB  C t HIGH
DC   100%
T
t LOW  0.693 RBC
0.693 R A  RB  C
T  t HIGH  t LOW DC   100%
0.693 R A  2RB  C
T  0.693 R A  RB  C  0.693 RBC
DC 
R  RB 
 100%
T  0.693 R A  2RB  C
A

R A
 2RB 

Frequency:
1
F
T
1
F
0.693 R A  2RB  C
EXAMPLE: 555 OSCILLATOR
For the 555 Timer oscillator shown below, calculate the circuit’s, period
(T), frequency (F), and duty cycle (DC).
EXAMPLE: 555 OSCILLATOR

Solution:

R A  390  RB  180  C  6.8 F

Period:
T  0.693 R A  2RB  C
T  0.693 390  2  180   6.8 F
T  3.534 mSec

Frequency: Duty Cycle:

F
1
DC 
R  R   100%
A B

T R  2R 
A B

F
1
DC 
390   180    100%
3.534 mSec 390   2  180  
F  282.941 Hz DC  76%
EXAMPLE: 555 OSCILLATOR
For the 555 Timer oscillator shown below, calculate the value for R A &
RB so that the oscillator has a frequency of 2.5 KHz @ 60% duty cycle.
EXAMPLE: 555 OSCILLATOR

Solution:

Frequency: Duty Cycle:

T
1

1
 400 Sec DC 
R A
 RB 
 100%  60%
f 2.5 kHz R A
 2RB 
T  0.693 R A  2RB  C  400 Sec R  RB 
A
 0 .6
T  0.693 R A  2RB  0.47 f  400 Sec R A
 2RB 
400 Sec R A  RB  0.6R A  2RB 
R A  2 RB   1228.09 
0.693  0.47 f R A  R B  0 .6  R A  1 .2  R B
R A  2 RB  1228.09 0 .4  R A  0 .2  R B
R A  0 .5  R B

Two Equations & Two Unknowns!

EXAMPLE: 555 OSCILLATOR
Solution:

Frequency: Duty Cycle:

R A  2 RB  1228.09 R A  0 .5  R B
Substitute and Solve for RB

R A  2 RB  1228.09 
0.5  RB  2 RB  1228.09 
2.5 RB  1228.09 
RB  491.23 
Substitute and Solve for RA

R A  2 RB  1228.09 
R A  2 491.23    1228.09 
R A  982.472   1228.09 
R A  245.618 
ASTABLE DUTY CYCLE

Duty Cycle >50% Duty Cycle <50%

Normally the 555 timer is unable to produce a To allow a Duty Cycle of 50% or less, a Diode
duty cycle of 50% or less. This is due to the fact D1 is placed in parallel with Rb such that
that the first half of the cycle both Ra and Rb during the charging cycle (T1) Rb is bypassed.
determine the charging interval (T1); where Rb This allows Ra and Rb to act independently,
alone determines the discharge interval (T2). allowing a duty cycle of nearly 0% to nearly
100%.
MONO-STABLE OPERATION

time period, T = 1.1 × R × C

MONO-STABLE OPERATION
time period, T = 1.1 × R1 × C1

The timing period is triggered (started) when the trigger input (555 pin 2) is less than 1/3 Vs, this
makes the output high (+Vs) and the capacitor C1 starts to charge through resistor R1. Once the
time period has started further trigger pulses are ignored. The threshold input (555 pin 6)
monitors the voltage across C1 and when this reaches 2/3 Vs the time period is over and
the output becomes low. At the same time discharge (555 pin 7) is connected to 0V, discharging
the capacitor ready for the next trigger.

The reset input (555 pin 4) overrides all other inputs and the timing may be cancelled at any
time by connecting reset to 0V, this instantly makes the output low and discharges the capacitor.
If the reset function is not required the reset pin should be connected to +Vs.
BISTABLE OPERATION

The circuit is called a bistable because it is stable in two states: output high and
output low. It is also known as a 'flip-flop'.It has two inputs:

Trigger (555 pin 2) makes the output high Trigger is 'active low', it functions when
< 1/3 Vs.
Reset (555 pin 4) makes the output low Reset is 'active low', it resets when < 0.7V.
INVERTING BUFFER (SCHMITT TRIGGER) OR NOT GATE

The buffer circuit's input has a very high impedance (about 1M) so it requires only a few µA, but
the output can sink or source up to 200mA. This enables a high impedance signal source (such
as an LDR) to switch a low impedance output transducer (such as a lamp).It is an inverting
buffer or Not Gate because the output logic state (low/high) is the inverse of the input state:
Input low (< 1/3 Vs) makes output high, +Vs
Input high (> 2/3 Vs) makes output low, 0V
When the input voltage is between 1/3 and 2/3 Vs the output remains in its present state. This
intermediate input region is a deadspace where there is no response, a property
called hysteresis. This type of circuit is called a Schmitt trigger. If high sensitivity is required the
hysteresis is a problem, but in many circuits it is a helpful property. It gives the input a high
immunity to noise because once the circuit output has switched high or low the input must
change back by at least 1/3 Vs to make the output switch back.