Give the classification of logic families. . Ua [SPPU : May-10,12, Dec.-08, Marks 4] a : A digital logic family is a fe logic levels and s ae upply volta Bic family, digit ic fa Fig. O11 om disital topic fa group of compatible devices with the ies. According to components used in mnilies are classified as shown in the Classitiction of logic amon Bipolar Unipolar Saturated Unsaturated Schothy TTL Ema + RTL : Registor Transistor Logic * DIL : Diode Tr ) to (S-5) Fig. Q.1.1 Classification of logic families 1.2 : Digital IC Characteristics Q.2 State and explain any four characteristics of digital ICs, S&F [SPU : Dec.-08,15, May-17, Marks 6] Ans. : Propagation Delay : The propagation delay of a gate is basically the time interval between the application of an input pulse and the occurrence of the resulting output pulse. The propagation delay. is a very (1-4)Digital Logle Famy, sation irganle ts because it limits the speeq Design & Computer 0 ic of logic oH The shorter t he propagation delay, the higher 48 aracteristis important characteris ; ch they can operate, The sor , Serer amiareleul and vice-versa. ; Fe aie: speed ipation ; The amount of powe that it draws from the : Power Diner average supply current, Icc, tha hy determined by the avera yen a It is the product of Ice and Voc : e Parameter - High-Level Input Voltage : is level will : reqed fora logical {at an input. Any voltage below this level will ny be accepted as a HIGH by the logic circuit. : Vit (max) Low-Level Input Voltage : It is the See required for a logic 0 at an input. Any voltage above this le not be accepted as a LOW by the logic circuit. )* High-Level Output Voltage : a logic circuit output in the logical 1 It is the minimum voltage state under defined load conditions. Nor (max) Low-Level Output Voltage : It is the maximum voltage level at a logic circuit output in the logical 0 state under defined load conditions, Iin- High-Level Input Current : mput when a specified high-level vo! Ij,- Low-Level Input Current: It is the Current that flows into an input when a specified low-level voltage is applied to that input, Jon High-Level Output Current ; It is the current that flows from an output in the logical 1 state under specified load conditions, Le It is the current that flows into an tage is applied to that input, in the two logic statesat es le Vy levgy "I nog leve] not age dad ge ad Logic Design « Io.~ Low-Leve 1 Out output in the logica, Put Noise Margin: py. Er specs circuit's ability to 4, ntanit the output voltage, “7, Vintmin) is kept at 8 few fj Jevel Vit (max) i8 Kept above V Van is the difference bet, and the minimum vo) \ voltage difference, Vi. is’ cailif"t) ,Tauired have low-state noise margin. 47 8 largest possible low output, \ required for a LOW input, en the Io lowest pos ‘OL(max) and the In short we can write as, Wu = Vou(enin) ~Virminy and 1 Fan-in and Ban-out The maximum number of inputs of seve that can be driven by the output of a logic gate i wont parameter called fan-out. In general, the fanou iq att! ¥Y * maximum number of inputs of the same IC family that the gate can maintaining its output levels within the specified limits." The fan-in of a digital logic gate refers to the number of inputs Speed Power Product (Figure of Merit) : © In general, for any digital IC, it is desirable to have shorter propagation delays (higher speed) and lower values of power dissipation. There is usually a trade-off between switching speed and power dissipation in the design of a logic circuit ie. speed is gained at the expense of increased power dissipation. Therefore, a common means for measuring and comparing the overall performance of an IC family is the Speed-Power Product (SPP). It is also called Figure of Merit. Operating Temperature Range : «It is the temperature range specified by the logic family within which devices are guaranted to work reliably. Power Supply Requirements : © Power supply Sr ad fom logic family to family. For eample, it is SV for TIL ad also “15 volts for CMOS family. Further more, power supply ae it is ds on logic family. For example, for 74 series TTL family 25V and for 54 series TTL family it is + 0.5 V. +0. Ke ==Logie Design & Computer Organication 1.3 : TTL : Standard TTL Characteristics, Operation of TTL NAND Gate Digital Logie Familie, i if. two-ing Q.3 With neat circuit diagram explain the operation © Put 1aF [SPPU : May-06,10, TTL NAND gates. Ans.: The Fig. Q.3.1 (a) shows the circuit diagram of 2-input NAND gate. Its input structure consists of multiple-emitter transistor and output structure consists of totem-pole output. Here, Q, is an NPN transistor having two emitters, one for each input to the gate. Although this circuit looks complex, we can simplify its analysis by using the diode equivalent of the multiple-emitter transistor Q,, as shown in Fig. Q.3.1 (b). Diodes D and D3 represent the two E-B junctions of Q, and Dg is the collector-base (C-B) junction. The input voltages A and B are either LOW (ideally grounded) or HIGH (ideally *5 volts), If either A or B or both are low, thie rorending diode conducys F'9+ 93-1 (b) Diode equivatent for a, and the base of Q, is the base volge Pled do acts as an emitter follow. Fig. Q.3.1 (a) Two input TTL NAND gat wn to apy roxims of Q, to almost zero, Th open , Qy goes into cut-off and the Q 12,13,16, Dec.-07, Marks 8) A Guide for Engineorina © Logic Design & Computer /ersed bias into forw: tum, Q4 gc summarizes Tabl Without diode D is low. To preve base-emitter dioc when the output Q.4 Draw thre: its operation. ‘Ans. : The Fig as that of two has three emit! input NAND g logic 0; other 2-input NANT. ‘AND gate. Table Q.4, 3-inpu!toric Desien & Computer Organisation Q; are reversed biased making them oft, 4 Malta Lonle Pamiy Dy to go into forward conduction. This fora, ° mT Q, goes into saturation, ee ASE di fom, Qs Producing ui Ic fummarizes all input and output conditions 'ow output, Ta lGH. ti 4 a Q A JB a Table Q.3.1 Truth table for 2-input NAND D, Without diode D; in the circuit, Qs will conduct slightly wre is tow. To prevent this, the diode is inserted; its voltage drop nego Bey hase-emitter diode of Qs reverse-biased. In this way, only Gv when the output is low. » only Qa conducts ft Q4 Draw three input standard TTL NAND gate circuit and explai 4 ain its operation. ES [SPPU : Dec.-08,10, Marks 8) ‘Ans, : The Fig. Q.4.1 shows the three input TTL NAND gate, It is same as that of two input TTL NAND gate except that its Qj (NPN) ensiad pe has three emitters instead of two. Rest of the circuit is same. For three input NAND gate if all the inputs are logic 1 then and then only output is logic 0; otherwise output is logic 1. The operation is similar to the 2-input NAND gate. The Table Q.4.1 shows the truth table for 3-input NAND gate. A B C. x Dee 20 ee 0 1 2 Or 0 1 1 0 0 1 Oe 1 1 1 dee 0-20 1 1 0 1 1 t fewertel Be 1 | ves eet ai 0 | 22 Table Q.4.4 Ti 3 sci NAN table of E gate of Fig. Q.4.1 Three input TTL NAND gate 4 Guide far Engineering Students1 Organization Digital Log Logic Design & Compute ic F ‘amilies nw ith eee arks 4] Ans. ? ae Open Ouiput stage consists of pull-up Oy Ben collector Ierutitor (2s), diode realstor and | jpul-dena nce ulldown transistor (Qy) Pe oon Habe of ont External pull-up resistor is not Ext el External pull-up resistor required for proper operat | a ae peration of | jutput of two gates cannot be siuer | 0 © Output of " ee Put of two gates can be tobither ialng wited AND technique. Operating 5) iS : perating speed is high. Operating speed is low. Table Q.6.1 Comparison of totem-pole and open collector output 7 Draw and explain the circuit diagram of tri-state TTL NAND ate. a TGF SPPU : May-05, Dec.-05, 07, Marks 6] ‘Ans. : The tristate configuration i: : config is a third type of T configuration. It utilizes the high-speed operation of the eens arrangement while permitting outputs to be wired-ANDed (Genssed together). It is called tristate TTL because it allows three possible output stages : HIGH, LOW and high-impedance. Truth table ig. 0.7.1 Tristate TTL inverter a Guide for Engineering Studentsa Digital Logic Famities Logic Design & Computer Organization er. It has two 3 ; ate inverter. It > Fig. Q.7.1 shows the simplified circuit for tristat Is id E. inputs A and E. is an ENABLE input. When normal inverter. Because (either ON or OFF) A is the normal logic input whereas E ENABLE input is HIGH, the circuit works as an when E is HIGH, the state of the transistor Q) isd ove. depends on the logic input A, and the additional ere nice circuited as its cathode is at logic HIGH. When ENGR ecco. regardless of the state of logic input A, the base-emitter a mao forward biased and as a result it tums ON. This shu eo through R, away from Q) making it OFF. As Q> is 4 he Sena sufficient drive for Q, to conduct and hence Qy turns O eee. ENABLE input also forward-biases diode D>, which shunt coe away from the base of Q;, making it OFF. In this way, when E] E input is LOW, both transistors are OFF and output is at high impedance state. Q.8 Explain the following characteristics of TTL logic families : i) Power dissipation ii) Noise margin iii) Propagation delay iv) Fan out. R Explain standard TTL characteristics in detail. OS [SPPU ; Dec,-08,10,12, May-10,13, Marks 8) OR Define the following terms related ‘ypleal values for standard TTL family : 4) Power dissipation ii) Fan-in i) vie to logic families, Mention Vou i) Noise margin, CS [sppu ; May-12, Marks 8] Bass 75 Vin eee While the Sra STS Works reliably Variation of 4,5 Di > le the 5. F voltage 1 output 108 maximum of power For TT both ar Power averag Fan-o inputs Qs Ans. sour has cont togea sign &. Computer Organtcation 1-9 bi igtal L nd noise margin : Table Q.8 vortage levels #" yal ard 74 series. T levels for the stan output | maximum values shown in the Table Q.8.1 are for oF Worst © of power supplys temperature and loading condition sac oe Maximum Table Q.8.1 Voltage levels TTL, Low state noise margin, Vi, and high state noise margin, \ e s gin, Va poth are equal and 0.4 V- power dissipation and propagation delay : x dissipation of about 10 mW. For A standard TTL gate has an average powe! standard TTL ‘A standard TTL output can typically drive 10 Fan-out = e, standard TTL has fan-out 10. inputs. Therefor Standard CMOS Characteristics, £ CMOS NAND Gate xplain its working, ks 3; May-12, Marks 4] 1.4: CMOS : Operation 0 CMOS inverter gate. E 1a [SPPU : Dec.-07, Mar MOS inverter circu! that the P-chann d the N-channel device are Q9 Draw the structure of it. It consists of hows the basic c el device has its Ans. : Fig. Q9.1 s two MOSFETs in series in such a Way source connected to + Vpp (@ positive voltage) an‘ has its source connected to ground. The gates of connected together as the common input and the together as the common output. the two devices drains are connectedIu Di igleal 1 gle Families Q5 4 Output OFF_OFt 1 _OFF _ON 1 ON _OFF_ Table Q.10.1 Truth table of NAND gate ere, the gates of both P-channel MOS! their sources, since the sources are conn‘ ‘ON. Since the gate - to - source voltages of Qs a MOSFETs) are both 0 V, those MOSFETs are Se. a vent is therefore connected 10 *Vpp (HIGH) through Q, and Q a disconnected from ground. When A = 0 and B = +Vpp. Q, is ‘beca cd « Nan and Q4 is ON because Ves, = +Vj Dee a i igs, = *Vpp- MOSFETs Q) and se their gate-to-source voltages are 0 V Since Q, is ON the output is connected to + Vpp and it is disconnected n A = +Vpp and B = 0 V, the situation is similar (not ut is connected to + Vpp through Q) and it is und because Q, is OFF. Finally, when both inputs and Q> are both OFF and Q; th ON. Thus, the output is connected to the ground through it is disconnected from +Vpp- The Table Q.10.1 ation of 2-input CMOS NAND gate. diagram interfacing of TTL gate 's are negative with respect tc d to + Vpp. Thus, Q, and Q. eis off becaus and Q3 is OFF, from ground. Whe: shown); the outp disconnected from grol ‘ch (A=B=+¥pp > MOSFETs Qi are high and Qg are bot Q; and Q4 and summarizes the oper: Q.11 Explain with a neat driving CMOS gates and vice-versa. DS [SPPU = May-05,07,13, Dec,-05, Marks 6; Dec. 08,11, Marks 8) OR How will you connect the output of CMOS logic circuit as a0 input to TTL logic circuit 2 Explain your reason with suitable 1H [SPU : Dec.-16, Marks 6] t values for CMOS ate of any TIL input current diagram. ‘Ans, : TTL Driving CMOS : The input current es | d with the output current capabilities extremely low compare : series. Thus, TTL has em meeting the CMOS requirements. no problpiaiat Logie Famili ee F oric jth the CMOS inpy — cir vee wom 00 THE << Va ime emo Neat ee dese situations eT output Sos Gist be raised to am ‘acceptable level & for MOS. This can be done by A TL ennecting pull-up resistor tthe 5 _ Wea eer Ta es ahem the sa eral. The pullup ress J i Ta geet) cndput (Ot S a approximately 5 V in the HIGH state, Fig. aii TL driving cmos at teing external pull-up resistor stat suf thereby providing an adequate input voltage level ee circuit is me + When output es more difficult TTL Driving HIGH Voltage cmos =f operating with Vpp greater than $ Y, the situation becom The outputs of many TTL devices cannot be operated at more than 5 Vv. In In such cases some alternative arrangements are made. Two of them are AC discussed below : a 1, When the TTL ir output cannot be ION a c pulled up to Voo, one can use open collector buffer as an interface re totem- pole TTL output amd CMOS ating TTL sy 4. ew) (Open collector : om Fig. Q.1 e the Fig. 0.11.2 ones be put) = . ec! he interface el alad used as P+tOVWe Fam Os ;, los Htor Bis ult, are Duy | a 13 & Computer Or8 oe Desi = aaute it 1 high voltage output for CMOS. Fig, trait arrangement & Q.113 a a priving TTL : CMOS outputs can easily TTL input requirement in the pot : n the HIGH 0 satisfy the puts can supply more than enough cur rent requirements (Ij). Thus no driving TTL in the HIGH state. require CMOS output voltage (Vor) satisfies TTL input requirement cre (Vg.) However, the current requirements in the ement in the LOW The TTL input has a relatively high input current in a no 8 rent in the LOW ate (Lo. is not satisfied. : sale (146 mA) and CMOS output current at LOW even one input of the TTL. In such situa ations some sufficient to drive f interface circuit is needed between the CMOS and TTL devices, type of Q.11.4 the CMOS In Fig. 4050 B, non-inverting puffer is used as an jnterfacing circuit. It has t current ratin, ea 3 e = CMOS gate Buffer = 3 mA which of Tor (max) satisfies the TTL input current requirement. = ™ HIGH Voltage CMOS inputs. Driving TTL : Some. Ic Fig. Q.11.4 CMOS driving TTL manufacturers have in LOW state using buffer provided several 74LS TTL devices that can withstand input voltages as high as 15 V. These devices can be driven directly from CMOS outputs operating at Vpp = 15 V. However, most TTL inputs cannot handle more than TEN and so interface is ret 45V 45V. necessary if they are to be driven from 4 high-voltage CMOS. 8 In such _ situations = = Tr gete level CMOS gate CMOS buffer n using CMOS buffer voltage translators are used. Fig. 0.11.5 Level transiatio 7 Guide for Engineering Stde§ outputs le circuit List the Marks 6) CMOS families 1 Comparison between TTL and 3: | Table Q. END...ea fea y di | 2ces | I | Logie Design & Computer Organization line number system r equals to 10 has 10 characters from 0 number system r equals to 2 has 2 characters 0 and 1 and al we can say that, a number represented in radix r ers in its set and r can be any value, This is illust cha Table 2.1 2 shows the relationship between decimal, binary, octal an Binar, 0000 Table 2.2 Relation between decimal, binary, octal and hexadecimal numbers Q.1 Convert (1101.101), to decimal number and explain the process of conversion. Ans. By adding each digit of a binary number in a power of 2 we can find the decimal equivalent of the given. binary number. This is illustrated in Fig. Q.1.1. - Gacoosy ‘A Guide for Engineering Studentsee signed BINA pti and C28 Leh as com Ans = (13.625)40 Ste) MS! i cha proceet sty a2 Convert (5632471) 10 deci Pee bal of conversion: + number in ® power of ® : ‘ans. : © By adding each digit of an octel © n octal number paer van find the decimal equivalent of the give! aa itustrated in Fig- Q2.1- 2s paesses as aecmeee |? |? axe? | exe | 9x8! 28° = An: Ne peat ones 3x8le 28° + eine ace Ste Fig. 0.2.1 Ste 3 Convert (3FD.84)1¢ into decimal number and explain the process of conversion. ‘Aus: By adding each digit of a hexadecimal number in a 7 : : power of || we can find decimal equivalent of the given hexadecimal number. ¢ s peaeetel See 16"! 2 wPsTF fo] 16" fealewtael Ne 168s Fete! Q7 . +Dx1e9 4 a exp 316715 164449 460 8x 16+ 4x 19-2 K + ad ns Q4 Wha 8x16 "4 = it is 4x 16% the radix = (1021.515625),. Ste Ang pe MT Systems 2 Of decimal, binary, octal and Ste,¥ \Goaes Logle Design & Computer Or i as Convert 101011010111 4, : conversion process. Stal equiva, : Ans. mma exp) . step 1: * Make group of 3-bits star, 43.625)10 MSB for fractional part, by adding Og 1 = "°™ LSB fy na the end, if sec” teeer step 1. —|0 out O41]. aces step 2. 2 5 | 5 g we Adding 0 to make a group of 3-bits, > js is TOU of 3 Step 2+ » Write equivalent octal number for eact (10101101.0111), = (255,34), ‘Ach Broup of 3-bit 6 Convert (125.62) to binary and explain the convers, ore ersion process, 810 Step 1: Write equivalent 3-bit binary number for each octal ¢ ach octal digit Step 2: Remove any leading or trailing zeros f Z a Octal (Base 8) [*Jo +0 l6 Step 2. [ : Leading zeros Trailing zero (125.62)g = (1010101.11001). Q7 Convert 1101101110 - 1001101 to hexadecimal equivalent and explain the conversion process. Step 1. Ans, : I Step 1: Make group of 4-bits starting from LSB for integer part and MSB for fractional part, by adding 0s at the end, if required. Step 2: Write equivalent hexadecimal number for each group of 4-bits. (1101101110.1001101), = (36E.9A)16opie Desten & Computer Orga ae a.it Convert (L101. 111011), = ¢ ‘ihn a Ans. = 101011 11101 0010 1011 1110 1100 BeBe. « (101011.111011). versions : Q.12 Do the follow D) (27.125)10 = ()2 Hi) BA2F)i6 = (2) 19 iti) C1194. ca [sppy he ‘ m Ans i) 2) 2741 2] 13 41 2 6 |0 [ Buln 0.5*2=1.0 2,141 ++ (27.125)49 = (1101.00), 0 ii) (3A.2F)j_ = 3 16'+10x 169+ 2x 16-1 + 15x 16°? = 48 + 10 + 0.125 + 0.05859375 = (58.18359375) 19 iii) (1101.0011)) = 1x 23 +1x 2? +0xX22 +1x23 41x24 = 8+4+1 + 0.125 + 0.0625 = (13.1875) 10 +0x 241% 29+0x 2 Q.13 Convert the following binary numbers to octal then to decimal. Show the steps of conversions. i) 11011100.101010 ii) 01010011.010101 iii) so110011 t= [SPPU: Dec.-17, Marks 6)6) Computer Organization (lon) Ht (SDB-FA); (0101 1101 104 15 Convert the following numbers as indicateg 1) (62.1)5 = 2)16= (2)2» W (BCO4)16 = 19 (23 hy ALroy, a =e i) (32. E)ig, (110010.111) ii) (48228). = (oitirogge ar” Hoo 199), Ans. iii) 214)5 46 Convert the following decimal numbers into thei QUidecimal numbers and octal numbers.” “HT equivaten nese 2) 1507 3) 23.56 4) 1.025 5) 100.5 SP SPPU : May-13, Marks 10 1 Ans. + 1) GA8)s6 (1650)x 2) (SE3)i« (2743)y, 3) (17.8F2)16, 27.436), 4) (1.066)16, (1.0146)s, 5) (64.8)16, (144.4)5 : Q.17 Convert the following hexadecimal numbers into their equivalent octal numbers and binary numbers. 1) ATZE 2) BD6.7 3)0.AFS4 4) DF 5) FF EG [ SPPU: May-13, Marks 10 ] Ans. : 1)(123456)s, (1010011100101110),, 2) (5726.34)s, (101111010110.0111)2, 3) (0.53652)s, (0.1010111101010100),, 4) (337)s, (11011111), 5) (3FF)s, (11111111)2] Q.18 Convert the following numbers, show all steps : i) (2598.675)9 = ( )16 ii) (110101.101010), = ( )g Uae [SPPU : Dec.-15, Marks 6 ] iii) (A72E)jg =( Dg Ans. : i) (2598.675)39 = (A26. ACC)16 ii) (110101.101010), = (65.52) iii) (A72E)4¢ = (1010011100101110)) = (123456)g]Computer Organization 2-19) tet Binary Revresene, — ponte Des = cn en Signed ang present decimal number "13" in ang nplement a.23 Represeh ’ gumber representation using eign; n°? ™*thods of vegative bina 8 cight bits, : umber. Ans. + jement aTaTiToro ~131n 1's complemerst representation GL AL] - 13's complement representation 2.3 : Binary Arithmeti 24 Explain the binary addition operation. Ams. > = 1, Add bits column-wise starting from LSB th carry if ar sults When ny Put the sum at the bottom of the same column, 3, Put the carry, if any, on the top of next column. Q.25 Add (28);9 and (15);9 by converting them into binary. when w : ae ‘Ans. : Using decimal to binary conversion technique we have (28)9 = (011100), and (15)j9 = (01111), aal4 Carry pe 0 0 1 1 4 0. Binary equivalent of (28)4o Sign Extension + G70 1171/1. Binary equivalent of (15)49 Sign—> F401 1.0 1.1 Result: Binary equivalent of (43),9 “°) 9 and Q.26 State the procedure to perform binary subtraction using 1's complement method. Ans. ; The operation A - B is performed using 1's complement method ss. as follows : 1 sc bie Take 1's complement of B. iretid 2. Result — A + 1's complement of B. 3. If carry is generated then the result is positive and in the true form. Add carry to the result to get the final result. a ee —_— g Student A Guide for Engineer lentSigned Binary Repy esign & COMP Arithmetic dnd ¢ method. Lorie m aF)ie = O16 Using 2's complement mett Marks 4 32 Do (7F)16 ae 1 a 5 (111112 and (SC)\¢ = (101 ass: OP | cany 11 A] Cig 0] 2s complement of (5C)y— OPO af] Rest = (aay fa Discard carry[5X] 0 q.33 Perform 2's complement arithmetics of : )M0-ADi0 HH D1o-AN10" Si) (- 7)19 + 1) 9 US [SPU : May-15, Marks 6] Ans.: (79 = 111)2 (119 = (01011), 0 7] Mo OREN Ffo]o]o] 1'scomplement ot? [+o] 1[ 010] 1's complement of 11 [foto] a] zs complement ot7 []o] 10] 1] 2's complement of 11 i) M10 -AD10 ]t[4]_| cary fot] t{ 1] 0 + [To] st] 0] 4] 2's complement of 11 4 [1 [4 [Oo] Resuttis in 2's complement form Mo-(1)40 1 1]_] cary Sign extension—>| 4| 1] 0| 0| 1] 2's complement of 7 | 4[ 0] 4] 2's complement of 11 7/0] 4] 1] 1] 0| Resultis in 2's complement form ii) (“Tyo + (1940 4] _] carry 0| 1| 2's complement of 7 t[ 4] (0 | 0| Result =4 14] [4 Sign extension-=| 1| 1] 0 +folifo 1 5 5 Discard carry [Xo] | - A Guide for Engineering Studentsles the ich ay er ve don : ¢ A code is said : enectve ©08 RIERA tir 4 Ig cotisleciekn 4 is he coy a sequential codes each succeed jal codes a — sequentis . than its preceding code ‘nwo and excess-3 are sequential, whereas the 2421 and oa axe ot sage What are error detecting and correcting codes ? ¢ To maintain the data integrity between transmitter and receiver han one bit are added in the data. These extra bit bit or more # n and sometimes correction of error in the data. allow the detectio «The data along with the extra bitPits forms the code, Codes which w only error detection ch allow error detection and correction are called error detecting are called error detecting codes and codes allo and correcting codes. 37 What is BCD code ? What are rules for BCD addition ? ‘Ans. : © BCD is an abbreviation for binary coded decimal «BCD is a numeric code in which each digit of a decimal number is represented by a separate group of 4-bits. The most common BCD code is 8-4-2-1 BCD. e It is called 8-4-2-1 BCD because the weights associated with 4 bits are 8-4-2-1 from left to right. This means that, bit-3 has weight 8, bit-2 has weight 4 bit-1 has weight 2 and bit-0 has weight 1. ¢ The Table Q.37.1 shows the 4-bit 8-4-2-1 BCD code used to represent a single decimal digit In multidigit coding, each decimal digit is individually coded with 8-4.2-1 BCD code, as shown in the : Fig. Q37.1. Total 8-bits are required jyeimai 778 8 to encode $89 in 8-4-2-1 BCD. e424Bcd 0/110) 1 1:00 0 Fig, 0.37.1 farm 4 Guide far Fuaineorino StudentsTz uation Represet! med Binary ary: Signed Bina unmet Letle Design & Computer Organtzation Rules addition * BCD for BCD addition rules are as follows 1. Add two BCD numbers using ordinary binary addition, 2. If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form. 9 or if a carry is generated from the 3. If the four-bit sum is greater than four-bit sum, the sum is invalid. d = To correct the invalid sum, add 6 (0110,) to the four-bit sum and ignore carry of this sum. = Add 1(0001), to the next higher-order BCD digit. Q.38 Represent the unsigned decimal number 965 and 672 in BCD and then show the steps necessary to find their sum. Ans, : Ad step 2: complement ¢ step 3: If complement ¢ result. Q.40 Perfor: 9's complem: Ans. : i) Step 1: Step 2: Aws wnat are wpe rays for BCD Pabiraction Wslag’s's complemesi aso what’ ae lement of a negative number Beeauiredeess OPP A yo numbers using BCD addition (Minu 2: Add two es 1 si Het of sbtaben Ce ean ted result is negative - omplement of the Test otherwise result is positive and dd result. e following subtractions of BCD numbers using qo Perform th i) 68-24 fi) 24-29 g's complement = Ans. gtep 1: 9's complement of 24 = 99 -24=75 step 2: Add 68 and 9's complement of 24 (68) BCD (75) 9's complement of (24)80 7 1 Invalid BCD numbers ‘Add 6 in each digit ‘Add end around carry Result Since there is a carry, result is positive and true * (scp -(24) scp =) sco ii) Step 1: 9's complement of 29 = 99 - 29 = 70 Step 2: Add 24 and 9's complement of 70 A Guide for Engineering StudentsLogie Design & Computer Organtzation 2-19 @ o cory Loh Tofots To ative. Since eary is zero the answer is ne@ f answer s 99 -94 = 6) BCD (5) BCD Step 3: Take 9's complement o! 9's complement of 9 (24) BCD - (29) BCD ved Examples g 9's complement. Unsol Q.41 Perform (46)30 -(22)10 in BCD us sass nt. 0.42 Perform (24)19 -(56)10 ia BCD using 9's compleme: BCD subtraction using 10's complement ? .43 What are the rulers for ‘Ans. : Steps for subtraction of BCD numbers using 10's complemen method Find the 10’s complement of a negative number. ‘Add two numbers using BCD addition (Minuend + 10s complement of subtrahend). Step 1: Step 2: p 3: If carry is not generated result is negative and find the 10's complement of the result, otherwise result is positive ani discard carry. : Q44 Perform (46) 19 - i ee (46) 19 ~ (22); in BCD using 10's complement. Step 1: ? Pp Find 10's complement of 22, 10's 2 complement of 22 = 9'5 complement of 22 + | % = (99-22) + 46 and 10s complement of 22 Ss — Step 2: 78 ise since ther ( a4s Pe Ans. * step 1 Step 2 Since Step Q.46 @ 2 Ans, isa carry the result is positive and tru BCL 2M Bep 45 Perform (24), ~ (56), in BCD using 10's complement Ans. ? step 1: Find 10's complement of 56. 10's complement of $6 = 9's comp! 1 ement> i ent ? = (99-56)+1=44 Plemen, Step 2: Add (24);o and 10's complement of 56. 1 carry 0.04 24eco a ei 00 10 10's complement of (56)gcp 105 TH Cony WO 1 1010100 (aco Since carry is 0 the answer is negative. ae 10 , Step 3: Take 10's complement of answer. 10's complement of 68 = 9's complement of 68 + 1 = (99 -68)+1 (24)19 — (56)19 = — 210 Q.46 Find 9's and 10's complement of the following decimal numbers : (i) 24,681,234 (ii) 63,325,600 Ans. ; i) 99999999 — 24681234 = 75318765 9's complement 75318765 + 1 = 75318766 10's complement ii) 99999999 — 63325600 = 36674399 9's complement 36674399 + 1 = 36674400 10's complement A Guide for Engineering Students 7 Gacones erQ.54 Write a short note on gray code. Ans. : *Gray code is a non-weighted code and is a special case of unit-distance code. Gray code In unit-distance code, bit pattems for two consecutive numbers differ in only one bit Position. These codes are also called cyclic codes. ¢The Table Q54.1 shows the bit Patterns assigned for gray code from decimal 0 to decimal 15, Signed Binary Representation ang ic PE poste? ass Pert a Excess-3 for & — 10 o Excess-3 for 5 > ijojo Complement of 8 in excess-3 a ign & © pei — To obtait between down the 3. Repeat Ss binary d a.56 Conv Ans. : Q.57 Stat Ans. : 1. binary nur 2. To ot betwee 3. Repea’ PrevioRepr Whmeti ea computer OFA sation suc a Fe bn Tene O84 fo oe o As thoriefer only in One bit position. ee ro Peers rrepert + The gray code is al Tice wat ome ee reicuidlcent Bits tora, alled reflected mirror mazes ‘of those for Oo through 3,9. Sim came 7 * for 830 throug] ; 0 milar ¥ for 8i0 through 15j9 are the mir oo itor image significant! Oyo through 710 9.58 State the rules for gray to binary code conve, ian 1iseine fOr B87 to binary code conversion i 1. The Most Significant Bit (MSB) of the binary numb y er is the same as Te Most Significant Bit (MSB) of the gray cod ay code number er. So write down MSB as it is. ain the nex net binary digit, perform an excl just written down and the next ae ea ly code bit. Write . To obt between the bit down the result. 2 3, Repeat step 2 until all gray code bits have been excl xclusive-ORed wit th binary digits. 56 Convert gray code 101011 into its binary equival jivalent. Ans. > oo lelelelelet 8) (101011) gray = (110040), Q. 57 State the rules for binary to gray code conversion. Aus. : ee 1. The MSB of the gray code is the same as the ' number. So write down MSB as it is. oN it vee the next gray digit, perform an exclusive-OR-operation ; een previous and current binary bit. Write down the result + Repeat step 2 until all binary bits have been exclusive ORed wil Previous ones. MSB of the fh theirSigned Binary Rep Leute Design & Computer Organicaton m 9-88 Encode the decimal number 46 Ans, to Gray code. # (4619 = (101110). Binary code: 1~@+0-@+1-O->1 Hee} ! Peyemi to.) 4 (46)19 = (111001) Gray into: ) Binary il) Exces, Q.59 Convert the decimal number 27 into fe ad ass, Marie ey iii) Gray iv) HEX, Ans, : 27) 9 (11011). 1B yex (27) * (0010 O111)8c0 =(0101 1010 excess -3 gee Lier aoa Oa Oy (4 Ot ti 0 (27),0= (10110) oray Unsolved Examples Q.60 Represent the decimal number 6 in gray code. Ans. : 0101 2.5 : IEEE Standard 754 Floating Point Number Representation Standards for representing floating point E> [sppu : May-13,14,16, Dec.-15] gers and very small fractions, a © to represent numbers and operate on them in such Position of the binary point is Variable and is automatically this case, the binary point is said to point numbers. To accommodate very large int computer must be abl€ss.3 56) ena senting floating poir veloped by the Institut = (IEEE), referred to us IEE » IEEE standard format E754 stand, 32 bit sign of number exponent in osgnifes * excess-127 sgriies representation Value represented = + 1.M Fig. 2.61.1 (a) Single-precision « The 32-bit standard representation shown in Fig. Q.61.1 (a) . ig 8) isc wt representation because it occupies a eee : ingle single-precisio apubits are divided into three fields as shown belo W word. The (Geld 1) Sign — 1- bit (Geld 2) Exponent — 8 - bits < 23 - bits (Geld 3) Mantissa «Instead of the signed exponel exponent field is E’ = E (scaling factor) + bias. @ In the 32-bit floating P' E’ = E (scaling factor) + 127. This repre called as the excess-127 format. alues of E’, namely, nt, E, the value actually stored in the int system (single precision), bias is 127. Henss sentation of exponent is also 0 and 255, are used to indicate the respectively in single The end vé floating point values of exact Zero and infinity, precision. «Thus range of E’ for normal values in single precision is 0 Changing each AND sign to an OR sign ang 3, Complementing any 0 or 1 appearing in the expression fe example? Dual of relation A + K=1lisa-A=0 A+AB=A+B a1 Prove that Ans. # = A+AB = A+ AB+ ae by Theorem : 4(a) = A+B-(A+A) by Postulate : 4(a) = A+B-1 + 5(a) =A+B Br) a2 Prove the following equations using Boolean algebra. i) XY+XYZ+ XYZ+XYZ=Y (X+Z) ii) ABCD + BCD+ BC D+BCD=B(D+C) fF [SPPU : Dec.-11, June-11, Marks 6] Ans. : i) xy+xyz+ xyZ+ Xyz = xy (1+z = y(x+ %Kz)= y (x+2) A+ AB 4 Guide for Engineer"t aie@3 Using Boolean algebra ) ABCD - BcD BCD~ BCD~B(D i) AB+AC+ aBC(aB+ @=1 ii) ABCD+ Apcp- aBp- Bn Ans. : i) Refer Q ii) ABCD- 3.2: Representation of Logic Functions Concepts *Each occurrence o} w * The able in cither a complemented or an logic Sncomplemented form in the Boolean function is called a literal ae *A product term is defined as either a literal or a product (also called f( Conjunction) of literals *A sum term is defined as either a literal or a st jum (also called disjunction) of literalsted or an ral. uso called io called dents { ' Product terms product of mums i5 an BFOUPS of sum terms ANDed togeth « rreach term in SOP form contains all the literals then the SOP form known as canonical SOP form rm is « Each individual term in the canonical SOP form is called minterm, « rf each term in POS form contains all the literals then the POS form is known as canonical POS form. «Each individual term in the canonical POS form is called maxterm +The POS and SOP functions derived from the same truth table are logically equivalent. «In terms of minterms and maxterms we can then write £(A, B, C) = imp +m, + my + my + mg +m, = M2 +Ms £(A,B, C) = Y.m(0,1, 3,4, 6 7) = ™M 5)Logle De rey es ae 0 0 0 y ABC =m Roenwweis ab0-n opts anc- = oo ees sign & Computer Organization T 200 ABC=m Ans. : AB, Step 2: AND product term with (missing literal F(A,B,C) = ODE Table 3.2 Minterms and maxterms for three variables Q.4 Convert the given expression in canonical SOP form. f(A, B, C) = AC + AB + BC Stop 1: Find the missing literal/s in each product term. C= AC + AB 2 Bc | ae Literal C is missing. oo tera 8 is missing, Original product terms AC - (B+B) + AB -(C+C)+ BE 4 | Missing literals a A Guide for Engineering Students + its complement), ind their complements as conv Ans: ? stop 1 1A Step 2! Step Exp: Sine:“ ms and reorder literals. pele — ine ten y yand the a Bete - AC? ACB+ABC+Ani xp (A,B: O ABC+ABCtABC+ABT4 An peorder* ving supiciont practice student should expand » AB ¢ oo”. sr in ie in sg STP Product term and ret repeated product terms swe 4 ’ 5 y 10.8.0) 2ABC+ABC+ABG+ABT+IABG .x ((a,8,0)=ABC+ABC+ABT+REC avert the given expression in canonical POS form, (A+B) B+O(A+O) ‘ Find the missing literal/s in each sum term (B+C) (A+C) (A+B) aia: Literal B is missing Literal Ais missing Literal C is missing step 2: OR sum term with (missing literal «its complement Original sum terms c A+c + 5) 1(A,B,C)= A+B + (CC) B+C + (AA) Missing literals and their complements Step 3: Expand the terms and reorder literals. Expand : Since A+BC = (A+B) (A+C) we have, eS) y@rcrA) (A+B+Q)A+B+O@+0*4 f(A, B,C) = (A+C+B)(A+C*B) 4 Guide for Engineering SteLeste Design 4 Computer Orgentcaton SAA Computer Organtzatt 1-7 Lette Minty, oF Reorder ; eet PABLO) = (A+5+0)(A+8+0) (A+B OA+Bs, pears No iMplemented form (A and C remain unchangeg in both noma ue ange: i s to AC, ). Thus the ont reduce’ © exes, Bo ec at ort io oly | lute (o) Fig. 0.9.4 « Fig. Q9-1 (b) shows an example of two vertically adjacent two can be combined to eliminate A variable since it ae \s. These uncomplemented and complemented forms. Thus the eee its ces to BC. «In a Kamaugh map the corresponding cells in the leftmost column and rightmost column are considered to be adjacent. Thus, the two Is in these columns with a common row can be combined to eliminate one variable. This is illustrated in Fig. Q.9.1 (c). Here variable B has appeared in both its complemented and uncomplemented forms and hence eliminated to give expression as AC Same pairing rules can be applied for 2 or 4 variable K-maps. In 4-variable K-maps, the corresponding cells in the top row and bottom row are considered to be adjacent. 2 How is it useful in simplification of | Q.10 What is quad in K-map Boolean expression ? Ans. : © Quad is a group of four adjacent ce cancels two variables in a K-map simplification. jis in a Kamaugh map. Ttt (@y=85 (oven (ov=80 Fig. Q.10.1 ey : 11 What is octet ? How is it useful in simplification of Boolean a. at is 2 expression ? Ans. : Octet is a group of eight adjacent cells in a Karaugh map. cancels three variables in a K-map simplifications. Fig: Q.11.1 shows several examples of octet. (Refer Fig. Q.11.1 on next page) Q.12 State the rules for simplifying logic function using K-map. Ans. : Rules for simplifying logic function using K-map are ; 1. Group should not include any cell containing a zero, 2. The number of cells in a Broup must be a power of 2, such as 1, 2, 4, 8 or 16, 3. Group may be horizo; tal, vertical but not diagonal, 4. Cell Containing 1 must be included in g at least one group, 5. Groups may overlap, 6 Each group should be ag Simplification, ce: Dates 'o get maximum st cell in a row cell in a column eh cor det by doBoolean map. It om next 5 (y-5 aan Fig. Q.11.1 Examples of combining octets of adjacent ones 8, A cell may be grouped more than once. The only condition is that every group must have at least one cell that does not belong to any other group. Otherwise, redundant terms will result. 9, We need not group all don't care cells, only those that actually contribute to a maximum simplification. 10, All above rules are stated considering the SOP simplification. In case of POS simplification all rules are same except 0) (zeto) takes place of 1 (one). Q.13 What do you mean by don't care conditions 2 Ans, : * In some logic circuits, certain input conditions never occur, oe ba Corresponding output never appears. In such cases the output ‘ndioted defined, it can be either HIGH or LOW. These output levels by °X’ or “a! in the truth tables and are called dou S0* don't care conditions or incompletely specified functions. Se eaea pak PO soe the following ©: lization ecm LOR Ming Puy ows p= dO 1, {4,155 nique : FTSPPU Og m ae cD Mara Z=ABD+ACD+BCD+ABD+ acy Fig. Q.16.1 | giz Using K-map convert the following standard POS ex : joto a minimum POS expression, a standard SOP errant an minimum SOP expression (a'+ B'+C+D) (A+B'+C+D) (A+B+C+D') ss (A'+B+C+D!) (AFB+C'+D). EF [SPPU :Decot5, Mars 6) : (A+B+C+D) (A +B+C+D\(A +B+C+Dy(A +B+T4) (A+B+C+D)(A +B+C+D)=nM(12, 4, 1, 3, 9, 2) = mM(1, 2, 3, 4, 9, 12) Minimum POS Expression using K-map (A+B+C) (6+C+D) (+c+D) * FIA.B.C,D)=(a+B8+0)(B+C+0)(8+C7") andStandard SOP Expression Cue oe irl AM (1, 2,3, 4, 9, 12) = 3m 0 . De e : « SRCD+ABCD+ABCD+A® can TABCD+ -ABCD+ABCL Minimum SOP Expression FIA D+BD+BC+AC @.18 Minimize the following function using K-map and implemen, using basic logic gates f(A,B,C,D) m(0,1,2,4,8,9,12,13) + 4(3,6,7), Q.20 Mir S@ [SPPU : May-14, Marks 6] Impleme Ans, : > Simplification tan = s / 2.19 Minimize the fottoy;,, 9" 2181 ing NAN, followin, 5 a using NAND gates only, & equation using K-map and feet ye 772 m042.35,7.,9,1 ) fA,E SS [spy ; Dec,-11, Marks 10)ooo Oreenienton poset on imple Implementation a simplll! lt) Fre ! ' Fig. Q.19.4 0.20 Minimize f(A, B, C, D)= > m (0, 2, 5, 6, 7,1 Implement using NAND gates. eee) + May-07, Marks 8) nent 0. Ans. > K-map simplification :Logle Design & Computer Organization Implementation : p and implement using Noy a 7,812) +4 (3, 91114) 7" ap [SPPU + Dec.-07, Marks 6) Q.21 Minimize function using se :£(A, B,C, D)= 7M (14, f (ABCD) = (A+ D) (A+B) (A+ C+D) Implementation using basic gates Implementation using only NOR gate MW B implementa’