EEC 116 Lecture #4:
CMOS Inverter AC
Characteristics
Rajeevan Amirtharajah
University of California, Davis
Jeff Parkhurst
Intel Corporation
Acknowledgments
• Slides due to Rajit Manohar from ECE 547
Advanced VLSI Design at Cornell University
Amirtharajah/Parkhurst, EEC 116 Fall 2011 2
Announcements
• Lab 2 this week, report due next week
• Quiz 1 on Monday!
Amirtharajah/Parkhurst, EEC 116 Fall 2011 3
Outline
• Review: CMOS Inverter Transfer Characteristics
• Finish Lecture 3 slides
• CMOS Inverters: Rabaey 5.4-5.5 (Kang &
Leblebici, 6.1-6.4, 6.7)
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CMOS Inverter VTC: Device Operation
P linear P cutoff
N cutoff N linear
P linear
N sat P sat
N sat
P sat
N linear
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Logic Circuit Delay
• For CMOS (or almost all logic circuit families), only
one fundamental equation necessary to determine
delay:
dV
I =C
dt
ΔV
• Consider the discretized version: I =C
Δt
ΔV
• Rewrite to solve for delay: Δt = C
I
• Only three ways to make faster logic: C, ΔV, I
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CMOS Inverter Capacitances
Vdd • Assume input
Cgs,p Csb,p transition is fixed,
then delay
determined by
output
Cgd,p Cdb,p
Capacitance on
Vin f node f (output):
Cgd,n Cdb,n Cint
Cg
• Junction cap
Cdb,p and Cdb,n
• Gate capacitance
Cgd,p and Cgd,n
Cgs,n Csb,n • Interconnect cap
Gnd • Receiver gate cap
Amirtharajah/Parkhurst, EEC 116 Fall 2011 7
CMOS Inverter Junction Capacitances
• Junction capacitances Cdb,p and Cdb,n:
– Equation for junction cap:
m
AC j 0 ⎛ εq N a N d 1 ⎞
C j (V ) = , C j0 = ⎜⎜ ⎟⎟
⎝ 2 N a + N d φ0 ⎠
m
⎛ V⎞
⎜⎜ 1 − ⎟⎟
⎝ φ0 ⎠
– Non-linear, depends on voltage across junction
– Use Keq factor to get equivalent capacitance for a
voltage transition
Cdb = AK eq C j + PK eqswC jsw
Amirtharajah/Parkhurst, EEC 116 Fall 2011 8
CMOS Inverter Gate Capacitances
• Gate capacitances CGD,p and CGD,n:
– Just after the input switches(t = 0+), what regions
are transistors in?
– One is in cutoff: CGD = Overlap Cap
– One is in Saturation: CGD = Overlap Cap
– Therefore, gate-to-drain capacitance is due to
overlap capacitance :
C gd , p = C gd ,n = CoxWLD
However, also need to consider Miller effect ...
Amirtharajah/Parkhurst, EEC 116 Fall 2011 9
CMOS Inverter Capacitances: Miller Effect
Cgd1
Vout
Vout
Vin Vin 2Cgd1
• When input rises by ΔV, output falls by ΔV
– Change in stored charge: ΔQ = Cgd1ΔV – (-Cgd1ΔV)
– Effective voltage change across Cgd1 is 2ΔV
– Effective capacitance to ground is twice Cgd1
• Including Miller effect:
C gd , p = C gd ,n = 2CoxWLD (For transistor in Cutoff)
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CMOS Inverter Capacitances: Receiver
• Receiver gate capacitance
– Includes all capacitances of gate(s) connected to
output node
– Unknown region of operation for receiver
transistor: total gate cap varies from (2/3)WLCox to
WLCox
– Ignore Miller effect (taken into account on output)
– Assume worst-case value, include overlap
C g = WLeff Cox + 2WLD Cox
Cg = WL Cox
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Inverter Capacitances: Analysis
• Simplify the circuit: combine all capacitances at
output into one lumped linear capacitance:
Cload = 2*Cgd,n + 2*Cgd,p + Cdb,n + Cdb,p + Cint
+ Cg
Miller effect
• Csb,n = Csb,p = 0
• Cgs,n and Cgs,p are not connected to the load.
These are part of the gate capacitance Cg
Amirtharajah/Parkhurst, EEC 116 Fall 2011 12
First-Order Inverter Delay
• Suppose ideal voltage step at input
• Assume: Current charging or
discharging capacitance Cload is
nearly constant Iavg Vout
Vin
• tPHL = Cload (Vdd - Vdd/2) / Iavg Cload
• tPLH = Cload (Vdd/2 - Vss) / Iavg
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Inverter Delay: Falling
ID.n Cload
Vin
• Assume PMOS fully off (ideal step input, ID,p = 0)
dV
I =C
dt
dVout
I D ,n = Cload Need to determine ID,n
dt
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Inverter Delay: Falling
NMOS in saturation
Vdd
Vdd - Vtn NMOS in linear region
Vdd/2
t0 t1 t2
• From t0 to t1: NMOS in saturation
• From t1 to t2: NMOS in linear region
• Find ID in each region
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Inverter Delay: Falling t1-t0
• Assumption: Input fast enough to go through
transition before output voltage changes
• Vout drops from VOH to VDD-VTN (NMOS saturated)
I DS = kn (Vin − VT 0,n ) / 2 = kn (VOH − VT 0,n ) / 2
2 2
VOH −VT 0 , n
− 2CL
t1
∫t dt = kn (VOH − VT 0,n )2 ∫ dV
VOH
out
0
2CLVT 0,n
t1 − t0 =
kn (VOH − VT 0,n )2
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Inverter Delay: Falling t2-t1
• Vout drops from (VOH-VT0,n) to VDD/2
• NMOS in linear region
[
I DS = kn (VOH − VT 0,n )Vout − 12 Vout
2
]
(VOH +VOL ) / 2
dVout
t2 − t1 = −CL ∫
VOH −VT 0 ,n
[
kn (VOH − VT 0,n )Vout − 12 Vout
2
]
CL ⎡ 2(VOH − VT 0,n ) − (VOH + VOL ) / 2 ⎤
t2 − t1 = ln⎢ ⎥
kn (VOH − VT 0,n ) ⎣ (VOH + VOL ) / 2 ⎦
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Inverter Delay: Falling, Total
• Total fall delay = (t1-t0) + (t2-t1)
CL ⎡ 2VT 0,n ⎛ 4(VOH − VT 0,n ) ⎞⎤
t PHL = ⎢ + ln⎜⎜ − 1⎟⎟⎥
k n (VOH − VT 0,n ) ⎣VOH − VT 0,n ⎝ VOH + VOL ⎠⎦
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Inverter Delay: Rising
• Similar calculation as for falling delay
• Separate into regions where PMOS is in linear,
saturation
CL ⎡ 2 VT 0, p ⎛ 4(VOH − VOL − VT 0, p ) ⎞⎤
t PLH = ⎢ + ln⎜ − 1⎟⎥
k p (VOH − VOL − VT 0, p ) ⎣⎢VOH − VOL − VT 0, p ⎜ V + V ⎟⎥
⎝ OH OL ⎠⎦
• Note: to balance rise and fall delays (assuming VOH =
VDD, VOL = 0V, and VT0,n=VT0,p) requires
⎛W ⎞
kp ⎜ ⎟
⎝ L ⎠ p μn
=1 ⎛W ⎞
=
μp
≈ 2.5
kn ⎜ ⎟
⎝ L ⎠n
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Inverter Rise, Fall Times
• Summary -- Exact method: separate into two regions
– t1
• Vout drops from 0.9VDD to VDD-VT,n (NMOS in
saturation)
• Vout rises from 0.1VDD to |VT,p| (PMOS in saturation)
– t2
• Vout drops from VDD-VT,n to 0.1VDD (NMOS in linear
region)
• Vout rises from |VT,p| to 0.9 VDD (PMOS in linear
region)
– tf,r = t1 + t2
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CMOS Inverter Delay
• Review of approximate
method
– Assume a constant average I1
V1=Vdd
current for the transition
– Iavg = average of drain V2=½Vdd I2
current at beginning and end
of transition
t1 t2
t PHL =
Cload
(VDD − 12 VDD )
I avg Iavg = ½(I1+I2)
t PLH =
Cload
( 12 VDD − VSS )
I avg
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CMOS Inverter Delay: 2nd Approximation
• Another approximate
method:
– Again assume constant Iavg
– Iavg = current I1 at start of I1
V1=Vdd
transition
CloadVDD
t PHL = V2=½Vdd
k n (VDD − VTn )
2
CloadVDD
t PLH =
k p (VDD − VTP )
2 t1 t2
– Why is this a good Iavg = I1
approximation (esp. for deep
submicron)?
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CMOS Inverter Delay: Finite Input Transitions
• What if input has finite rise/fall time?
– Both transistors are on for some amount of time
– Capacitor charge/discharge current is reduced
Empirical equations:
2
⎛ tr ⎞
tpHL(ns)
t phl (actual ) = t phl ( step ) + ⎜ ⎟
2
⎝2⎠
2
⎛tf ⎞
t plh (actual ) = t ( step ) + ⎜⎜ ⎟⎟
2
plh
⎝2⎠
trise(ns)
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How to Improve Delay?
• Minimize load capacitances
– Small interconnect capacitance
– Small Cg of next stage
• Raise supply voltage
– Increases current faster than increased swing ΔV
• Increase transistor gain factor
– Increase transistor drive current for
charging/discharging output capacitance
• Use low threshold voltage devices
– More subthreshold leakage power dissipation
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Inverter Power Consumption
• Static power consumption (ideal) = 0
– Actually DIBL (Drain-Induced Barrier Lowering),
gate leakage, junction leakage are still present
• Dynamic power consumption
T
1
Pavg = ∫ v(t )i(t )dt
T0
1⎡ ⎛ dVout ⎞ ⎛ dVout ⎞ ⎤
T /2 T
Pavg = ⎢ ∫ Vout ⎜ − Cload ⎟dt + ∫ (VDD − Vout )⎜ Cload ⎟dt ⎥
T⎣0 ⎝ dt ⎠ T /2 ⎝ dt ⎠ ⎦
⎡ T /2 T ⎤
1 ⎢⎛ Vout ⎞
⎟ + ⎛⎜VDDVout Cload − CloadVout 2 ⎞⎟ ⎥
2
1
Pavg = ⎜ − Cload
T ⎢⎜⎝ 2 ⎟⎠ ⎝ 2 ⎠ T /2 ⎥
⎣ 0 ⎦
1
Pavg = CloadVDD = CloadVDD f
2 2
T
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Next Time: Combinational Logic and Layout
• Combinational MOS Logic
– DC Characteristics, Equivalent Inverter method
– AC Characteristics, Switch Model
• Combinational Logic Layout
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