UNIT - 2

Faculty: Dr. Jisha P

Syllabus
Gate Level Modelling: Gate Types, Gate Delays, Examples.
Dataflow Modelling: Continuous assignment, Delays, Expressions,
Operators, Operands, Operator Types, and Examples.

Dr. Jisha P BMSCE 2

Gate Types
➢A logic circuit can be designed by use of logic gates.

➢Verilog supports basic logic gates as predefined primitives.

➢These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition.

➢All logic circuits can be designed by using basic gates.

➢There are two classes of basic gates: and/or gates and buf/not gates.

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And/Or Gates
◦ And/or gates have one scalar output
and multiple scalar inputs.
◦ The first terminal in the list of gate
terminals is an output and the other
terminals are inputs.
◦ The output of a gate is evaluated as
soon as one of the inputs changes.
◦ The and/or gates available in Verilog
are shown below.
◦ and or xor nand nor xnor
◦ These gates are instantiated to
build logic circuits in Verilog.
Dr. Jisha P BMSCE 4
Example - Gate Instantiation of And/Or Gates
wire OUT, IN1, IN2;
// basic gate instantiations.
and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);
xor x1(OUT, IN1, IN2);
xnor nx1(OUT, IN1, IN2);
nand na1_3inp(OUT, IN1, IN2, IN3);// More than two inputs; 3 input nand gate
and (OUT, IN1, IN2); // gate instantiation without instance name
// legal gate instantiation

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Truth Tables for And/Or

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 Buf/Not Gates
◦ Buf/not gates have one scalar input and one or more scalar outputs.
◦ The last terminal in the port list is connected to the input. Other
terminals are connected to the outputs.
◦ We will discuss gates that have one input and one output.
◦ Two basic buf/not gate primitives are provided in Verilog.
◦ buf not
◦ The symbols for these logic gates are

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Example - Gate Instantiations of Buf/Not Gates
Truth Tables for Buf/Not Gates
◦ // basic gate instantiations.
◦ buf b1(OUT1, IN);
◦ not n1(OUT1, IN);
◦ // More than two outputs
◦ buf b1_2out(OUT1, OUT2, IN);
◦ // gate instantiation without instance name
◦ not (OUT1, IN); // legal gate instantiation

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 Bufif/notif
◦ Gates with an additional control signal on
buf and not gates are also available.
◦ bufif1 notif1
◦ bufif0 notif0
◦ These gates propagate only if their
control signal is asserted.
◦ They propagate z if their control
signal is deasserted.
◦ Symbols for bufif/notif are:

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 Truth Tables for Bufif/Notif Gates

• These gates are used when a signal

is to be driven only when the control
signal is asserted.
• Such a situation is applicable when
multiple drivers drive the signal.
• These drivers are designed to drive
the signal on mutually exclusive
control signals.

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 Gate Instantiations of Bufif/Notif Gates
//Instantiation of bufif gates.
bufif1 b1 (out, in, ctrl);
bufif0 b0 (out, in, ctrl);
//Instantiation of notif gates
notif1 n1 (out, in, ctrl);
notif0 n0 (out, in, ctrl);

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Array of Instances
◦ Simple Array of Primitive Instances
wire [7:0] OUT, IN1, IN2;
// basic gate instantiations.
nand n_gate[7:0](OUT, IN1, IN2);
// This is equivalent to the following 8 instantiations
nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);

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Design of Gate-level Digital Circuits:
Multiplexer
◦ A multiplexer is a combinational circuit that has many data inputs and a single output,
depending on control or select inputs.

◦ For N input lines, log2(N) selection lines are required, or equivalently, for 2n
input lines, n selection lines are needed.

◦ Multiplexers are also known as “N-to-1 selectors,” parallel-to-serial converters, many-

to-one circuits, and universal logic circuits.

◦ They are mainly used to increase the amount of data that can be sent over a network
within a certain amount of time and bandwidth .

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 Multiplexer
◦ Multiplexer is an combinational circuit which has 2,4,8 and
so on inputs with select line 1,2,3 and so on.

◦ Output of the multiplexer is connected to the particular

input based on the select line.

◦ For example in 2X1 MUX, if select line is 0, first input is

selected else second input is selected.

◦ There are different ways to describe MUX in Verilog.

◦ We can use gate level modelling, we can use data flow

modelling, we can use ternary operator, we can use if else
statement or we can use case statement.

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 Types of Mux: 2X1 Multiplexer
◦ The Mux can be of different types based on input but in this article we will go
through two major types of mux which are
◦ 2×1 Mux
◦ 4×1 Mux
◦ 2×1 Multiplexer
◦ The 2×1 is a fundamental circuit which is also known 2-to-1 multiplexer that are
used to choose one signal from two inputs and transmits it to the output.
◦ The 2×1 mux has two input lines, one output line, and a single selection line.
◦ It has various applications in digital systems such as in microprocessor it is
used to select between two different data sources or between two different
instructions.

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 2X1 Multiplexer
◦ In this Block Diagram where I0 and I1
are the input lines ,Y is the output line
and S0 is a single select line.
◦ The output of the 2×1 Mux will depend
on the selection line S0,
◦ When S is 0(low), the I0 is selected
◦ when S0 is 1(High), I1 is selected
◦ Logical Expression of 2×1 Mux Using
the Truth Table , the Logical
Expression for Mux can be determined
as:

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 2X1 Multiplexer
◦ Circuit Diagram of 2×1 Multiplexers:

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2X1 Multiplexer Verilog Code

◦ Basic 2X1 MUX in gate level

modelling.
◦ It has two inputs, one select line and
one output.
◦ The boolean expression for 2X1 is given as

◦ For this, we require two AND gate, one OR

gate and one NOT gate.

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Examples: Design of Gate-level Digital Circuits
◦ Gate-level multiplexer
◦ Design a 4-to-1 multiplexer with 2 select signals.
◦ Multiplexers serve a useful purpose in logic design.
◦ They can connect two or more sources to a single destination.
◦ They can also be used to implement Boolean functions.
◦ Assume for this example that signals s1 and s0 do not get the value x or z.
◦ The I/O diagram and the truth table for the multiplexer

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 Design of Gate-level Digital Circuits
◦ The I/O diagram will be useful in setting up the port list for the 4-to-1 Multiplexer.

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4×1 Multiplexer
◦ The 4×1 Multiplexer which is also known as the 4-to-1
multiplexer.
◦ It is a multiplexer that has 4 inputs and a single output.
◦ The Output is selected as one of the 4 inputs which is
based on the selection inputs.
◦ The number of the Selection lines will depend on the
number of the input which is determined by the equation
log2n, In 4×1 Mux the selection lines can be determined as
log24 =2. so two selections linputs are needed.
◦ In the Given Block Diagram I0, I1, I2, and I3 are the 4
inputs and Y is the Single output which is based on
Select lines S0 and S1.
◦ Multiplexer can act as universal combinational circuit. All
the standard logic gates can be implemented with
multiplexers.
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Truth Table and Circuit Diagram of 4×1 Multiplexer

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4-to-1 Multiplexer

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Design of Gate-level Digital Circuits
◦ The gate-level modeling is virtually the lowest abstract level of modeling.
◦ This style of modeling will include primitive gates that are predefined in
Verilog HDL.
◦ The designer should know the basic logic circuit and the logic gates that
are employed in that circuit for a particular system.
◦ There is another abstraction layer below gate-level: switch level modeling,
which deals with the transistor technologies.

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 Design of Gate-level Digital Circuits-
4-to-1 Multiplexer
◦ The logic diagram for the multiplexer using basic logic gates :

• The logic diagram has a one-to-one

correspondence with the Verilog description.
• Two intermediate nets, s0n and s1n, are
created; they are complements of input
signals s1 and s0.
• Internal nets y0, y1, y2, y3 are also required.
• Note that instance names are not specified for
primitive gates, not, and, and or.
• Instance names are optional for Verilog
primitives but are mandatory for instances of
user-defined modules.
Dr. Jisha P BMSCE 25
Verilog Description of 4:1Multiplexer
// Module 4-to-1 multiplexer. Port // Gate instantiations
list //is taken exactly from the I/O // Create s1n and s0n signals.
diagram.
not (s1n, s1);
module mux4_to_1 (out, i0, i1, i2,
i3, s1, s0); not (s0n, s0);
// Port declarations from the I/O // 3-input and gates instantiated
diagram and (y0, i0, s1n, s0n);
output out; and (y1, i1, s1n, s0);
input i0, i1, i2, i3; and (y2, i2, s1, s0n);
input s1, s0; and (y3, i3, s1, s0);
// Internal wire declarations // 4-input or gate instantiated
wire s1n, s0n; or (out, y0, y1, y2, y3);
wire y0, y1, y2, y3; endmodule

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Verilog Description of Stimulus for Multiplexer
// Define the stimulus module (no ports) IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0; // set input lines
module stimulus; #1 $display("IN0= %b, IN1= %b, IN2= %b, IN3=
// Declare variables to be connected %b\n",IN0,IN1,IN2,IN3);

// to inputs S1 = 0; S0 = 0; // choose IN0

reg IN0, IN1, IN2, IN3; #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
reg S1, S0; S1 = 0; S0 = 1; // choose IN1
// Declare output wire #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
wire OUTPUT; S1 = 1; S0 = 0; // choose IN2
// Instantiate the multiplexer #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
mux4_to_1 mymux(OUTPUT, IN0, IN1, S1 = 1; S0 = 1; // choose IN3
IN2, IN3, S1, S0);
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
// Stimulate the inputs
end
// Define the stimulus module (no ports)
endmodule
initial
begin
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Output

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The output of the simulation is shown below. Each combination of the
select signals is tested.

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Schematic
Design of Gate-level Digital Circuits-8×1 multiplexer
An 8-to-1 multiplexer is a digital device that
selects one of the eight inputs lines to the output line
by using three-bit selection line.

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'
.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+
S0'.S1.S2.A6+S0.S1.S3.A7
Dr. Jisha P BMSCE 31
Design of Gate-level Digital Circuits-8×1 multiplexer

◦ Logic diagram for 8×1

MUX:
◦ The input signals are
A0, A1, A2, A3, A4, A5,
A6, A7, S0, S1, S2 and
the output signal is Y.

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Verilog Description of 8:1Multiplexer
`timescale 1ns/1ps
module m81(input A0, A1, A2, A3, A4, A5, A6, A7, S0, S1, S2, output Y);
wire T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11;
not(T1, S0);
not(T2, S1); If there exist more than two same gates, we
not(T3, S2); can concatenate the expression into one
single statement !
and(T4, A0, T1, T2, T3), (T5, A1, S0, T2, T3); Eg: not(T1, S0), (T2, S1), (T3, S2);
and(T6, A2, T1, S1, T3), (T7, A3, S0, S1, T3);
and(T8, A4, T1, T2, S2), (T9, A5, S0, T2, S2);
and(T10, A6, T1, S1, S2), (T11, A7, S0, S1, S2);
or(out, T4, T5, T6, T7, T8, T9, T10, T11);
endmodule Dr. Jisha P BMSCE 33
Verilog Description of 8:1Multiplexer- TB
initial begin // Initialize Inputs
S0 = 0;S1 = 0;S2 = 0;A0 = 1;A1 = 0;A2 = 0; A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
// Wait 100 ns for global reset to finish
#100; // Add stimulus here
#100; S0 = 0;S1 = 0;S2 = 1;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
#100; S0 = 0;S1 = 1;S2 = 0;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
#100; S0 = 0;S1 = 1;S2 = 1;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
#100; S0 = 1;S1 = 0;S2 = 0;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
#100; S0 = 1;S1 = 0;S2 = 1;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
#100; S0 = 1;S1 = 1;S2 = 0;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
#100; S0 = 1;S1 = 1;S2 = 1;A0 = 0;A1 = 1;A2 = 0;A3 = 0;A4 = 0;A5 = 0;A6 = 0;A7 = 0;
end
endmodule Dr. Jisha P BMSCE 34
Simulation Output

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Design Methodology - example
◦ Top-Down Design Approach
1. 8x1 Multiplexer: The main module will have eight inputs (D0 to D7), three selection lines (S2, S1, S0),
and one output (Y).

2. 4x1 Multiplexer: This will be used as an intermediate block to select between four inputs, controlled by
two selection lines (S1, S0).

3. 2x1 Multiplexer: This will serve as the base building block. Each 2x1 multiplexer will have two inputs,
one select line, and one output.

◦ Bottom up Design Approach

1. Step 1: Start with the smallest module, the 2x1 multiplexer.

2. Step 2: Use multiple 2x1 multiplexers to build a 4x1 multiplexer.

3. Step 3: Use the 4x1 multiplexers to construct the 8x1 multiplexer.

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4 : 1 MUX using 2 : 1 MUX

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Verilog Code - Bottom up Design Approach
◦ Verilog Code for 4×1 Mux
◦ Verilog Code for 2×1 Mux
module mux4x2(out,i0,i1,i2,i3,s1,s0);
module mux2x1(out,a,b,s);
input i0,i1,i2,i3,s1,s0;
input a,b,s;
output out;
wire and_1,and_2,s_c;
wire mux1,mux2;
output out;
mux2x1 mux_1(mux1,i0,i1,s1);
not (s_c,s);
mux2x1 mux_2(mux2,i2,i3,s1);
and (and_1,a,s_c);
mux2x1 mux_3(out,mux1,mux2,s0);
and (and_2,b,s);
endmodule
or (out,and_1,and_2);
endmodule

Dr. Jisha P BMSCE 38

Test Bench code for 4×1 Mux
module mux4x2_tb;
wire t_out; #5 //3
reg t_a, t_b, t_c, t_d, t_s1, t_s0; t_a = 1'b0;t_b = 1'b0;t_c = 1'b1;t_d = 1’b0;
mux4x2 my_4x2_mux( .i0(t_a), .i1(t_b), .i2(t_c), .i3(t_d), t_s0 = 1'b1;t_s1 = 1'b0;
.s1(t_s1), .s0(t_s0), .out(t_out) ); #5 //4
initial t_a = 1'b0;t_b = 1'b0;t_c = 1'b0;t_d = 1’b1;
begin t_s0 = 1'b1;t_s1 = 1'b1;
// 1 #5 //5
t_a = 1'b1;t_b = 1'b0;t_c = 1'b1;t_d = 1’b1; t_a = 1'b1;t_b = 1'b0;t_c = 1'b0;t_d = 1’b0;
t_s0 = 1'b0;t_s1 = 1'b1; t_s0 = 1'b0;t_s1 = 1'b0;
#5 //2 end
t_a = 1'b0;t_b = 1'b1;t_c = 1'b0;t_d = 1’b0; endmodule
t_s0 = 1'b0;t_s1 = 1'b1;

Dr. Jisha P BMSCE 39

 8 : 1 MUX using 4 : 1 MUX
We can implement the 8×1 multiplexer using
a lower order multiplexer.
To implement the 8×1 multiplexer, we need
two 4×1 multiplexers and one 2×1 multiplexer.
The 4×1 multiplexer has 2 selection lines, 4
inputs, and 1 output. The 2×1 multiplexer has
only 1 selection line.
For getting 8 data inputs, we need two 4×1
multiplexers. The 4×1 multiplexer produces
one output. So, in order to get the final output,
we need a 2×1 multiplexer.

Dr. Jisha P BMSCE 40

 Verilog Code – Top-Down Design Approach
module mux_4_1(i0, i1, i2, i3, s0, module mux_2_1(i0,
module mux_8_1(i0, i1, i2, i3, i4, i5, i6,
s1, y); i1, s0, y);
i7, s0, s1, s2, y);
input i0, i1, i2, i3, s0, s1; input i0, i1, s0;
input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
output y; output y;
output y;
wire y1, y2;
wire not_s0, not_s1; wire not_s0, and0,
// Instantiate two 4:1 multiplexers for
wire and0, and1, and2, and3; and1;
lower and upper 4 bits
not (not_s0, s0);
mux_4_1 mux_lower (i0, i1, i2, i3, s0,
not (not_s1, s1); not (not_s0, s0);
s1, y1);
and (and0, i0, not_s0, not_s1 and (and0, i0, not_s0);
mux_4_1 mux_upper (i4, i5, i6, i7, s0,
and (and1, i1, s0, not_s1); and (and1, i1, s0);
s1, y2);
and (and2, i2, not_s0, s1);
// Use a 2:1 MUX to choose between y1
and (and3, i3, s0, s1); or (y, and0, and1);
and y2
or (y, and0, and1, and2, and3); endmodule
mux_2_1 mux_final (y1, y2, s2, y);
endmodule
endmodule
Dr. Jisha P BMSCE 41
Verilog Code - behavioural
module module module
mux_8_1(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2,y) mux_4_1(i0,i1,i2,i3,s0,s1,y); mux_2_1(i0,i1,s0,y);
; input i0,i1,i2,i3,s0,s1; input i0,i1,s0;
input i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2; output reg y; output reg y;
output reg y; always @(*) always @(*)
begin begin
wire y1,y2; case ({s0,s1}) case (s0)

// always @(*) 2'b00: y = i0; 1'b0:y=i0;

// begin 2'b01: y = i1; 1'b1:y=i1;
2'b10: y = i2; default:y=0;
mux_4_1 g1(i0,i1,i2,i3,s0,s1,y1); 2'b11: y = i3;
mux_4_1 g2(i4,i5,i6,i7,s0,s1,y2); default: y = 0; endcase
mux_2_1 g3(y1,y2,s2,y); end
// end endcase endmodule
endmodule end
endmodule
Dr. Jisha P BMSCE 42
16 x 1 Multiplexer

The logical expression of the

term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.
S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.
S3+A4.S0'.S1.S2'.S3'+A5.S0 '.S1.S2'.
S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+
A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+
Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3+
A12S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+
A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

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Logical circuit of the above expression is given below:

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16×1 multiplexer using 8×1 and 2×1 multiplexer

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// Verilog code - Gate-level modeling of 8:1 multiplexer
module mux_8_1(i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2, y);
input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
output y;
wire not_s0, not_s1, not_s2;
wire and0, and1, and2, and3, and4, and5, and6, and7;
// Inverting select lines
not (not_s0, s0);
not (not_s1, s1);
not (not_s2, s2);
// AND gates to select the correct input based on select lines
and (and0, i0, not_s0, not_s1, not_s2); // when s2s1s0 = 000, select i0
and (and1, i1, s0, not_s1, not_s2); // when s2s1s0 = 001, select i1
and (and2, i2, not_s0, s1, not_s2); // when s2s1s0 = 010, select i2
and (and3, i3, s0, s1, not_s2); // when s2s1s0 = 011, select i3
and (and4, i4, not_s0, not_s1, s2); // when s2s1s0 = 100, select i4
and (and5, i5, s0, not_s1, s2); // when s2s1s0 = 101, select i5
and (and6, i6, not_s0, s1, s2); // when s2s1s0 = 110, select i6
and (and7, i7, s0, s1, s2); // when s2s1s0 = 111, select i7
// OR gate to combine the results
or (y, and0, and1, and2, and3, and4, and5, and6, and7);
endmodule Dr. Jisha P BMSCE 46
Verilog Code – Gate Level
// Gate-level modeling of 2:1 // Top-level module: 16:1 multiplexer using two 8:1
multiplexer multiplexers and one 2:1 multiplexer
module mux_2_1(i0, i1, s0, y); module mux_16_1( input i0, i1, i2, i3, i4, i5, i6, i7,
input i0, i1, s0; input i8, i9, i10, i11, i12, i13, i14, i15,
input s0, s1, s2, s3, output y);
output y;
wire y1, y2; // Outputs of the two 8:1 multiplexers
wire not_s0, and0, and1;
// Instantiate two 8:1 multiplexers
not (not_s0, s0);
mux_8_1 mux1 (i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2, y1);
and (and0, i0, not_s0);
// when s0 = 0, select i0 mux_8_1 mux2 (i8, i9, i10, i11, i12, i13, i14, i15, s0, s1, s2, y2);
and (and1, i1, s0); // Instantiate a 2:1 multiplexer to select between the outputs of
// when s0 = 1, select i1
the two 8:1 MUXes
// OR gate to produce final output mux_2_1 mux3 (y1, y2, s3, y);
or (y, and0, and1);
endmodule endmodule

Dr. Jisha P BMSCE 47

16 x 1 Multiplexer using 4 x 1 MUX
◦ You need a combinational
logic with 16 input pins, 4
select lines, and one output.
◦ In a 4:1 mux, you have 4
input pins, two select lines,
and one output.
◦ At least you have to use 4
4:1 MUX, to obtain 16 input
lines.
◦ But you then have a logic with
4 output pins.
◦ We can use another 4:1
MUX, to multiplex only one of
those 4 outputs at a time. Dr. Jisha P BMSCE 48
Verilog Code – Gate Level
module mux4to1_gate(out,in,sel); module mux16to1(out,in,sel);

input [0:3] in; input [0:15] in;

input [0:1] sel; input [0:3] sel;
output out; output out;
wire a,b,c,d,n1,n2,a1,a2,a3,a4; wire [0:3] ma;
not n(n1,sel[1]);
not nn(n2,sel[0]); mux4to1_gate mux1(ma[0],in[0:3],sel[2:3]);

and (a1,in[0],n1,n2); mux4to1_gate mux2(ma[1],in[4:7],sel[2:3]);

and (a2,in[1],n2,sel[1]);
and (a3,in[2],sel[0],n1); mux4to1_gate mux3(ma[2],in[8:11],sel[2:3]);
and (a4,in[3],sel[0],sel[1]);
mux4to1_gate mux4(ma[3],in[12:15],sel[2:3]);
or or1(out,a1,a2,a3,a4);
mux4to1_gate mux5(out,ma,sel[0:1]);
endmodule endmodule
Dr. Jisha P BMSCE 49
Test Bench File for 16:1 MUX in=16'b1000000000000000; sel=4'b0000;
module testmux_16; #30 in=16'b0100000000000000; sel=4'b0001;
#30 in=16'b0010000000000000; sel=4'b0010;
reg [0:15] in;
#30 in=16'b0001000000000000; sel=4'b0011;
reg [0:3] sel; #30 in=16'b0000100000000000; sel=4'b0100;

wire out; #30 in=16'b0000010000000000; sel=4'b0101;

#30 in=16'b0000001000000000; sel=4'b0110;
mux16to1 mux(out,in,sel); #30 in=16'b0000000100000000; sel=4'b0111;

initial #30 in=16'b0000000010000000; sel=4'b1000;

#30 in=16'b0000000001000000; sel=4'b1001;
begin #30 in=16'b0000000000100000; sel=4'b1010;
$monitor("in=%b | sel=%b | out=%b", #30 in=16'b0000000000010000; sel=4'b1011;

in,sel,out); #30 in=16'b0000000000001000; sel=4'b1100;

#30 in=16'b0000000000000100; sel=4'b1101;
end #30 in=16'b0000000000000010; sel=4'b1110;

initial #30 in=16'b0000000000000001; sel=4'b1111;

begin end
50
endmodule
De-multiplexer

Dr. Jisha P BMSCE 51

De-multiplexer
◦ A De-multiplexer is a combinational circuit that has only 1 input line and 2N output
lines.
◦ Simply, the multiplexer is a single-output and multi-input combinational circuit.
◦ De-multiplexer is opposite to the multiplexer.
◦ The information is received from the single input lines and directed to the output
line. On the basis of the values of the selection lines, the input will be connected to
one of these outputs.
◦ Unlike encoder and decoder, there are n selection lines and 2n outputs.
◦ So, there is a total of 2n possible combinations of inputs.
◦ There are various types of De-multiplexer which are as follows: 1×2, 1×4, 1×8..etc

Dr. Jisha P BMSCE 52

1×2 De-multiplexer:
◦ In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0,
and single input, i.e., A.
◦ On the basis of the selection value, the input will be connected to one of the outputs. The block
diagram and the truth table of the 1×2 multiplexer are given below.
Logical circuit

The logical expression of the term Y is as follows

Y0=S0’.A Y1=S0.A

Dr. Jisha P BMSCE 53

Gate level modelling: 1×2 De-multiplexer:

Dr. Jisha P BMSCE 54

Simulation Output

Dr. Jisha P BMSCE 55

1×4 De-multiplexer:
◦ In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2
selection lines, i.e., S0 and S1 and single input, i.e., A.
◦ On the basis of the combination of inputs which are present at the selection lines S0
and S1, the input be connected to one of the outputs.
◦ The block diagram and the truth table of the 1×4 multiplexer are given below.
Truth Table:

Dr. Jisha P BMSCE 56

1×4 De-multiplexer: Logical circuit

◦ The logical expression of the

term Y is as follows:

◦ O0=S1' S0’ i
◦ O1=S1' S0 i
◦ O2=S1 S0’ i
◦ O3=S1 S0 i

Dr. Jisha P BMSCE 57

Gate level modelling: 1×4 De-multiplexer:
module demux ( input i,s1,s0, output o0,o1,o2,o3 );
wire s1n, s0n, o0,o1,o2,o3;
not(s1n,s1);
not(s0n,s0);
and(o0,s1n,s0n,i);
and (o1,s1n,s0,i);
and(o2,s1,s0n,i);
and(o3,s1,s0,i);
endmodule
Dr. Jisha P BMSCE 58
Gate level modelling: 1×4 De-multiplexer-TB
module demux_tb;
reg I, s1, s0; // Inputs
wire o0,o1, o2,o3; // Outputs
demux uut (i,s1,s0, o0,o1,o2,o3 );
initial begin // Testbench logic

i = 0; s1 = 0; s0 = 0; 10; // Initialize Inputs

i = 1; s1 = 0; s0 = 0; // Test case 1: s1=0, s0=0, i=1 -> o0 should be 1
#10; i = 1; s1 = 0; s0 = 1; // Test case 2: s1=0, s0=1, i=1 -> o1 should be 1
#10; i = 1; s1 = 1; s0 = 0; // Test case 3: s1=1, s0=0, i=1 -> o2 should be 1
#10; i = 1; s1 = 1; s0 = 1; // Test case 4: s1=1, s0=1, i=1 -> o3 should be 1
#10; i = 0; s1 = 1; s0 = 1; // Test case 5: i=0, all outputs should be 0
#10; // End simulation
$stop;

end
endmodule 59

Dr. Jisha P BMSCE

1×8 De-multiplexer:
◦ In 1 to 8 De-multiplexer, there
are total of eight outputs, i.e.,
Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0,
S1and S2 and single input, i.e.,
A.
◦ On the basis of the
combination of inputs which
are present at the selection
lines S0, S1 and S2, the input
will be connected to one of
these outputs.

Dr. Jisha P BMSCE 60

1×8 De-multiplexer: The logical expression
of the term Y is as
follows:
Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2A
Y5=S0.S1'.S2A
Y6=S0'.S1.S2A
Y7=S0.S1.S3.A
Dr. Jisha P BMSCE 61
Logical circuit of the above expressions is given below:

Dr. Jisha P BMSCE 62

Verilog code
module demux_1_to_8( input d,s0,s1,s2,output y0, y1,y2,y3, y4, y5, y6, y7 );

not (s0n,s0),(s1n,s1),(s2n,s2);

and g1 (y0,d,s0n,s1n,s2n);
and g2 (y1,d,s0,s1n,s2n);
and g3 (y2,d,s0n,s1,s2n);
and g4 (y3,d,s0,s1,s2n);
and g5 (y4,d,s0n,s1n,s2);
and g6 (y5,d,s0,s1n,s2);
and g7 (y6,d,s0n,s1,s2);
and g8 (y7,d,s0,s1,s2);
endmodule
Dr. Jisha P BMSCE 63
//Testbench code for 1-8 DEMUX Structural/Gate Level Modelling
initial begin
// Initialize Inputs

d = 0;s0 = 0;s1 = 0;s2 = 0;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
#100; d = 1;s0 = 0;s1 = 0;s2 = 0;
#100; d = 1;s0 = 1;s1 = 0;s2 = 0;
#100; d = 1;s0 = 0;s1 = 1;s2 = 0;
#100; d = 1;s0 = 1;s1 = 1;s2 = 0;
#100; d = 1;s0 = 0;s1 = 0;s2 = 1;
#100; d = 1;s0 = 1;s1 = 0;s2 = 1;
#100; d = 1;s0 = 0;s1 = 1;s2 = 1;
#100; d = 1;s0 = 1;s1 = 1;s2 = 1;
end
Dr. Jisha P BMSCE 64
 1×8 De-multiplexer using 1×4 and
1×2 de-multiplexer
◦ We can implement the 1×8 de-multiplexer using
a lower order de-multiplexer.
◦ To implement the 1×8 de-multiplexer, we need
two 1×4 de-multiplexer and one 1×2 de-
multiplexer.
◦ The 1×4 multiplexer has 2 selection lines, 4
outputs, and 1 input.
◦ The 1×2 de-multiplexer has only 1 selection line.
◦ For getting 8 data outputs, we need two 1×4 de-
multiplexer.
◦ The 1×2 de-multiplexer produces two outputs.
◦ So, in order to get the final output, we have to
pass the outputs of 1×2 de-multiplexer as an input
of both the 1×4 de-multiplexer. Dr. Jisha P BMSCE 65
1 x 16 De-multiplexer

◦ In 1×16 de-
multiplexer, there are
total of 16 outputs,
i.e., Y0, Y1, …, Y16,
4 selection lines, i.e.,
S0, S1, S2, and S3
and single input, i.e.,
A. On the basis of
the combination of
inputs which are
present at the
selection lines S0,
S1, and S2, the input
will be connected to
one of these outputs.

Dr. Jisha P BMSCE 66

 Logical circuit:
◦ The logical expression of the
term Y is as follows:
◦ Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3’
Y15=A.S0.S1.S2'.S3

Dr. Jisha P BMSCE 67

The block diagram of 1×16
de-multiplexer using 1×8
and 1×2 de-multiplexer

Dr. Jisha P BMSCE 68

 Eg: 4-bit Ripple Carry Full Adder
◦ The basic building block is a 1-bit full adder.
◦ The mathematical equations for a 1-bit full adder are shown below.
◦ sum = (a ⊕ b ⊕ cin)
◦ cout = (a . b) + cin . (a ⊕ b)
◦ The logic diagram for a 1-bit full adder is shown in Figure.

c2

Dr. Jisha P BMSCE 69

Eg: 4-bit Ripple Carry Full Adder
◦ Verilog Description for 1-bit Full
Adder
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;
// Instantiate logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
Dr. Jisha P BMSCE 70
Eg: 4-bit Ripple Carry Full Adder
◦ A 4-bit ripple carry full adder can be constructed from four 1-bit full adders, as
shown in Figure.
◦ Note that fa0, fa1, fa2, and fa3 are instances of the module fulladd (1-bitfull
adder).

Dr. Jisha P BMSCE 71

Eg: 4-bit Ripple Carry Full Adder
◦ Note that the port names used in a 1-bit full adder and a 4-bit full adder are the
same but they represent different elements.
◦ The element sum in a 1-bit adder is a scalar quantity and the element sum in the
4-bit full adder is a 4-bit vector quantity.
◦ Verilog keeps names local to a module.
◦ Names are not visible outside the module unless hierarchical name referencing is
used.
◦ Also note that instance names must be specified when defined modules are
instantiated, but when instantiating Verilog primitives, the instance names are
optional.

Dr. Jisha P BMSCE 72

Verilog Description for 4-bit Ripple Carry Full Adder
// Define a 4-bit full adder module stimulus;
reg [3:0] A, B; // Set up variables
module fulladd4(sum, c_out, a, b, c_in); reg C_IN;
// I/O port declarations wire [3:0] SUM;
wire C_OUT;
output [3:0] sum;
// Instantiate the 4-bit full adder. call it FA1_4
output c_out;
input[3:0] a, b; fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);
Initial begin
input c_in; $monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b,
// Internal nets SUM= %b\n",A, B, C_IN, C_OUT, SUM);
end
wire c1, c2, c3; Initial begin // Stimulate inputs
// Instantiate four 1-bit full adders. A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
#5 A = 4'd2; B = 4'd5;
fulladd fa1(sum[1], c2, a[1], b[1], c1); #5 A = 4'd9; B = 4'd9;
fulladd fa2(sum[2], c3, a[2], b[2], c2); #5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
fulladd fa3(sum[3], c_out, a[3], b[3], c3); end
endmodule Dr. Jisha Pendmodule BMSCE 73
Verilog Description for 4-bit Ripple Carry
Full Adder
The output of the simulation is shown below:
0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000
5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111
10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111
15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010
20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
25 A= 1010, B=0101, C_IN= 1,, C_OUT= 1, SUM= 0000

Dr. Jisha P BMSCE 74

Gate Delays
◦ In real circuits, logic gates have delays associated with them. Gate delays allow the Verilog user to
specify delays through the logic circuits. Pin-to-pin delays can also be specified in Verilog.
◦ Verilog gate delays specify how values propagate through nets or gates.
◦ The gate delay declaration specifies a time needed to propagate a signal change from the gate input
to its output.
◦ The gate delay declaration can be used in gate instantiations. The delays can also be used for
delay control in procedural statements.
◦ Digital elements are binary entities and only hold either of the two values, 0 and 1.
◦ The transition from 0 to 1 and 1 to 0 has a transitional delay, and therefore each gate element
propagates the value from input to its output.
◦ For example, a two-input AND gate has to switch the output to 1 if both inputs become 1 and back to
0 when inputs become 0.
◦ The net delay declaration specifies a time needed to propagate values from drivers through the net.
It can be used in continuous assignments and net declarations.
◦ Dr. Jisha P BMSCE 75
Gate Delays: Rise, Fall, and Turn-off Delays

◦ The delays declaration can contain up to three values, such as rise, fall, and turn-off
delays.
◦ The time taken for the output of a gate to change from some value to 1 is called a
rise delay.
◦ The time taken for the output of a gate to change form some value to 0 is called a
fall delay.
◦ The time taken for the output of a gate to change from some value to high
impedance is called turn-off delay.
◦ If only one delay value is specified, then it is used for all signal changes. The default
delay is zero.
◦ If two delays are specified, then the first delay specifies the rise delay, and the
second delay specifies the fall delay.
◦ If the signal changes to high-impedance or unknown, then the smaller value will be used.
Dr. Jisha P BMSCE 76
Rise delay
◦ The rise delay is associated with a gate output transition to a 1 from
another value.

Dr. Jisha P BMSCE 77

Fall delay
◦ The fall delay is associated with a gate output transition to a 0 from
another value.

Dr. Jisha P BMSCE 78

Turn-off delay
◦ The turn-off delay is associated with a gate output transition to the high
impedance value(z) from another value.
◦ If the value changes to x, the minimum of the three delays is considered.
◦ Types of Delay Specification:
◦ // Delay of delay_time for all transitions
and #(delay_time) a1(out, i1, i2);
◦ // Rise and Fall Delay Specification.
and #(rise_val, fall_val) a2(out, i1, i2);
◦ // Rise, Fall, and Turn-off Delay Specification
bufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);
Dr. Jisha P BMSCE 79
Gate Delays: Min/Typ/Max Values
◦ Verilog provides an additional level of control for each type of delay mentioned above.
◦ For each type of delay rise, fall, and turn-off three values, min, typ, and max, can be
specified.
◦ Any one value can be chosen at the start of the simulation.
◦ Min/typ/max values are used to model devices whose delays vary within a minimum
and maximum range because of the IC fabrication process variations.
◦ Min value
◦ The min value is the minimum delay value that the designer expects the gate to have.
◦ Typ val
◦ The typ value is the typical delay value that the designer expects the gate to have.
◦ Max value
◦ The max value is the maximum delay value that the designer expects the gate to have.

Dr. Jisha P BMSCE 80

Examples: min, typ, and max value specification

// Two delays
◦ Min, Max, and Typical Delay Values
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// One delay // if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
// if +mindelays, delay= 4
and #(3:4:5, 5:6:7) a2(out, i1, i2);
// if +typdelays, delay= 5
// Three delays
// if +maxdelays, delay= 6
// if +mindelays, rise= 2 fall= 3 turn-off = 4
and #(4:5:6) a1(out, i1, i2); // if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);
Dr. Jisha P BMSCE 81
 Delay Example
◦ A simple module called D implements the
following logic equations:
◦ out = (a . b) + c
◦ The gate-level implementation is shown in
Module D.
◦ The module contains two gates with delays
of 5 and 4 time units.

Dr. Jisha P BMSCE 82

Eg1: Verilog Definition for Module D with Delay
// Stimulus (top-level module)
module D (out, a, b, c); module stimulus;
output out;//I/O port declarations // Declare variables
reg A, B, C;
input a,b,c; wire OUT;
wire e; // Internal nets // Instantiate the module D
D d1( OUT, A, B, C);
// Instantiate primitive gates // Stimulate the inputs.
to build the circuit //Finish the simulation at 40 time
units.
and #(5) a1(e, a, b); initial
//Delay of 5 on gate a1 begin
A= 1'b0; B= 1'b0; C= 1'b0;
or #(4) o1(out, e,c); #10 A= 1'b1; B= 1'b1; C= 1'b1;
//Delay of 4 on gate o1 #10 A= 1'b1; B= 1'b0; C= 1'b0;
#20 $finish;
endmodule end
Dr. Jisha P
endmodule
BMSCE 83
Waveforms for Delay Simulation
Simulation time at each transition
is specified below the transition.

1. The outputs E and OUT are

initially unknown.
2. At time 10, after A, B, and C
all transition to 1, OUT
transitions to 1 after a delay
of 4 time units and E changes
value to 1 after 5 time units.
3. At time 20, B and C transition
to 0. E changes value to 0
after 5 time units, and OUT
transitions to 0, 4 time units
after E changes.
Dr. Jisha P BMSCE 84
Waveforms for Delay Simulation

Dr. Jisha P BMSCE 85

Example 2: Deduce the design block for the given Verilog code and draw the
waveforms for the stimulus given:
module stimulus;
module sr latch(q, qbar, s, r, ck); 10 reg s, r, ck=1’b0;
output q, qbar; wire q, qbar;
sr latch uut (q, qbar, s, r, ck);
input s, r, ck;
always #10 ck = ∼ck;
wire sbar, rbar; initial
nand #5 U0 (sbar, s, ck); begin
nand #5 U1 (rbar, r, ck); s = 1’b1; r = 1’b0;
nand #5 U2 (q, sbar, qbar); #25 s = 1’b0; r = 1’b0;
#20 s = 1’b1; r = 1’b1;
nand #5 U3 (qbar, rbar, q);
#20 s = 1’b0; r = 1’b1;
endmodule #20 $finish;
end
endmodule
Dr. Jisha P BMSCE 86
Answer:
◦ The provided Verilog code implements an SR latch with clock using NAND gates.
◦ Let’s break down the design block and analyze its behavior.
◦ Design Analysis of SR Latch Module:
◦ Inputs: s (Set), r (Reset), ck (Clock)
◦ Outputs: q, qbar (complement of q)
◦ Internal Wires: sbar, rbar
◦ Working:sbar and rbar are generated by nand gates (U0 and U1), where:
◦ sbar is the NAND of s and ck
◦ rbar is the NAND of r and ck
◦ q and qbar are determined by nand gates (U2 and U3), forming the cross-coupled latch:
◦ q is the NAND of sbar and qbar
◦ qbar is the NAND of rbar and q
◦ Timing:Each NAND gate has a delay of 5 time units.

Dr. Jisha P BMSCE 87

Dr. Jisha P BMSCE 88
 Analysis:
◦ Initial Conditions:
◦ ck toggles every 10 time units (#10 ck = ~ck).
◦ Initial Inputs: s = 1, r = 0
◦ Stimulus Sequence:
◦ At t = 0: s = 1, r = 0 (Set condition)
◦ At t = 25: s = 0, r = 0 (Hold condition)
◦ At t = 45: s = 1, r = 1 (Invalid condition, both set and reset are 1)
◦ At t = 65: s = 0, r = 1 (Reset condition)Simulation ends at t = 85.

Dr. Jisha P BMSCE 89

 Analysis:
◦ Expected Behavior of the SR Latch
◦ The behavior can be summarized as follows:
◦ Set Condition (s = 1, r = 0): q should become 1 and qbar should become
0.
◦ Reset Condition (s = 0, r = 1): q should become 0 and qbar should
become 1.
◦ Hold Condition (s = 0, r = 0): The latch retains its previous state.
◦ Invalid Condition (s = 1, r = 1): This condition is typically avoided as it
leads to an undefined state.

Dr. Jisha P BMSCE 90

Waveforms :

Dr. Jisha P BMSCE 91

Eg:- Decoder gate level model

◦ Decoder

◦ This Decoder is a combinational logic circuit, and its purpose is to decode the data given
to it. It is made of n number of input lines and 2n output lines.

◦ For every probable input condition, there are various output signals and depending on the
input.

◦ Need of Decoder: Memory Addressing, Seven-Segment Displays, Control Systems

 Decoder - 2 to 4 line decoder:
◦ In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs, i.e., Y0, Y1, Y2,
and Y3.

◦ For each combination of inputs, when the enable 'E' is set to 1, one of these four outputs will be 1.
 Decoder - 2 to 4 line decoder:
◦ The logical expression and circuit of the term Y0, Y0, Y2, and Y3 is as follows:
Decoder - 2 to 4 line decoder: gate level
module decoder24_gate(en,a,b,y); // declare input and output ports
input en,a,b;
output [3:0]y;
wire na,nb; // supportive connections required to connect nand gates
// instantiate 4 nand gates and 3 not gates
not n1(na,a);
not n2(nb,b);
nand n3(y[0],en,na,nb);
nand n4(y[1],en,na,b);
nand n5(y[2],en,a,nb);
nand n6(y[3],en,a,b);
endmodule
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Decoder - 2 to 4 line decoder: TB
module tb;
reg a,b,en; // input port are declared in reg(register)
wire [3:0]y; // output port are declared in wire(net)
decoder24_gate dut(en,a,b,y); // instantiate design block
initial
begin
en=0;a=1'bx;b=1'bx;#5
en=1;a=0;b=0;#5
en=1;a=0;b=1;#5
en=1;a=1;b=0;#5
en=1;a=1;b=1;#5
$finish; // terminate simulation using $finish system task
end
endmodule Dr. Jisha P BMSCE 96
Simulation output & Schematic

Dr. Jisha P BMSCE 97

 Decoder - 3 to 8 line decoder:
◦ The 3 to 8 line decoder is also
known as Binary to Octal
Decoder.
◦ In a 3 to 8 line decoder, there is a
total of 8 outputs, i.e., Y0, Y1,
Y2, Y3, Y4, Y5, Y6, and Y7 and 3
inputs, i.e., A0, A1, and A2.
◦ This circuit has an enable input
'E’.
◦ Just like 2 to 4 line decoder, when
enable 'E' is set to 1, one of these
8 outputs will be 1.
◦ The block diagram and the truth
table of the 3 to 8 line encoder
are given below.
Decoder - 3 to 8 line decoder:
The logical expression of the term Y0,
Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Decoder –
3 to 8 line decoder:
◦Logical circuit of the above
expressions is given :
a) Structural modelling (gate level): Decoder
module decoder( input E,a2,a1,a0, module tb;
output [7:0]Y ); wire [7:0]Y;
not(a2n,a2); reg E,a2,a1,a0;
not(a1n,a1); decoder A1(E,a2,a1,a0,Y);
not(a0n,a0); initial begin
and(Y[0],a2n,a1n,a0n,E); E=1;a2=0;a1=0;a0=0;
and(Y[1],a2n,a1n,a0,E); #5 E=1;a2=0;a1=0;a0=1;
and(Y[2],a2n,a1,a0n,E); #5 E=1;a2=0;a1=1;a0=0;
and(Y[3],a2n,a1,a0,E); #5 E=1;a2=0;a1=1;a0=1;
and(Y[4],a2,a1n,a0n,E); #5 E=1;a2=1;a1=0;a0=0;
and(Y[5],a2,a1n,a0,E); #5 E=1;a2=1;a1=0;a0=1;
and(Y[6],a2,a1,a0n,E); #5 E=1;a2=1;a1=1;a0=0;
and(Y[7],a2,a1,a0,E); #5 E=1;a2=1;a1=1;a0=1;
endmodule #15 $finish;
end
endmodule
b) Data Flow modelling: Decoder
module decoder( input E,a2,a1,a0, output [7:0]Y);
assign Y[0]=((~a2)&(~a1)&(~a0)&E);
assign Y[1]=((~a2)&(~a1)&(a0)&E);
assign Y[2]=((~a2)&(a1)&(~a0)&E);
assign Y[3]=((~a2)&(a1)&(a0)&E);
assign Y[4]=((a2)&(~a1)&(~a0)&E);
assign Y[5]=((a2)&(~a1)&(a0)&E);
assign Y[6]=((a2)&(a1)&(~a0)&E);
assign Y[7]=((a2)&(a1)&(a0)&E);
endmodule
c) Behavioral Modelling: Decoder
module decoder( input E,a2,a1,a0, output reg [7:0]Y);
always@(E,a2,a1,a0)
if(E==1)
case({a2,a1,a0})
3'b000:Y=8'd1;
3'b001:Y=8'd2;
3'b010:Y=8'd4;
3'b011:Y=8'd8;
3'b100:Y=8'd16;
3'b101:Y=8'd32;
3'b110:Y=8'd64;
3'b111:Y=8'd128;
default:Y=1'b0;
endcase
endmodule
Simulation Output
Schematic
3 to 8 line decoder using 2 to 4 decoder:

106
Dr. Jisha P BMSCE
Verilog code
module decoder_3to8 ( input A2, A1, A0, // 2-to-4 Decoder Module
output [7:0] Y ); module decoder_2to4 (
wire E1, E2;
input A1, A0, E,
assign E1 = A2; output [3:0] Y);
assign E2 = ~A2;
assign Y[0] = E & ~A1 &~A0;
// Instantiating two 2-to-4 decoders assign Y[1] = E & ~A1 & A0;
decoder_2to4 dec1 (.A1(A1), .A0(A0), .E(E1), .Y(Y[7:4])); assign Y[2] = E & A1 & ~A0;
assign Y[3] = E & A1 & A0;
decoder_2to4 dec2 (.A1(A1), .A0(A0), .E(E2), .Y(Y[3:0]));

endmodule endmodule
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Verilog code
module testbench;
reg A2, A1, A0;
wire [7:0] Y;
// Instantiate the 3-to-8 decoder
decoder_3to8 uut ( .A2(A2), .A1(A1), .A0(A0), .Y(Y) );
initial
begin
// Test each input combination
A2 = 0; A1 = 0; A0 = 0; #10;
A2 = 0; A1 = 0; A0 = 1; #10;
A2 = 0; A1 = 1; A0 = 0; #10;
A2 = 0; A1 = 1; A0 = 1; #10;
A2 = 1; A1 = 0; A0 = 0; #10;
A2 = 1; A1 = 0; A0 = 1; #10;
A2 = 1; A1 = 1; A0 = 0; #10;
A2 = 1; A1 = 1; A0 = 1; #10;
$finish;
end
endmodule
Dr. Jisha P BMSCE 108
Simulation output & Schematic

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BMSCE