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MAE 95-01 SENSOR INTERFACE PROCESSOR (SIF-P)

PRODUCT DATA

CONTENTS

Page

1. SUMMARY OF OPERATION 1

2. HARDWARE DESCRIPTION 1

3. SOFTWARE 2

4. HARDWARE DETAIL 3

5. PHYSICAL ARRANGEMENT 8

6. APPENDIX 1 CONNECTOR DETAILS 9

7. APPENDIX 2 EXTERNAL WIRING 11

This Document Is Sourced From MAE 95-01/SIF_P.PD/A1

Issue A © 1999 ALSTOM Controls Ltd.

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1. SUMMARY OF OPERATION
The SIF_P board provides the interface for 10 Analogue inputs with a resolution of 12
bits [11 bits plus sign]. Analogue to Digital converters convert each analogue input in
sequence into digital form, the processor generates a message in the defined format
to transfer the data over the serial link to the host.

A ribbon cable bus interface provides the facility to link to a companion Digital I/O
board, SIF_D. MAE 95-02.

Key functions on this and associated boards are:-

• Embedded Processor board, scanning the I/O and communicating as a master

or slave with a host over a serial link.

• The serial port has galvanically isolated RS485 and RS232 interfaces in the
same 9 way D type connector.

• 10 x 12 bit Analogue inputs, differential, +/- 10 Volts.

• One pulse count input channel, unidirectional, with differential input amp.

• 24 Volt supply.

• Display output port compatible with Hitachi/Toshiba Liquid Crystal Display.

• Bus connector to support up to 8 I/O boards.

• Generates a variable mark/space waveform, to control lamp dimming for the

LCD backlight and for lamp dimming on the supplementary Digital I/O board.

The PCB is designated as SIF_P.

The size of the board is 3U high(100mm) x 180mm deep, normally mounted on 4

studs, but can be mounted in a rack.

2. HARDWARE DESCRIPTION
The PCB is a processor based interface which scans 10 external analogue inputs in
sequence, converts the inputs into digital form with 11 bits plus sign resolution and
sends the data over a serial link running at 19.2kbits/sec to a host processing system.

The host, in most Marine applications, will be a Terminal server connected to a SPARC
based workstation via the SCSI port.

The serial link S/W protocol is specific to this application, however, alternative S/W
protocols could be included in the firmware to provide a link to another Comms
system viz. GEM80/400, Alspa 8035, 8075 etc.

A single supply, 24 volts, provides the required on-board supplies by using DC-DC
Converters mounted on the PCB.

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2.1 EXTERNAL INTERFACE

The serial port supports both RS232 for local connection and RS485 for remote use,
point to point or multidrop.

An on-board header provides a connection for a 2 line x 16 character Liquid Crystal

Display using the standard connections and software protocol adopted by several
manufacturers viz. Hitachi, Densitron, Sanyo etc., with support for an LED backlight,
with control of the brightness.

A backplane connector provides a parallel bus link to companion I/O boards. A 16

way 24 Volt digital I/O board, SIF_D, being the only one available at present.

3. SOFTWARE
The Host message content defines when digital I/O is present, when true, lamp
dimming is required. The value of analogue input A0 is used to determine the
mark/space ratio of the pulse train sent down the Ribbon or Backplane bus to all SIF-
D boards. Zero volts input to A0 produces min brightness, +5V input to A0 produces
maximum brightness.

Any SIF-P which is a slave monitors incoming messages from the Host and raises a
SIF-P watchdog alarm if the Host does not address it for a period exceeding 8
seconds. The Host will normally address each SIF-P at least four times per second.

When a SIF-P watchdog alarm is raised the SIF watchdog buzzer (output bit 0 on SIF-
D address 0) and the SIF watchdog lamp (output bit 1 on SIF-D address 0) should
both be set, with the WD lamp flashing. When the silence button (input bit 1 on SIF-D
address 0) is next set the buzzer should be cancelled. The SIF-D WD alarm lamp
remains on (not flashing) until the Host establishes reliable contact with the SIF-P
again.

Lamp Test. While the lamp test button is set (input bit 0 of SIF-D address 0) all outputs
(LCD, lamps and buzzers) are set, a sequential procedure is utilised to avoid
overloading the lamp power supply, to allow both buzzers to be heard and utilise all
functions of the LCD. While lamp test is depressed the analogue and digital input
signals continue to be updated on the serial link. The output signals are overwritten or
ignored.

The input data to the SIF-P is assembled as an output messages with updated digital
and analogue values and transmitted immediately after receiving a message from the
Host.

The digital data received from the Host, is passed without modification to the SIF-D
units.

The data update rate for the SIF_P to Host processor, is 5Hz.

Digital inputs to the Host processor via the serial link are masked by the Enable button
which is located at B2 of SIF_D address 0.

Each lamp has three states in addition to the lamp test previously defined. The serial
message from the Host contains information for steady and flashing lamps states. The
SIF_P must flash the lamps at a rate of 0.5 seconds on, 0.5 seconds off in accordance
with the following truth table, overleaf.

© 1999 ALSTOM Controls Ltd. Issue A

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BIT IN ON WORD BIT IN FLASHING WORD LAMP STATE

0 0 OFF
1 0 ON
0 1 FLASHING
1 1 FLASHING

Analogue inputs can be of two types:-

a) A potentiometer which uses the +/- 5 Volt Pot reference supplies, sourced from
the SIF_P. These inputs are multiplied by 2048 and then divided by the
measured Pot reference supply [+/-]. This removes the requirement for
accurate Pot reference supplies.

b) An externally powered voltage source.

Input is scaled to be ±2048 when the signal is ±10 Volts.

Frequency is to be scaled

0/500Hz 0/500

The frequency will be obtained by counting the pulses over a one second period,
giving a resolution of 1 Hz, the fresh value will be calculated once per second.

4. HARDWARE DETAIL
4.1 PROCESSOR, RAM, ROM, ADDRESS SELECT

4.1.1 Processor

The processor used is a 80C51FA in a PLCC package.

The clock for the processor uses a 11.05920MHz crystal, selected as a convenient
frequency for the internal UART to communicate at 19.2kbps

4.1.2 RAM

The PCB has been tracked to incorporate a 62256, 32kbyte static RAM.

It will be assembled using a 6264, 8kbyte static RAM.

4.1.3 ROM

The PCB has been tracked for a 28F010, 128kbytes Flash PROM.

It is fitted with a 28F256, 32kbytes Flash PROM.

No on-board programming facility for the Flash PROM has been provided.

4.1.4 Address Select

A 16 way Hex switch, SW1, Address select, provides the facility to individually address
up to 16 SIF_P processor boards in a multidrop link.

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4.2 BUS INTERFACE

A BUS interface is provided to interface to supplementary I/O boards.

It is based on a half size DIN41612, with rows a and c loaded, a1 - a16 and c1 -
c16.

Two or three boards can be linked using a 32 way ribbon cable or, for larger systems,
a PCB backplane, SIF_BP, MAE 95-03, has been designed, where the SIP_P supports
up to 8 SIF_D Digital I/O boards.

2 x SIF_BP Backplanes will mount in one 19" rack, giving the facility of 256 bits of 24
Volt digital I/O in one 3U high rack.

The bus lines are defined as follows:

8 bit bi-directional data bus, BAD0 - BAD7,

8 active low Board select lines, NBS0 - NBS7,

2 latched Address lines, BA0 - BA1,

2 active low control lines, BRD/, BWR/,

1 lamp dimming control line, variable Mark/space, BPWM.

+/- 5 Volt supplies.

24 Volt Power

4.2.1 Lamp Brightness Control

A lamp brightness control facility is provided for both the Digital I/O boards and for
the LCD backlight.

The processor generates a variable Mark to Space ratio signal, PWM, the period being
defined by AIP0, only when in the slave mode. The resolution of the PWM is 8 bits, i.e.
256, with a minimum value of 1/256 and a maximum of 255/256.

The PWM signal on the SIF_D, digital I/O board, determines the ON/OFF time for the
output lamp drivers.

4.3 ANALOG INPUTS

The Analogue inputs are connected by means of a 26 way ribbon cable header
mounted on the front edge of the board.

This connector also provides reference supplies for the potentiometer inputs, viz.
Joystick, Amplitude, Turning moment etc.

There 13 Analogue inputs, AIP0 - AIP12, of which 11 are available as external

connections

AIP10 is the + Pot Reference PREF+ Not available as an external input

AIP11 is the - Pot Reference PREF- Not available as an external input

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AIP12, although input to the A/D converter is normally used as a pulse count input to
determine the frequency of an input waveform.

4.3.1 Input Differential Amps

All external Analogue inputs, AIP0 - AIP9 and AIP12, are buffered by differential
amplifiers.

The input sensitivity is nominally +/-10V with an input impedance of 260k.

The input networks, by reasons of availability of suitable surface mount components

and cost, are based on 1% components, resulting in a +/-1% gain spread.

The A/D converter has a resolution of 11 bits plus sign.

Analogue input channels 0 - 3 have differential and common mode 10mS input filters

The remainder of the analogue input channels have 100uS filters.

Protection diodes at the front end of the amplifiers, provide no damage protection up
to in excess of +/- 110 volts.

AIP12 is the Pulse train input PTR+, PTR-

This input is connected to one of the A/D converters to be used as a normal analogue
input.

It is also connected to a comparator to produce a zero crossing detection which is

input to one of the interrupt ports of the processor.

4.3.2 A - D Conversion.

Two x 8 I/P, 12 bit, Serial Analogue to Digital converters with sample and hold are
fitted, to provide the facility to sample two input channels at the same time, a
requirement for Synchro or resolver inputs.

A mean of several successive conversions is passed to the host to reduce the effect of
random noise pick-up.

4.3.3 Synchro Inputs

Two Synchros are catered for, with Synchro 1 using AIP6 and AIP7 for its stator inputs
and Synchro 2 using AIP4 and AIP5 for its stator inputs.

When Synchro mode is selected, AIP4 - 7 are sampled at specific times dependant on
the synchro reference inputs.

The two Synchro rotor / reference inputs REF1, REF2 are input to the A/D converters,
REF1 to AIP8 and REF2 to AIP9, as normal Analogue inputs and are also input to
comparators to give zero crossing detection for the inputs which are fed to interrupt
ports on the processor.

A ↑ transition, interrupts the processor, starts an internal counter, which continues until
the input goes low,↓. The value stored in the counter is the period of the positive half
cycle of the reference waveform. Dividing this value by 2, gives the point for the next
positive half cycle where the reference is at a peak.

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For the best resolution, the stator inputs, S1 to S2 and S3 to S2 are sampled at this
time, S1 to S2 is input to A/D Conv 0 and S3 to S2 is input to A/D Conv 1.

V[s3-s2] = VR.sinωt.sinθ V[s1-s2] = -VR.sinωt.sin(θ+120)

Note: The math for conversion to the angle θ is carried out in the host processor,
SPARC or similar.

4.3.4 A/D Converter References

The A/D converters require accurate positive and negative reference voltages.

A Linear Technology LT1004, IC19, is used for the positive reference, buffered by a
voltage follower, IC23A, produces a VR+ = 1.235V. An amplifier, IC23B, with a gain
of -1 using 0.1% resistors provides a negative reference = -1.235V +/- 0.001V.

4.3.5 Potentiometer References

Two supplies, PREF+ and PREF-, nominally +5V and -5V, are provided for the input
potentiometers.

There is no adjustment on these supplies and they may vary from board to board, or
over a period of time.

PREF+ and PREF- are input to the A/D converter as AIP10 and AIP11, giving accurate
values for the Pot references.

The actual value read from the pot is divided by AIP10 if positive or by AIP11 if
negative, giving a ratio equal to 1.00 for maximum setting. The ratio is then multiplied
by +/- 2048 giving a value which is not dependant on the actual pot reference
supply.

This is defined as Ratio mode of operation.

4.3.6 Analogue Input Modes

A 16 way Hex rotary switch, SW2, provides the facility for selecting the mode of
operation of the board, as listed in the table below.

Switch Position Master/Slave Synchro 1 Synchro 2 Analogue I/P Type

0 Slave Absent Absent Absolute
1 Slave Absent Absent Ratio
2 Slave Absent Present Absolute
3 Slave Absent Present Ratio
4 Slave Present Absent Absolute
5 Slave Present Absent Ratio
6 Slave Present Present Absolute
7 Slave Present Present Ratio
8 Master Absent Absent Absolute
9 Master Absent Absent Ratio
A Master Absent Present Absolute
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Switch Position Master/Slave Synchro 1 Synchro 2 Analogue I/P Type

B Master Absent Present Ratio
C Master Present Absent Absolute
D Master Present Absent Ratio
E Master Present Present Absolute
F Master Present Present Ratio

4.3.7 PTR Input

The wind speed signal from a Munro anemometer is produced by an ac generator

with increasing voltage and increasing frequency with increasing wind velocity.

The wind speed is input to the PTR+ and PTR- as a differential input with both
common mode and differential mode filtering. The output of the differential amp is
connected to a comparator to provide a zero crossing digital input to one of the
interrupt inputs, P1.0, of the processor.

The frequency of the input signal is determined by counting the number of positive
edges in one second.

The output of the differential amp is also connected to the A/D converter as AIP12, for
use in other applications as conventional analogue input.

4.4 SERIAL LINK

The Processor includes a built in UART with programmable Baud rate. For this
application, the Baud rate is fixed at 19.2kbps.

A second unregulated DC-DC Converter, converts the 24 Volts supply to isolated +/-5
Volt supplies for the serial interface. +5VI and -5VI.

The serial link interface is opto isolated.

IC26, SN75155, running from the +/- 5VI, provides the RS232 transmit and RS232
receive interface. The minimum spec for RS232 levels is +/- 3V.

Two separate LTC485, RS485 transceivers are utilised, IC24 for RS485 receive and
IC25 for RS485 transmit.

The RS485 receive lines, RXA and RXB and the transmit lines , TXA and TXB, are
biased to a logic 1 or mark condition, with RXA = Hi, RXB = Lo, TXA = Hi and TXB =
Lo. Connecting or disconnecting the serial link connector leaves the lines in a logic 1,
or mark condition.

Receive data is a logical OR of the RS232 and RS485 receive data with no links
required.

RS232 transmit data is permanently enabled, RS485 data is controlled by the Transmit
enable generated by the processor. For a point to point link, it is enabled
permanently, for a multidrop link it is enabled only when the Master instructs the
interface to transfer data to the host.

Two green LED’s driven by pulse stretching mono-stables, IC34A and IC34B , indicate
serial link activity on the transmit port and the receive port.
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4.5 LIQUID CRYSTAL DISPLAY LCD

A 16 way header provides connection using ribbon cable, to a separate 2 line x 16

character Hitachi/Toshiba Liquid Crystal Display.

4.5.1 LCD Backlight

The display specified, is fitted with an LED backlight assembly, rated at 4.2V, 168mA.

The backlight runs from the -5V supply as the normal loading on this supply is low.

Control of the brightness of the backlight is required.

The PWM signal is filtered to produce a mean level between 0V and +5V.

0V produces zero current through the backlight and +5V produces 160mA for
maximum brightness.

4.6 POWER SUPPLY

The power input for the PCB is nominally + 24v +/- 10%

An XP BX3 DC - DC Converter produces +/- 5 volts.

The + 5 volts is for the processor and the logic on the board and with further filtering
for the analogue circuitry.

The - 5 volts is used for the analogue circuitry and for the LCD Backlight.

A second DC - DC converter fed from the 24 volts supply produces +/- 5 volts
isolated supply for the Serial link, RS232 and RS485.

The estimated load current for the board is 150mA at 24 volts

4.7 RELIABILITY

The MTBF for the module has been calculated as = 86,580 Hours

4.8 EXTERNAL SPECIFICATION COMPATIBILITY

Temperature The board will operate from 0 °C to 70 °C.

Mil 167 approval All steps necessary will be taken to ensure that the interface
board meets Mil 167 and Lloyd's approval. e.g. operational
temperature ranges, construction, etc.

5. PHYSICAL ARRANGEMENT
The PCB is normally mounted on a metal backplate by four x 3mm PCB mounting
spacers.

One SIF_P links to one SIF_D using a ribbon cable.

For larger systems, where the SIF_P processor board links to more than 1 Digital I/O
board, the boards will mount in a 3U high rack.

A PCB backplane, SIF_BP [MAE 95-03] will link one SIF_P to up to 8 SIF_Ds.

© 1999 ALSTOM Controls Ltd. Issue A

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TR1
IC11
IC10
REF 1,2 IC22
IC7

IC12

IC17 IC1
PL3 ANIP 4,5 ANIP 6,7
PL1
IC9 IC5

IC18 SW1 IC2

ANIP 1,2 ANIP 2,3
IC8
IC4
SW2
IC23
IC19
IC26 IC32
SK1 IC31
IC33 P
IC3 IC28
L
IC6 TB1
IC30 2
IC25 IC27

IC34
IC24 IC29

FIGURE 1 COMPONENT LAYOUT

6. APPENDIX 1 CONNECTOR DETAILS

180mm

PL3
PL1
SIF-P
PROCESSOR BOARD

100mm

SK1

TB1

0.2in 0.2in

0.2in 0.2in

FIGURE 2 PCB OUTLINE AND DIMENSIONS

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6.1 TB1 POWER INPUT

2 way Phoenix/Klippon Terminal block

PIN I/P FUNCTION

1 V+ 24 Volt Supply
2 GND 0 Volt return

6.2 SK1 SERIAL LINK

9 Way D Type Connector 90° PCB Socket

Pin out identical to GEM80/400 Serial ports

PIN 0/P FUNCTION PIN O/P FUNCTION

1 RXA RS485 RX+ 2 RXD RS232 RXD
3 TXD RS232 TXD 4 RXB RS485 RX-
5 CMN 0VI Common 6 TXA RS485 TX+
7 RT+ 1k Pull up to 5VI 8 RT- 1k Pull down to 0VI
9 TXB RS485 TX-

6.3 PL1 BUS CONNECTOR TO DIGITAL I/O MODULES

32 way DIN 41612 C/2 connector A and C rows

PIN I/O FUNCTION PIN I/O FUNCTION

A1 BRD/ Bus Read Active Lo C1 +5V +5 Volt logic supply
A2 BWR/ Bus Write Active Lo C2 +5V +5 Volt logic supply
A3 BPWM Pulse Width Mod C3 0V 0 Volt logic
Lamp brightness control
A4 BA0 Bus Address A0 C4 0V 0 Volt logic
A5 BA1 Bus Address A1 C5 0V 0 Volt logic
A6 NBS0 I/O Board Select 0 C6 NBS1 I/O Board Select 1
A7 NBS2 I/O Board Select 2 C7 NBS3 I/O Board Select 3
A8 NBS4 I/O Board Select 4 C8 NBS5 I/O Board Select 5
A9 NBS6 I/O Board Select 6 C9 NBS7 I/O Board Select 7
A10 -5VA -5Volt Analogue Supply C10 0V 0 Volt logic
A11 BAD0 Bus Address/Data Bit 0 C11 BAD1 Bus Address/Data Bit 1
A12 BAD2 Bus Address/Data Bit 2 C12 BAD3 Bus Address/Data Bit 3
A13 BAD4 Bus Address/Data Bit 4 C13 BAD5 Bus Address/Data Bit 5
A14 BAD6 Bus Address/Data Bit 6 C14 BAD7 Bus Address/Data Bit 7
A15 +24V +24V Power distribution C15 0VP 0 Volt Power
A16 +24V +24V Power distribution C16 0VP 0 Volt Power

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6.4 PL2 LCD DISPLAY PANEL

16 Way Header Connects to LCD panel

PIN 0/P FUNCTION PIN O/P FUNCTION

1 0V 0 Volt Supply 2 +5V 5 Volt Supply
3 VO Viewing angle 4 LRS Data - Control/
5 LRD Read - Write/ 6 LE Enable
7 LAD0 Data/Address Bit 0 8 LAD1 Data/Address Bit 1
9 LAD2 Data/Address Bit 2 10 LAD3 Data/Address Bit 3
11 LAD4 Data/Address Bit 4 12 LAD5 Data/Address Bit 5
13 LAD6 Data/Address Bit 6 14 LAD7 Data/Address Bit 7
15 BLC- Backlight Control - 16 BLC+ Backlight Control +

6.5 PL3 ANALOGUE INPUTS

26 way IDC Header

PIN I/O FUNCTION PIN I/O FUNCTION

1 AIP0+ Analogue Input 0+ 2 AIP0- Analogue Input 0-
3 AIP1+ Analogue Input 1+ 4 AIP1- Analogue Input 1-
5 AIP2+ Analogue Input 2+ 6 AIP2- Analogue Input 2-
7 AIP3+ Analogue Input 3+ 8 AIP3- Analogue Input 3-
9 AIP4+ Analogue Input 4+ 10 AIP4- Analogue Input 4-
11 AIP5+ Analogue Input 5+ 12 AIP5- Analogue Input 5-
13 AIP6+ Analogue Input 6+ 14 AIP6- Analogue Input 6-
15 AIP7+ Analogue input 7+ 16 AIP7- Analogue Input 7-
17 REF1+ Synchro Reference 1+ 18 REF1- Synchro reference 1-
Analogue Input 8+ Analogue Input 8-
19 REF2+ Synchro Reference 2+ 20 REF2- Synchro reference 2-
Analogue Input 9+ Analogue Input 9-
21 PTR+ Pulse train + 22 PTR- Pulse Train -
Analogue Input 12+ Analogue Input 12-
23 0VA Analogue 0 Volts 24 0VA Analogue 0 Volts
25 PREF+ Pot Reference Supply + 26 PREF- Pot Reference Supply -

7. APPENDIX 2 EXTERNAL WIRING

Analogue Inputs

The cable between the SIF_P processor and plant wiring is specified as a 26 way
ribbon cable which connects to either a SIF_AT analogue termination panel in the
Sensor junction box, or to a marshalling board for use in the Console nose, or to
standard Ribbon Interface units.

The connectors for each end of the cable are 26 way D type Insulation displacement
Connectors IDC socket.

Farnell Components stock No 249-002.

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Serial Link

The 9 way D type connector caters for both RS232 and RS485 interfaces.

The cable to be used for the RS485 link, should be two twisted pairs, each individually
screened, with an overall braid screen. By reason of common mode limitations of the
RS485 drivers and receivers, the 0V at each node on the link, should be connected
together, using another core in the cable.

The RS232 interface is to be used only for local connection. The same cable, defined
in the previous paragraph could be used. Alternatively a three core cable, with an
overall screen would be acceptable.

COPYRIGHT

This document is copyright and confidential © 1999 ALSTOM Controls Ltd.

It must not be disclosed outside ALSTOM Controls Ltd without written permission from
the Design Authority.

© 1999 ALSTOM Controls Ltd. Issue A