International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 08 Issue: 04 | Apr 2021 www.irjet.net p-ISSN: 2395-0072

Design of 4*4 SRAM using Cadence Virtuoso in 90nm Technology

V.JEYARAMYA1, D.GURUPANDI2, RICHARD R3, REKAN KUMAR S4

1Associate Professor: V.Jeyaramya, Dept. of ECE, Panimalar Institute of Technology,Chennai

2Assistant Professor: D.Gurupandi, Dept. of ECE, Panimalar Institute of Technology,Chennai
3Student, Dept. of ECE, Panimalar Institute of Technology,Chennai
4Student, Dept.of ECE, Panimalar Institute of Technology,Chennai

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Abstract: With the demands of upcoming technologies, An attempt to analyze the performance of NAND and
further more the difficulties of nanometer-era of VLSI NOR gate based on CMOS technology is done. Result shows
designs and logics require new advanced logic strategies NAND gate dissipates 55.73% lesser static power, less area
and styles that are in the meantime elite, high performance, and less access time [3]. A 6T SRAM has been designed for low
power application in 180 nm and 90 nm technologies. It is
energy efficient and robust and immune to noise and
observed as scaling down occurs the dynamic power, current,
variation. SRAM circuits are comprehensively used to plan
rise time, fall time and area reduces [4]. It is found that leakage
high end circuits that result in good performance, because of of a transistor is responsible for more than 40% of power
their speed. Then again, the key negative mark of this circuit dissipation occurs in the circuit. Va rious power reduction
is high vulnerability to noise. The principle reason behind techniques like Self-Vo ltage Controller circuit, Transistor
this is the sub-threshold leakage current coursing through Stacking, and Supply Vo ltage Reduction, have been
the NMOS network of the designed system. With persistent implemented. It has been observed that as voltage increases,
innovation scaling, this issue is getting increasingly serious. the proportionate increase in leakage current occurs [5]. A 16
Another noise tolerant circuit method is proposed. In the Kbit memory has been designed that operates at the frequency
proposed work, we have upgraded the conduct of the SRAM. of 1.24 GHz. For cell arrays , sleep controller and power cut-off
The proposed method provides advantage in terms of delay during standby mode for low leakage current are used.
and power. This postulation portrays the new low power, Programmable timing control circuit is used to mitigate the
noise tolerant method presents a correlation aftereffect of delay variation [6]. It also focused on energy analysis of SRAM
this logic with already existing method. Simulation results with multi-threshold to reduce power dissipation and improve
demonstrate that, in 180 nm CMOS technology when we performance. For reducing leakage current high threshold is
utilize proposed 8T SRAM, it could accomplish minimum required for cross coupled latch and access transistor. With
level of delay. Moreover, the logic also works productively optimum device combination energy efficiency improved by
with all the circuits. Atlast we infer that, the proposed 6.24 times whereas, optimum device combination along with
scheme contributes an extremely productive is not just performance boosting and power reduction technique shows
33 times improvement of energy efficiency [7]. Transistor
noise tolerant, yet in addition energy efficient and high
sizing has the very crucial role for a read or write operation to
speed.
be stable [8]. Dual threshold 7T SRAM cell is proposed and
compared with the standard 6T SRAM cell. It analyses the basis
Keywords: SRAM, DRC, LVS, RCX, Delay, Rise time, Fall time,
of read delay, write delay, leakage power consumption and
Power dissipation. Static Noise Margin in all the three (hold, read and write) mode
of operation. Single bit line is used to reduce the access time for
read and write operation. The leakage power consumption and
I. INTRODUCTION
write delay are reduced by 61.50% and 66.67% respectively
[9].
It is very challenging to design electronic gadgets with very The detailed analysis of 6T, 7T, and 8T SRAM cell with
efficient working and consume the least power. Major issues respect to various electrical para meters is carried out. It
that persuade the necessity of low power design are the observes the variation of dynamic power, static power
increase of different kind of electronic gadgets viz. smart card, dissipation and delay with supply voltage. Also an effort has
audio video supported multimedia products, wireless device been made to analyse the variation of temperature on
etc. These devices and systems need high density, high speed dynamic and static power dissipation. Full custom layout
and low power design [1]. SRAM plays an important role in design has been done successfully for the said SRAM cells and
cache memory of computer, laptop, analog to digital converter, RCX completed successfully.
high speed registers, electronic toys, mobile phone, camera etc. This paper has been organized into following steps: Section I
The SRAM is advantageous as it does not require refreshing enlists a brief introduction of previous work done. Section II has
data until the power is ON. The maximum attainable data a discussion on the operation of various schematic of SRAM
storage capacity of a memory chip approximate ly doubles in cells. Section III shows the Layout and its Av-Extracted view
every two years [2]. Consistent scaling leads to the need of very that may be used for post layout simulation. In Section IV
high density, high performance, low leakage current, less power simulated results are discussed along with tables and graphs.
dissipation with low cost. Section V has the conclusion of the paper.

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 08 Issue: 04 | Apr 2021 www.irjet.net p-ISSN: 2395-0072

Flowchart of Proposed work

simulation and parameters measurement has been carried
out. Layout of schematic is drawn and DRC is checked then
The flowchart in Fig.1 shows the brief description of
LVS matching occurs. Thereafter, RCX test is run for Av-
the work carried out in this paper. 6T, 7T & 8T SRAM cell
Extracted view for parasitic e xt raction.
schematic is designed in Cadence virtuoso.
Further

II. DISCUSS ION ON VARIOUS DES IGNS OF

SRAM CELLS
A. Operation of 6T SRAM

A conventional 6T SRAM memory cell consists of two

inverters cross-coupled to each other along with two access
transistors as shown in Fig.2 [3]. The information is stored at
the two internal nodes P & Q for read and write operation
through access transistor.
For the read operation, first precharge bit line (BL)
and bit line bar (BLB) to VDD and then turn “ON” word line
(WL) to activate NM3 & NM4 so that internal node P & Q make
connections with BL and BLB. During write operation WL
should become high and depend on the initial condition of
nodes P and Q, bit “0 or 1” can be written. At hold state, WL
remains OFF and BL & BLB are left floating.
Failure in read operation is sometimes observed,
caused due to increase in voltage at any of nodes (P or Q) of an
inverter which leads to tripping of another inverter means the
voltage at another node (Q or P) starts falling resulting loss of
information.

Fig. 1 Flowchart of the proposed work

Fig.1 Schematic of 6T SRAM [3]

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The output waveform shown in Fig.3 dictates the

transient analysis and DC analysis of 6T SRAM cell. The
analysis result shows dynamic power and static power 8.69
μW and 18.15 pW respectively.
.

Fig.
4 Transient and DC response of 10T SRAM cell

Fig.2 Transient and DC response of 6T SRAM

The simulations are carried at 1.8 V and the operating

temperature is 27 0C.

B. 10T SRAM memory ce ll

The schematic of 10T SRAM memory cell, shown in Fig. 6

[1], consists of two inverters connected back to back, two
access transistors (NM2 & NM3) and a read buffer, that
consists of two transistors (NM4 & NM 5). During write
operation word line WWL, bit line WBL and WBLB are used
and RWL & RBL are used during read operation.

III. CONCLUS ION

A SRAM was designed using the proposed. The proposed one

after simulation was compared with the simulation results of
the previous proposed logic, which were simulated in same
environment as the proposed logic. The outputs could be seen
from the simulations. The effort has been made to find out area,
delay, fall t ime, rise time, dynamic power, s tatic power, 3 dB
bandwidth for different SRAM cells as shown in Table.2. The
measured results show that static power dissipation is same for
Fig.3 Schematic of 10T SRAM all the SRAM cells considered but dynamic power is least for 6T
SRAM it is highest for 10T SRAM cell with 1.8 V supply voltage
The RBL precharged to VDD and the current flows through the and 0.9 V threshold voltage. The variation of power dissipation
transistor of read buffer, not through the internal nodes. So the and delay has also been observed as a function of supply
internal nodes remain at the same status as they are. The voltage. The effect of temperature variation on power
output waveform in Fig.7 depicts the transient and DC dissipation has also been observed. As observed from Layout,
simulation for 8T SRAM cell along with dissipated power at the area occupied by 6T SRAM cell is minimum and for 10T
room temperature. The result shows that it dissipates 10.55 μW SRAM cell it is maximum..
dynamic power and 18.15 pW static power at the supply voltage
of 1.8 V.

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 08 Issue: 04 | Apr 2021 www.irjet.net p-ISSN: 2395-0072

REFERENCES
❑ Soumitra Pal, et al(2016) “9-T Sram Cell For Reliable
Ultralow-Power Applications And Solving Multibit Soft-
Error Issue”IEEE Transactions On Device And Materials
Reliability.
❑ Dinesh Sangwan, et al(2013)“A study on design and
analysis of SRAM & DRAM” International Journal of
Enhanced Research in Science Technology & Engineering.
❑ Hiroyuki Yamauchi(2017) “A Discussion on SRAM Circuit
Design Trend in Deeper Nanometer-Scale Technologies”
IEEE Transactions On Very Large Scale Integration (VLSI)
Systems
❑ Mukesh Kumar, et al (2017) “ Performance Evaluation of
6T, 7T & 8T SRAM at 180 nm Technology”IEEE-40222.

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