Digital Receiver Technical Specifications
Hardware details:
Receiver Channels (ADC):
Number of input channels: 8
Resolution: 16-bit
Sampling rate: Up to 125 MHz
1 dB compression point: +6 dBm
Peak damage level: +20 dBm
Dynamic range: Up to 110 dB
Intermediate frequency (IF): 5.0 to 100 MHz, typically 60 MHz
Connector type: SMA female, 50 Ohm Impedance
MDS level: -90 dBm.
Transmitter Channels (DAC):
Number of channels: 4 real or 2 complex waveform generators freely programmable
Resolution: 16-bit
Sampling rate: Up to 900 MHz
IF Bandwidth: 10 MHz
Power output level: +3 dBm @60 MHz IF
Connector type: SMA Female, 50 Ohm Impedance
Dedicated Downlink to Signal Processor:
Interface 1:
Serial Tag Angle
Connector type 15 pin SUBD female
Connector label J4
Protocol RS422, 8 bit, 1 Startbit, 1 Stopbit
Baudrate 230400
Pin 6 Data +
Pin 13 Data -
Pin 8 GND
Interface 2
Uplink
Connector type 15 pin SUBD female
Connector label J1
Protocol RS422
Pin 3 Data In +
Pin 11 Data In -
Pin 8 GND
Interface 3
Downlink
Fibre Multimode 850 nm, 50/125 μm, OM3
Connector type LC Simplex
Connector label FO1
GPIO pins for controlling external hardware
Hardware functionality is broadly classified a
1. Waveform Generator
2. Data Acquisition
3. Timing & Control Unit
Hardware functionality:
1.Waveform Generation:
a) Generation of NLFM and Short pulse CW wave forms with configurable
pulse widths and modulation BW. Waveform parameters will be provided via
up-link.
b) Three Pulsing scheme must be implemented details of which will be
communicated in the later stage.
c) Filtering and Digital Up conversion.
d) Interpolation to increase the sampling rate.
e) Digital to Analog Conversion.
f) output analog buffer/signal conditioner.
g) All the DAC channels must be in synchronization.
2.Data Acquisition:
a) Input analog buffer/signal conditioner and limiter
b) Dynamic selection between high and low level channels in based on power
level for each polarization
c) Analog to digital conversion and All 8 ADC channels wit synchronization.
d) Digital down conversion to zero IF
e) Decimation to reduce the sampling rate
f) Filtering
g) Matched filter implementation , Coherent integration, incoherent integration.
Filter coefficients and integration times will be received via up-link.
h) Receive data from encoder for azimuth and elevation
i) Data packing along with Header. Header data format will be intimated in the
later stage
j) Data Multiplexing
k) Data transfer to back end system (Optical Interface)
3. Timing and control signal generation :
a) Hardware Provision to give external LO A 80MHz sine wave reference clock
signal, external Sampling Clock and external reference trigger will be the
input to the Hardware.
b) All the clock need to be generated internally and phase locked to the
reference clock signal.
c) System also should be able to run independently without external reference
clock signal. Proper arrangements should be given in the design.
d) Able to generate the Staggered PRF.
