Lab Series Introduction

To those familiar with conventional Nyquist-rate analogue-to-digital converter (ADC) and

digital-to-analogue converter (DAC) design, Delta-Sigma modulation (DSM) can appear a
somewhat inscrutable data conversion technique when first encountered. It is our
experience that a quick way for beginners to really get a feel for how DS modulators work
and how the relevant theory applies in practice is by hands-on experimenting with real
modulators as they learn. This is the purpose of this course’s laboratories; to use hands-on
experimenting to hopefully make the points covered of the lecture materials clearer and
more meaningful by letting you see them in action. The first 5 laboratories focus on
system-level simulation of some simple modulators to help students make the important
leaps from encountering new theory in the lectures to actually understanding the
significance of these lecture materials in practice. The next 5 laboratories look at high-level
circuit design of discrete-time analogue modulators implemented as switched-capacitor
circuits. Ideally, by the end of the lectures and laboratories course you should feel able to
confidently design real DSMs.

This first laboratory introduces Matlab and Simulink as very useful tools for system-level
modelling and predicting the performance of DSMs. These two tools are widely-available
and widely-used in industry and academia for system modelling and simulation.

System-level modelling and simulation play critical roles in the early stages of a Delta
Sigma modulator design, be it a DSM-based ADC, DAC or even a purely digital design,
such as a divider in a fractional-N PLL.

A first task when designing any new, complex system is often to build one or more
mathematical models of the system which can be used to predict and explore the system
behaviour, optimize aspects of its behaviour and/or compare competing designs. Only
once a satisfactory system-level design is achieved are detailed implementation issues
considered – this is the “Top-Down” design approach. For linear systems, exact
mathematical analysis to aid their design is often possible; predicting system stability and
noise being commonly-encountered and well-established examples.

Unfortunately, DSMs contain a quantiser and are thus nonlinear feedback systems. As is
common for nonlinear systems, exact mathematical analysis of DSMs is often very difficult
or even impossible, and to date there is no complete theoretical analysis for arbitrary
DSMs that can be used to accurately and unquestionably predict if a proposed modulator
design will fully meet its performance targets, and do so with no undesirable side-effects.

Nevertheless, some useful analytical results have been achieved which can be used to
guide a design of a DSM, and you will encounter some of these is the course lectures:

• In a few specific cases exact mathematical analysis may be possible.

• By making simplifying assumptions some general mathematical analyses become
possible, but violating these assumptions can result in the real modulator behaving very
differently than predicted (such as having a much reduced stable input signal range or
even total loop instability).
• Additionally, some analyses yield only upper or lower performance bounds, beyond
which it may be possible to push some designs to achieve higher performance without
disastrous results. In this sense they are more like warning guidelines when constructing a
new design rather than giving absolute design limits.
• Finally, some commonly-used results are just accepted rules-of-thumb based more
on extensive experience than theoretical consideration!

The consequence of the various approximations and limitations invoked either to get
mathematically tractable results or simply because experience suggests they are good
rules-of-thumb, is that extensive system-level simulation is essential to check whether a
given modulator will indeed perform to specification when designed using existing theory -
and without unwelcome surprises such as modulator instability under certain conditions.

It should be noted that even when designing and simulating at the system level, DSM
models commonly include (usually simplified) models of some real circuit implementation
effects which can have a strong influence on the behaviour of the modulator. For any
modulator these can include:

• Finite signal-swing headroom effects such as soft saturation and hard clipping;
saturating integrators or quantisers can badly degrade overall modulator performance, and
even cause irrecoverable modulator loop oscillation in some high-order modulators.

Additionally, for an analogue modulator loop (i.e. a DSM-based ADC) these may further
include:

• Finite gain and bandwidth of the circuits used to realize the integrators.
• Nonlinearity of the modulator circuits.
• Effects of systematic or random (“mismatch”) component deviations; consequences
of these include signal path gain errors (some modulators are very sensitive to this) and
highly-troublesome nonlinearity in the feedback DAC path of modulators with multi-bit
quantisers (the topic of lab 4).

The reason why such effects are often included - even if only in approximate form - at the
system-level simulation stage is that circuit-level simulation is not an effective tool for
investigating their effects. System-level simulations usually run at least thousands of times
faster than circuit-level simulation using tools such as HSPICE™ or Spectre™
(seconds/minutes versus hours/days). Given that many hundreds or thousands of
simulations may be required to convince a designer that their DSM design will behave as
expected for likely inputs (no SQNR degradation, oscillations, signal distortion, in-band
spurious tones etc.), it is unreasonable in terms of simulation time requirements to use
only circuit simulators for examining the consequences of real circuit effects. Including
approximations of circuit effects in the system-level model can however allow their likely
effects to be studied under a wide range of modulator operating conditions and hence
hugely increases the likelihood that any problems they cause will be found, and found
early in the design process.

Please maintain a good laboratory notebook as you work through the lab exercises
for this course. You will be asked to note and comment on various aspects of
modulator behaviour and will be asked often to refer back to previous results -
sometimes those obtained during a prior lab session - when comparing different
modulators. Your laboratory notebook will not be assessed, but failure to keep good
notes will make your laboratory work unnecessarily difficult by requiring you to re-
run previous exercises when comparing results.
 Sigma-Delta Data Converters
Laboratory Session 1
1.0 Objectives

In this laboratory, you will examine the properties of the first order sigma-delta modulator
(called “MOD1” using the terminology of the course text [1]) using Matlab and Simulink:

• You will be able to observe the time domain waveforms of the modulators in
response to both DC and sine wave inputs.
• You will observe noise shaping in the frequency domain via Fast Fourier
Transforms (FFTs), thereby confirming first-hand a fundamental operating principle
of DSMs, and see how noise shaping can result in high resolution conversion in
oversampled systems.
• A number of effects will be studied such as idle tones, dead zones and saturation.
You will observe the effects of dither and finite gain on the MOD1 modulator
characteristics.

The material in this laboratory is intended to aid students in understanding the material in
chapter 1 and 2 of [1].

1.1 Setup
You are strongly advised to consult the course textbook [1] while you are following the
laboratory; “Understanding Delta Sigma Modulators” by R. Shreier and G. Temes, which is
available online at:
http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508.

Login to Learn on http://myed.ed.ac.uk and download the file “SDsimulink.tar.gz” from the
folder “Latest Database” into your home directory.

Unzip this file by typing “gunzip SDsimulink.tar.gz”.

Untar the resulting file by typing “tar xvf SDsimulink.tar”.

You will see a new directory “EdUni”. Change directory into this location by typing “cd
EdUni”.

In this directory there are general utility routines:

sweep_testbench.mdl

In the directory “LAB1” there are a number of Simulink files that will be used in this
exercise:

dc_to_mod1.mdl
mod1.mdl
mod1_delint.mdl
quantiser1.mdl
quantiser2.mdl
quantiser3.mdl
sin_to_mod1.mdl
As well as a second directory “ELEE11080_ROUTINES” containing the following Matlab
command files:

baseband_power.m
baseband_sqnr.m
calc_quant_gain.m
init_vars.m
init_vars3.m
integ_stats.m
Qout_SNDR.m
Qout_SNDR_ac.m
sweep_dc_bbpwr.m
sweep_dc_dc.m
sweep_sin_ampl_sqnr.m

In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.

In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current

Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directory “LAB1”.

Type “init_vars” into the Matlab Command Window. This routine sets the default values for
common variables used in the various forthcoming exercises.

You are now ready to begin the lab.

1.2 MOD1: A First Order Modulator Simulink Model

The first modulator we will study is the very simplest DSM, a first order modulator loop with
single bit quantisation. The convention for this course will be to refer to a modulator with
loop order N as a type “MODN” modulator; the modulator we are about to study is thus
“MOD1”.

Right click on “dc_to_mod1.mdl” in “LAB1” and select “Open F4”. You should now see the
modulator schematic shown in Figure 1.
Fig. 1 dc_to_mod1.mdl schematic

This consists of the following main elements:

1. A non-delaying discrete-time integrator composed of a 1/z unit delay element in

feedback to an adder. A gain block precedes the delay element, and can represent
any finite integrator gain at dc, e.g. caused by the finite gain of an amplifier used to
implement a real analogue integrator, using the parameter modctrl.igain1 (the
default is +Inf, giving an ideal integrator with infinite gain at dc). A saturation block
represents the clipping effect of, e.g., finite power supply voltages or digital word
lengths in real modulators. The saturation range is set to +/-modctrl.isat1 and the
default range is +/-Inf which does not clip the signal. The integrator is the core
block responsible for noise shaping in the modulator.

2. A single-bit midrise quantiser. A quantiser element with step size of two has been
employed. This quantiser has output states +1 and -1 as show in Figure 2.

Fig. 2 The 1-bit quantiser transfer function

As this quantiser has only 2 output states, which can be encoded using a single
binary digit, it is often called a single bit, or 1-bit, quantiser. Here we use “-1” and
“+1” instead of the usual “0” and “1” as our binary codes simply so that the output is
then centred on zero.
 Notes: The default Matlab quantiser is midtread type with a step size of 2, so to
implement Figure 2 the input signal is shifted up by +1 before the quantiser and
down by -1 after to implement midrise behaviour. Consult [1] pages 21-24 if you are
unsure what these terms mean. Note too that the Matlab quantiser has infinite input
and output range and will give output codes “-5”, “+3”, “+101” etc. for suitably large
analogue inputs; the saturation block is needed to limit the output range to the
desired “-1” to “+1”.

3. A delaying feedback loop from the quantiser output to the input, where the two
signals are subtracted and the error signal LOOPERR is applied to the integrator.
The delay in the feedback represents the time to quantise, sample and feed back
the integrator output – usually a single clock cycle.

Note that for an analogue modulator the feedback path requires a DAC because the
quantiser output is a digital code but the modulator input is analogue. Here the
quantiser outputs -1 and +1 map directly to the desired analogue feedback levels -1
and +1 so no D/A conversion is needed at the system modelling level. Had we used
a quantiser with output codes “0” and “1” then a conversion to “-1” and “+1”
analogue levels respectively would be needed in the feedback path to support an
analogue input signal range -1 to +1.

4. A filter at the output of the modulator, the output of which recovers the low
frequency average of modulator digital output stream. A real analogue-input
modulator (ADC) is followed by a digital filter (with decimation to reduce the sample
rate) to remove out-of-band signals and create the digital output (a digital-input
modulator (DAC) is followed by an analogue post-filter to create the analogue
output). Here we use an analogue filter simply for simulation simplicity.

In addition to the main functional elements in the modulator there are a number of input
and output blocks:
1. A dc input parameterised by the variable “input_dc”,
2. A dither source input, generating white noise between +1 and -1. This is scaled by a
gain block (modctrl.dgain1) and summed at the input of the quantiser.
3. A time scope which allows various internal signals in the modulator loop to be
visualized.
4. A spectrum scope performing an FFT of the modulator output.

Notes:

The default sampling frequency, Fs, is chosen as 1 MHz. The default oversampling ratio,
OSR, is 64. The signal band of interest extends to Fs/(2.OSR), and is thus from 0 Hz
to 7812.5 Hz. All other frequencies are “out-of-band” and would be removed by the
decimation filter following the modulator.

1.3 Time Domain Operation for DC Input

We will now examine how the first order modulator sigma-delta ADC behaves with the
simplest possible input, a DC input level. You may wish to consult section 2.6 of the
course text during this exercise.
Set the DC input level to 0 by typing “input_dc = 0” into the Matlab command window or by
right clicking on the input_dc entry in the workspace pane.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the Simulink
window.

You will see an FFT of the modulator output appear in a “Spectrum Scope” window. This
shows the output spectrum for frequencies from dc to Fs/2.

Right-click the FFT plot area and select autoscale to see the entire trace.

Double click on the time scope to observe the waveforms at the nodes in the modulator.
You may wish to autoscale the waveforms (the binoculars icon will scale them all).

Click on the magnifying glass icon with “Zoom X-axis” in to let you zoom into a few cycles
of the LOOPERR, INT1OUT and QUANTOUT waveforms.

Note any periodicity in the modulator behaviour and any strong frequency tones in the
FFT.

Repeat this for the following values of input_dc: 0.5, 0.75, 0.875, and 0.9375.

1. Observe and explain the time scope waveforms and the FFT tone frequencies and
amplitudes for each dc value. Can you predict the tone frequencies for a given
input_dc?

Tip: set x-axis to log in View/Spectrum settings

input_dc = 0

No idle tones (flat spectrum), modulator output toggles continuously between +1 and -1

input_dc = 0.5 = ½

a=1 and b=2 in fractional form, so period of fundamental idle tone is 2b (see Lecture 3),
i.e. frequency is fs/4=250kHz
input_dc = 0.75 = 3/4

a=3 and b=4 in fractional form, so period of fundamental idle tone is 2b, i.e. frequency is
fs/8=125kHz. There are also two harmonics.

input_dc = 0.875 = 7/8 (hint: use “format rat” in Matlab)

a=7 and b=8 in fractional form, so period of fundamental idle tone is 2b, i.e. frequency is
fs/16=62.5kHz. There are also six harmonics.

input_dc =0.9375 = 15/16

a=15 and b=16 in fractional form, so period of fundamental idle tone is 2b, i.e. frequency is
fs/32=31.25kHz. There are also fourteen harmonics.

2. Note in each case, the lowpass filter output QUANTLPF and compare its settled
value to the input_dc setting (The Y magnifying glass may help here). Is the
modulator a good dc ADC; that is, does the filtered output dc level accurately
represent the analogue dc input (once any initial settling transient has passed)?

Yes, in each case the filtered output matches the dc input (in the steady state). Note that
the idle tones are outside the signal band and are therefore filtered out by the low pass
filter.

3. Is the output spectrum first-order noise-shaped? If not then why not?

The output is not first-order noise-shaped (no 20db/dec slope is visible). This is because
the quantisation noise is dominated by idle tones at specific frequencies. This breaks the
assumption of white (uncorrelated) additive quantisation noise in our linear model, and
means that the noise transfer function is not exercised at a broad range of frequencies and
hence it is shape is “hidden”.

Now, set input_dc to “–pi/10” and re-run the simulation. Repeat for input_dc set to
+0.4367.

1. Observe and comment on the shape of the FFT plots. Is there noise shaping
evident? Are there strong tones? Why do you get the results you do? What is so
different about the dc input –π/10 and the previous inputs ½, ¾. etc.?

input_dc = -pi/10

The input is now an irrational number, although because it is still represented by a rational
number by Matlab (due to the finite precision of computers), there are nevertheless idle
tones (spurious peaks) in the spectrum. However, the idle peaks don’t completely
dominate the spectrum and noise shaping (20dB/dec slope) is now visible.

input_dc = 0.4367 = 307/703

a=307 and b=703 in fractional form, so period of fundamental idle tone is b, i.e. frequency
is fs/703=1.4 kHz (this peak can be seen on the spectrum by reducing the bin size RBW).
The fundamental idle tone is also visible on the time scopes (perhaps most obviously on
the filtered modulator output). Nevertheless, due to the many harmonics of the idle tone
“filling up” the spectrum, the noise shaping (20dB/dec slope) is again visible.

Set input_dc to +0.98 and re-run the simulation.

1. Observe and explain the time scope waveforms and FFT frequencies.
a=49 and b=50 in fractional form, so period of fundamental idle tone is 2b, i.e. frequency is
fs/100=10kHz. The behaviour is strongly tonal (although the tones are outside the signal
band for the assumed OSR) and no noise shaping is visible.

Set input_dc to +1.02 and re-run the simulation.

1. Observe and explain the time scope waveforms, in particular the integrator output.
What sort of input signal sizes can this modulator handle? Why?

An input with absolute value > 1 makes the modulator unstable, as it cannot be
reproduced by a sequence of +1’s and -1’s. The output gets “stuck” at +1 and the
integrator keeps integrating the consequent loop error of 0.02, thereby tending to infinity.
The spectrum/FFT is purely composed of numerical artefacts (as the output no longer has
spectral content).

1.4 Tonal Behaviour for Swept DC Input

The previous exercise highlighted the highly tonal behaviour of basic MOD1 for rational dc
inputs and the simple relationship between the input level and resulting tone frequencies.
We will now study the signal-band tonal behaviour of MOD1 across a swept range of input
dc levels. By signal-band we mean here only that energy in the output spectrum which lies
between dc and Fs/(2.OSR); remember that a modulator is an oversampled converter and
only a portion of its output spectrum (as defined by the OSR) is of interest. Any “out-of-
band” noise and/or tones outside the signal-band will be removed by a post-filter. You
may wish to consult section 2.6 of the [1] during this exercise, particularly noting the
discussion of figure 2.22.
Close “dc_to_mod1.mdl”.

Type target_modulator=‘mod1’ into the Matlab Command Window.

Run the routine “sweep_dc_bbpwr”.

The sweep_testbench.mdl Simulink model window will appear (and may or may not then
close automatically – Matlab seems quite unpredictable in this regard as new software
versions are released!) and the simulation will start.

Warning: The simulation analyses the signal-band noise power for 1000 dc levels may
take over five minutes to complete!

A plot of total baseband noise power in dBW will be generated for input amplitudes from 0
to 1, the maximum allowed input.

1. Observe the noise power at the dc levels studied in section 1.3.

2. Note which input levels have high tonal noise power and explain this. Why is the
signal-band power small for simple rational inputs such as 0, 1/2, 1/3, 1 etc. (note
the notches in the noise features at these levels). Compare the plot to that in Fig.
2.22 (OSR=64) of [1] and note the comments at the foot of page 44.

(same profile as corresponding plot in [1])

It is input levels close to simple rational inputs e.g. 0.497=497/1000 that tend to produce
high tonal noise power (peaks in the above figure), as these inputs lead to limit cycles with
long periods, which thus fall within the signal band. Simple rational inputs themselves lead
to short limit cycles (outside the signal band) dominating the spectrum. Therefore, there is
reduced quantisation noise in the signal band, resulting in the notches seen in the figure.

Leave the baseband noise power window open.

Now add some random noise dither by setting modctrl.dgain1=0.2 in the Matlab Command
Window.
Re-run the simulation to get another baseband noise power window.
(Refer to Figure 1 to double-check exactly where dither is being applied.)

1. What has happened to the tones and average power levels? (It is sufficient to
compare visually results with and without dither here, numerical answers are not
required.)
2. Why does dither cause this? Is adding dither a good idea then? Is so then how
much should you add? Can you add too much? Must the dither be white, or will,
 e.g., Gaussian noise work? Don’t spend too long thinking about this; it is a good
topic to discuss with the teaching staff but somewhat beyond the scope of this
course.

The plot has become “smoother”, indicating reduced tonal behaviour because of the dither.
Although the baseline noise power has increased by around 20dB (due to additional noise
being injected into the loop), the average noise power has only increased by about 2dB
(due to the removal of peaks). The behaviour of the modulator has become more
robust/consistent, with fewer problematic inputs.

Dither breaks up limit cycles (this can be observed on the time scope: the period of limit
cycles is no longer constant, leading the corresponding spectral peak being “dampened”).
However, it does also raise the noise floor in the signal band, so excessive dither can
ultimately impact the resolution of the modulator.

Gaussian or uniformly distributed white noise will both work, this can be verified by
changing the noise parameters in the model.

1.5 DC Input with Finite Integrator Gain

We will now study the effect of finite integrator gain on the time domain waveforms and dc
transfer function of MOD1. You may wish to refer to section 2.8 of the course text during
this exercise.

Close all windows generated in Section 1.4 and open “dc_to_mod1.mdl” again.

Simulations so far have assumed an idea integrator with infinite integrator gain at dc; this
is trivially easy to achieve in digital modulators, but in analogue modulators the integrator
gain at dc will be finite owing to things like finite amplifier gains, leakage currents
discharging integration capacitors, etc.

Remove the dither by setting modctrl.dgain1=0.0.

Now introduce a finite dc gain error in the modulator by setting modctrl.igain1=50. Recall
that an ideal integrator’s gain tends to infinity for input frequencies tending towards dc.
Now the gain will level-off for low-frequency inputs and the integrator looks like a low-pass
filter with dc gain 50.

Try a few dc levels: input_dc = 0.4367, 0.1, 0.01 and 0.005.

 1. Note the difference between the output filter QUANTLPF and the input_dc value,
and observe the LOOPERR, INT1OUT and QUANTOUT waveforms. Is the
modulator still an accurate dc ADC, i.e. do the input and output dc levels match? If
not then why not?

There is an offset between QUANTLPF and the input_dc value, QUANTLPF always
being lower than abs(input_dc). This is due to the integrator being “leaky”, and
therefore unable to generate the sequence required to drive the average of the
modulator output to the correct value.

2. Comment in particular on the MOD1 output with inputs 0.01 and 0.005. What is
happening here?

These inputs fall into the deadzone around input_dc = 0 and therefore give the
same output as input_dc = 0 (the modulator output toggles between +1 and -1, the
average/filtered output being 0).

3. Comment also on any tone frequencies (you are not expected to check them by
hand-calculation here), just note if they have changed compared to the infinite gain
case.

input_dc = 0.4367 now shows three high frequency (>100kHz) tones, for input_dc
= 0.1 the frequency of the fundamental tone has reduced, input_dc = 0.01 and
0.005 show the same (flat) spectrum as input_dc = 0

Close the dc_to_mod1.mdl window and now perform a dc sweep for a subset of the input
range (-0.1 to +0.1) by running “sweep_dc_dc”.

Now type modctrl.igain1=inf and rerun “sweep_dc_dc” to get an ideal integrator transfer
function for comparison.

1. Compare the dc sweep results for an ideal integrator and one with finite dc gain 50.
Which is the best ADC (i.e. which gives output = input most accurately)?
2. Note the dead zone behaviour when modctrl.igain1= 50 (c.f. figure 2.24 in [1]).
These are the flat regions where the modulator output is the same for all modulator
inputs within the zone. It is strongest about input 0, but small additional dead zones
can be noted around other rational inputs. Is this behaviour desirable or
undesirable? Why?
3. Measure the width of the main dead zone around input_dc = 0 and relate this to the
integrator gain - compare it to that predicted on page 53 of the course text for A=50.
Do you get a good match with theory?

igain1 = inf ingain1 = 50

The ADC with an ideal integrator can reproduce the input exactly (when the average of the
output is taken). On the other hand, the input-output plot for the case of the finite gain
integrator shows an offset as well as dead zones. This is undesirable as it means, for
example, that low amplitude inputs will not be reproduced at the output. The observed
width of the dead zone around input_dc=0 is 0.02, this is in line with the theory, which
predicts a dead zone extending from -1/(2A) to +1/(2A).

See page 51-53 and Fig. 2.24 of [1] for more information about dead zones.

1.6 Sine Wave Input

We will now examine the behaviour of MOD1 in response to a sine wave input.

The parameter sinfreq (default: 4882.8125 Hz – note that with the default number of
significant digits Matlab will show this as 4882.8 Hz) and sinamp (default 0.707) set the
frequency and amplitude of the input sine wave.

(Note this frequency has been chosen such that an integer multiple (40) of complete
periods of the sinusoid are present within the 213 = 8192 samples acquired by the FFT
routine and also so that the sine wave frequency falls exactly into one of the PSD bins.

Such measures are generally very necessary to avoid effects like spectral leakage (even if
windowing is being used - we highly recommend you read appendix A of [1]) or waveform
truncation from corrupting the simulation results. Satisfying the dual needs of a complete
number of waveform cycles in a power-of-2 sample window length in addition to the signal
being in an exact FFT bin can limit the number of input frequencies that can be simulated
well. Please bear this in mind throughout all labs; careless frequency choices can
easily generate plots dominated by FFT artefacts instead of modulator behaviour,
especially at the high signal-to-noise ratios we will be interested in!)

Close the Simulink windows from the previous section.

Open “sin_to_mod1.mdl” and ensure modctrl.igain1=Inf (typing “init_vars” again will reset
all variables to suitable values). This schematic is identical to dc_to_mod1 but with a
discrete time sampled sinewave source replacing the dc input source.

Run the simulation.

You will see an FFT of the modulator output showing a large input tone and a rising
quantisation noise spectrum (difficult to see easily here due to the large number of
spurious tones).

Type “Qout_SNDR” to see the plot with log axes (you may be able to select a log X-axis in
the spectrum scope, but this is unfortunately not possible with some versions the Simulink
Spectrum Scope, e.g. those supplied with Matlab versions earlier than R2014) and the
value of the baseband signal to noise+distortion ratio (SNDR) for an oversampling factor of
64.

Double click on the time scope to observe the waveforms at the nodes in the modulator.

Zoom into a few cycles of the LOOPERR, INT1OUT and QUANTOUT waveforms.
 1. Note the amplitudes of the LOOPERR and INT1OUT waveforms.
2. Can you see the sinewave captured in the modulator output QUANTOUT in the
varying density of 1s and -1s in its output sequence? Does the digital output stream
look like it encodes the input sinewave accurately? Yes!
3. Is the modulator a good analogue to digital converter? That is, is the output
sinewave after the low-pass filter a good copy of the input sine wave (ignore any
phase shift between the input and output, as this is predominantly caused by the
low-pass filter)? Note the effective number of bits reported earlier by Qout_SNDR
and comment on how this compares with the number of bits in the modulator
internal quantiser. The modulator is a reasonably good ADC for this particular input,
although the spectrum shows spurious tones (in addition to the signal peak). The
resolution of the modulator is indicated as 9-bits (as compared with the 1-bit internal
quantiser).

Type “sinfreq = sinfreq/8” to reduce the input frequency and re-run the experiment.

1. Note the changes in the waveforms, FFT and SNDR.

2. Measure the slope of the quantisation noise spectrum; is this what you expect for
first-order noise shaping?

The time waveforms are similar in profile and have the same amplitudes as before. The
spectrum is “cleaner” (no obvious spurious peaks in the signal band), although the SNDR
(and ENOB) is somewhat lower than before. This demonstrates the dependence of tones
not only on the dc input level but also on the input frequency.
Repeat the exercise for sinfreq=4882.8125 Hz and sinamp = 0.95 and 1.05

1. Note the amplitudes of LOOPERR and INT1OUT and compare with those obtained
when sinamp was 0.707 (keep these results as they will be required in lab 2).
Comment on the SNDR difference for input amplitudes 0.95 and 1.05. Does MOD1
recover readily from overload caused by the peaks of the sinamp = 1.05 signal?

sinamp=0.95

sinamp=1.05

The amplitudes of LOOPERR and INT1OUT have somewhat increased (to close to 2, at
which quantiser overload starts), and the spectral plots show higher spurious peaks and
reduced SNDR (especially in the case of sinamp=1.05). For sinamp=1.05, the integrator
slightly “meanders” at the peaks of the input signal (corresponding to the modulator
becoming unstable as the magnitude of the input goes above 1, but then quickly
recovering as the input drops back below 1) – this effect can be seen even more clearly by
running a sim for, eg., sinamp=1.1.
1.7 Sine Wave Amplitude Sweep

We will now study the signal to quantisation noise of MOD1 in response to a range of sine
wave amplitudes.

Close “sin_to_mod1.mdl” and any plot windows and set sinfreq=4882.8125 Hz if it is not
already so.

Run the routine “sweep_sin_ampl_sqnr”.

The sweep_testbench.mdl window will appear; you can ignore it if it does not automatically
disappear. You will see a plot of signal to quantisation noise ratio (SQNR) versus sine
wave input amplitude in decibels (dBs), where 0 dB corresponds to amplitude = 1.

1. Note the peak value of SQNR and compare this to the theoretical SQNR from the
formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 (
)
2L + 1
where the modulator order L=1, the oversampling ratio OSR=64, and number of bits
N=1. Do you get a reasonable match?
2. Why isn’t the peak SQNR achieved for maximum signal (0 dB)? What has
happened at 0 dB?

The peak SNDR of 57.5dB is achieved at an amplitude of approx. -1 dBFS or 10^-(1/20) =

0.89. This is similar to the SQNR of 56.8dB predicted by the theoretical equation above. At
0dB, the modulator is only marginally stable at the peaks of the input, and there is
increased distortion and tonal behaviour, leading to a reduction in SNDR.

What SNR do you observe below an input level of -35 dB of full-scale (FS)? You will find
there is no signal here, so the SNR = 0 (because S=0). This is not a dead-zone, but an
artefact of MOD1’s (awful!) tendency to tonal behaviour. This behaviour is very input
dependent; for example, re-running the sweep with sinfreq = 610.3516 Hz gives a much
“better behaved” result. Try it. One way we have seen to disrupt tones and limit cycles
from forming is to inject a (pseudo)random dither in to the loop.

Now try adding a small amount of dither.

Set sinfreq = 4882.8125 Hz and modctrl.dgain1=0.2 in the Matlab Command Window and
re-run the simulation.

1. How has behaviour below -35 dB input altered? Does the modulator look “better
behaved” (no flat regions or wild swings in the SQNR versus amplitude plot) with
dither? Why?
2. What is the peak SQNR value? Compare to that predicted by the above formula.
Again, comment on any drop in SQNR as the input amplitude rises from -1 dB to 0
dB.

Adding reduces idle tones, leading to a smoother plot, with a more monotonic increase in
SNDR as the input amplitude is raised. However, the peak SNDR value is somewhat lower
than before (by around 4dB), due to the increased noise floor resulting from the dither. As
before, there is a drop in SNDR from -1dBFS to 0dBFS

Set modctrl.dgain1 = 0.8 and re-run the simulation.

1. Does the SNDR versus amplitude curve look to have improved further by adding
even more dither?
2. What is the peak SQNR now? What has adding more dither done to the peak
SQNR? What then could be one downside to adding large amounts of dither to help
disrupt the loop tendency towards tonal behaviour?

The curve is now smoother still, but the peak SNDR has dropped further (to around 47dB).
This demonstrates the downside of adding large amounts of dither: it leads to a lower
SNDR and hence effective resolution.
Reset the dither level to modctrl.dgain1=0.0.
Set the finite integrator gain with modctrl.igain1=10.

3. How has the SQNR graph changed? Is the modulator ever likely to be a good
noise-shaping ADC with an integrator gain of only 10? Would you expect it to be?

A large dead-zone has appeared preventing inputs with amplitude lower than -25dBFS
(0.05) from being reproduced at the output. For higher amplitudes, the SNDR fluctuates
considerably as a result of idle tones, and the peak SNDR is 14dB lower than for infinite
integrator gain. Thus, an ADC with an integrator gain of just 10 will offer a rather poor
performance.

1.8 Learning review

This lab has examined some key, basic properties of DSMs by studying specifically the
behaviour of the basic modulator MOD1. Hopefully being able to experiment with a
modulator in simulation and seeing effects like noise-shaping, dc tone generation, dead-
zones and the effects of dither etc. in action will aid your understanding of the various
significant basic principles underlying all DSM operation covered in the course lectures.

You may also have noted that despite being the obvious start point for modulator study,
MOD1 is actually quite a dreadful modulator; being highly prone to:

1. dc limit cycles (tonal spectrum with no noise-shaping),

2. idle tones with sine wave or irrational dc input (noise shaping evident, but with
strong tonal behaviour also present),
3. wide dead zones unless the integrator dc gain is very high.

Consequently MOD1 is not widely used on its own. Applying dither helps greatly, but in
practice with real modulators having limited integrator output swing etc., dither tends to
overload single-bit MOD1s, causing further problems. Offering only first-order noise
shaping, MOD1 is also limited in achievable SQNR for realistic oversampling ratios (to
achieve 16 bits ENOB for audio signals to 20 kHz would require the MOD1 to be clocked
at 100 MHz).
For the above reasons, MOD1, especially with 1-bit quantisation, is not commonly seen,
even for the least demanding applications (MOD1 does appear often as part of certain
cascaded modulators called MASH and SMASH converters to be examined in later labs).

The next labs will introduce higher-order modulators that behave much more like ideal
delta-sigma modulators (and so will hopefully be a much better aid than MOD1 to gaining
a better insight into and understanding of modulator behaviour), give far better SQNR at
moderate oversampling ratios, and that are thus much more commonly used.

1.9 Additional material

If you have finished the lab with time to spare, or using some time afterwards, you may
wish to become familiar with the important topic of “effective gain” of a 1-bit quantiser,
covered in section 2.1.1 of [1]. See also section 3.3.1.

Variation of effective quantiser gain with input signal level – especially for modulators
using 1-bit quantisation – is the source of many instability or “real NTF ≠ intended NTF
with degraded performance consequences” problems in practice.

Some test-benches with 1, 2 and 3-bit midrise quantisers with output range [-1:1] are
provided in LAB1:

quantiser1bit.mdl
quantiser2bit.mdl
quantiser3bit.mdl

Additionally, the ELEE11080_ROUTINES script

calc_quant_gain.m

has been provided. To use these, first open and run one of the quantiser test benches and
then type “calc_quant_gain” to compute the effective quantiser gain. You may wish to
examine the calc_quant_gain.m script and compare with section 2.1.1 of [1]. The sine
wave input is best for visually studying the quantiser operation by clicking on the signal
scope. The white noise source is better for estimating the gain.

You should alter the peak values of the sine or white noise quantiser input signal (by
clicking on the relevant signal source block and editing appropriately) and note the
effective gain. You may wish to plot a graph of gain versus input amplitude from, say, 0.25
to 1.5 in 0.25 steps using the white noise source for the 1-bit and 3-bit quantiser and
compare them. Which has the better-defined gain? Why? (Hint, sketch the quantiser
transfer functions: which uses more than 2 points to define the gain of a corresponding
linearised quantiser model? When does input overload start for each?)
Overload starts at +2,+1.333 and +1.14, respectively for 1, 2 and 3-bit midrise quantisers
(when the error becomes > 0.5 LSB). The more output levels, the better-defined (more
uniform) the gain is.

References:
[1] Schreier, Temes: Understanding Delta-Sigma Data Converters, Wiley-Blackwell 2004.
 Sigma-Delta Data Converters
Laboratory Session 2
1.0 Objectives

In this second laboratory, you will examine the properties of some second order modulator
topologies. We will follow almost exactly the same sequence of simulations done for the
first order modulator in laboratory session 1. You should make comparisons between the
performance of the first and second order modulators throughout.

1.1 Setup

You may wish to consult the course textbook as you are following the laboratory,
“Understanding Delta Sigma Modulators” By R. Shreier and G. Temes, which is available
online at:

http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508

You should still have a copy of all the Matlab laboratory materials in a directory called
“EdUni” created at the start of Laboratory 1; if not then please consult the laboratory 1
hand-out for instructions on how to create this Matlab workspace (and please don’t delete
it again!).

Change directory into this location by typing “cd EdUni”.

In this directory there is a general utility simulation test bench:

sweep_testbench.mdl

In the directory “LAB2” there are a number of files that will be used in this exercise:

dc_to_mod2.mdl
mod2.mdl
mod2_boserwooley.mdl
mod2_errorfeedback.mdl
mod2_silvasteensgaard.mdl
sin_to_mod2.mdl

As in laboratory session 1, we will also require the utilities held in the directory
“ELEE11080_ROUTINES”.

In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.

In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current

Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directory “LAB2”.

Type “init_vars” into the Matlab Command Window. This routine sets the default values for
common variables used in the forthcoming exercises.
You are now ready to begin the lab.
1.2 Second Order Modulator Simulink Model

Fig. 1 dc_to_mod2.mdl schematic

Right click on “dc_to_mod2.mdl” in “LAB2” and select “Open F4”. You should now see the
second order modulator schematic shown in Fig. 1. This is “MOD2” in the course text and
consists of the following main elements that you encountered in MOD1 in lab 1:

1. Two non-delaying integrators each composed of a 1/z unit delay element in

feedback to an adder. A gain block precedes the delay element, and can represent
any finite integrator gain at dc and a saturation block represents the clipping effect
of, e.g., finite power supply voltages or digital word lengths in real modulators. The
integrators are the core blocks responsible for noise shaping in the modulator.

2. A midrise quantiser. This is a single-bit quantiser with output states -1 and 1 as

described in the lab 1 notes.

3. A delaying feedback loop from the quantiser output to the input, where the two
signals are subtracted and the error signal LOOPERR is applied to the integrator.
The delay in the feedback represents the time to quantise, sample and feed back
the integrator output – usually a single clock cycle.

4. An (analogue) filter at the output of the modulator that removes out-of-band signal
components at the modulator output so that you can visualise the signal-band
performance. Recall that in a real DSM-based ADC this would be a digital filter and
an analogue filter is used here simply for ease of simulation.

In addition to the main functional elements in the modulator there are a number of input
and output blocks:
1. A dc input parameterised by the variable “input_dc”,
2. A dither source input, generating white noise between +1 and -1. This is scaled by a
gain block (modctrl.dgain1) and summed at the input of the quantiser.
3. A time scope which allows various internal signals in the modulator loop to be
visualized.
4. A spectrum scope performing a FFT of the modulator output.
Notes:

The default sampling frequency, Fs, is chosen as 1MHz. The default oversampling ratio,
OSR, is 64. The signal band of interest extends to Fs/(2.OSR), i.e. from 0 Hz to 7812.5 Hz.

1.3 Time Domain Operation for DC Input

We will now examine how the second order modulator sigma-delta ADC behaves with a
DC input. You may wish to consult sections 2.6 and 3.3.2 of the course text during this
exercise and also compare with your results for MOD1 dc behaviour from lab 1.

Set the DC input level to 0 by typing “input_dc = 0” into the Matlab command window or by
right clicking on the input_dc entry in the workspace pane.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the Simulink
window.

You will see an FFT of the modulator output appear in a “Spectrum Scope” window.

Right-click the FFT plot area and select autoscale to see the entire trace.

Double click on the time scope to observe the waveforms at the nodes in the modulator.
You may wish to autoscale the waveforms (the binoculars icon will scale them all).

Click on the magnifying glass icon with “X” in to let you zoom into a few cycles of the
LOOPERR, INT1OUT, INT2OUT and QUANTOUT waveforms.

Note any periodicity in the modulator behaviour and strong frequency tones in the FFT.

Repeat this for the following values of input_dc: 0.5, 0.75, 0.875, 0.9375.

1. Observe the time scope waveforms and the FFT tone frequencies and amplitudes
for each dc value. Compare the frequencies to those obtained for MOD1 with these
dc inputs in lab 1 and comment. Note that the limit cycles in MOD2 are more
complicated than MOD1, e.g. by initialising the first and second integrators to 0.5
and 0.75, input_dc=0 can give output tones at multiples of Fs/2 rather than at
multiples of Fs/4 seen here – see Table 3.1 of [1] for this example. Consequently,
we will not analyse MOD2 in detail with a view to predicting limit cycle frequencies
for given dc inputs as previously done for MOD1. See also the footnote on page 78
of [1].

input_dc = 0 (Note: the spectral plots below were obtained by taking screenshots of the
oscilloscope, but it is simpler to use File -> Copy to Clipboard!)
The tone frequency is fs/4=250kHz (output cycles as +1,+1,-1,-1)
input_dc = 0.5

The tone frequency is fs/8=125kHz.

input_dc = 0.75

The tone frequency is fs/16=62.5kHz.

input_dc = 0.875

The tone frequency is fs/32=31.25kHz.

input_dc = 0.9375

The tone frequency is fs/64=15.625kHz.

For the cases considered above, the frequency of the fundamental tone is half of what was
seen with MOD1 (however, as noted above, the frequency in fact depends on the initial
state of the modulator, so predicting the frequency is not straightforward).

2. Note in each case the lowpass filter output QUANTLPF and compare its settled
value to the input_dc setting (The Y magnifying glass may help here). Is the
modulator a good dc ADC, i.e. does the filtered output accurately represent the
analogue dc input?

Yes, in each case the filtered output matches the dc input (in the steady state). Note that
the idle tones are outside the signal band and are therefore (largely) filtered out by the low
pass filter. For input_dc = 0.9375 (where the tone is closest to the signal band), the filtered
output is seen to fluctuate by approx. +/-0.0002.

3. Look carefully at the integrator output values in each case. You can create
histograms of the integrator outputs by typing “integ_stats(INT1OUT)” and
“integ_stats(INT2OUT)” in the Matlab Command Window. Make a rough graph of
the absolute maximum integrator values versus the dc input. Comment on the
magnitude of the integrator outputs relative to the modulator input.

The magnitude of the integrator outputs (especially that of INT2) rises rapidly as the DC
input approaches 1 (and the magnitude of INT1 and INT2 always exceeds the input).

4. Why does the spectrum not appear to be second order noise shaped? Is MOD2 any
less prone to tonal behaviour than MOD1? Why?

The output is not second-order noise-shaped (no 40db/dec slope is visible). This is
because the quantisation noise is dominated by idle tones at specific frequencies. This
breaks the assumption of white (uncorrelated) additive quantisation noise in our linear
model, and means that the noise transfer function is not exercised at a broad range of
frequencies and hence it is shape is “hidden”.

Now, set input_dc to “–pi/10” and then +0.4367 and re-run the simulation.

1. Observe and comment on the shape of the FFT plots. Is noise-shaping evident? If
so than what order does the slope suggest it has?

input_dc = -pi/10

The input is now an irrational number, so limit cycles are much less visible in the spectrum,
and noise shaping (40dB/dec slope) can now be seen.

input_dc = 0.4367

Although the input is rational number, no strong periodicity is visible in the spectrum (or in
the time trace of the output) and noise shaping (40dB/dec slope) is again evident.

Set input_dc to +0.98 and re-run the simulation.

1. Observe and explain the time scope waveforms and FFT frequencies.
2. Use the time scope to note the integrator output ranges. Compare these with the
integrator range for MOD1 with input_dc = 0.98. Is a real MOD2 likely to have
problems with dc input levels near +/- 1?

See section 3.3.2 of [1] for more discussion. We will return to the very important
issue of integrator signal range, and what happens when signals exceed real
integrator output limits later in this lab.
The behaviour is strongly tonal, with the frequency of the fundamental tone being 5kHz, so
inside the signal band, (compared with 10kHz in the case of MOD1). No noise shaping is
visible. We also note that max(|INT1OUT|) > 2, and max(|INT2OUT|) >80 (compared with
max(|INT1OUT|) < 2 for MOD1), leading to massive quantiser overload (and increased
quantisation noise). In a real MOD2, the integrator outputs would saturate, resulting in
further distortion and noise.

Set input_dc to +1.02 and re-run the simulation.

1. Observe and explain the time scope waveforms.

An input with absolute value > 1 makes the modulator unstable, as it cannot be
reproduced by a sequence of +1’s and -1’s. The output gets “stuck” at +1 and the
integrators keeps integrating the consequent loop error of 0.02, their outputs increasing
indefinitely.

1.4 Tonal Behaviour for Swept DC Input

The previous exercise highlighted that the basic MOD2, like MOD1, still gives strong
output tones instead of a shaped-noise spectrum for rational dc inputs. We will now study
the signal-band tonal behaviour of MOD2 across a swept range of input dc levels. By
signal-band recall we mean here only that energy in the output spectrum which lies
between dc and Fs/(2.OSR); remember that a modulator is an oversampled converter and
only a portion of its output spectrum (as defined by the OSR) is of interest. Any noise
and/or tones outside the signal-band will be removed by a post-filter. You may wish to
consult section 3.3.1 of the course text during this exercise.

Close “dc_to_mod2.mdl”.

Type target_modulator=‘mod2’ into the Matlab Command Window.

Run the routine “sweep_dc_bbpwr”.

The sweep_testbench.mdl Simulink model window will appear and the simulation will start.

Warning: The simulation analyses the signal-band noise power for 1000 dc levels may
take over five minutes to complete!

A plot of total baseband noise power in dBW will be generated for input amplitudes from 0
to 1, the maximum allowed input.

1. Observe the signal-band noise power versus dc input behaviour and compare it
with that shown in [1] in Figure 3.11.
2. Compare also with the result obtained using MOD1 in laboratory session 1 (the
course text shows the MOD1 result in Figure 2.22, so you do not need to rerun the
simulation). Is MOD2 more or less prone to signal-band tones than MOD1?
Compared with MOD1, the plot shows reduced fluctuations (smaller peaks), indicating that
MOD2 is less prone to signal-band tones over most of the input range*. The “baseline”
noise level is also lower. However, there is a significant jump in the signal-band noise
power as the DC input nears 1. This is due to INT2 “ballooning”, and the quantiser being
severely overloaded as a result (see results for dc_input = +0.98 above). As a
consequence, the average base-band noise power (for the whole input range) is in-fact
slightly higher than for MOD1. Note also the upward slope in the baseline – this is due to
the effective quantiser gain reducing for higher input levels, which in turns increases the
NTF (i.e. reduces the suppression of quantisation noise) within the signal band (the effect
becoming increasingly significant near dc_input=1).

*As we have seen in section 1.3 above, MOD2 can still produce idle tones, especially for
some rational dc inputs, but, on the whole, strong in-band tones are less likely to occur, as
the modulator now has a bigger “state space”, i.e. two integrator outputs rather than one,
so there is bigger variety of state sequences, making it harder for repeating sequences
with large amplitudes and long periods to emerge.

Leave the baseband noise power window open.

Now add some random noise dither by setting modctrl.dgain1=0.2 in the Matlab Command
Window.
Re-run the simulation to get another baseband noise power window.
(Refer to Figure 1 to double check where dither is being applied.)

3. Has the dither made much difference to the signal-band noise behaviour? Is dither
necessary to suppress signal-band tones for MOD2? How does this compare with
MOD1?
While the effect is less marked than in the case of MOD1, dither does reduce the peaks on
the plot, indicating that signal-band tones are being successfully suppressed (a fact that is
also reflected in a lower average base-band noise power).

1.5 DC Input with Finite Integrator Gain

We will now study the effect of finite integrator gain on the time domain waveforms and dc
transfer function of MOD2. You may wish to refer to section 3.3.3 of the course text during
this exercise.

Close the windows generated in Section 1.4 and open “dc_to_mod2.mdl” again.

Simulations so far have used ideal integrators with infinite integrator gain at dc.

Remove any dither from the last section by setting modctrl.dgain1=0.0 (or just type
init_vars to reset all control variables).

Now introduce a finite dc gain error in the modulator integrators by setting

modctrl.igain1=10 and modctrl.igain2=10. Recall that an ideal analogue integrator’s gain
tends to infinite for input frequencies tending towards dc. Now the gain will level-off for low-
frequency inputs and the integrator looks like a low-pass filter with dc gain 10 (this is an
extremely poor integrator!).

Try a few dc levels e.g. input_dc as (0.4367, 0.1, 0.01).

1. Note the difference between the output filter QUANTLPF and the input_dc value,
and observe the LOOPERR, INT1OUT, INT2OUT and QUANTOUT waveforms. Is
the modulator still an accurate dc ADC? If QUANTLPF is not equal to input_dc then
why does this difference arise?

There is an offset between QUANTLPF and the input_dc value, QUANTLPF always
being lower than abs(input_dc). This is due to the integrators being “leaky”, and
therefore unable to generate the sequences required to drive the average of the
modulator output to the correct value.

Close the dc_to_mod2.mdl window and then perform a dc sweep for a subset of the input
range (-0.1 to +0.1) by running “sweep_dc_dc”.
 2. Note the dead zone behaviour. It is strongest about input 0, but small additional
dead zones can be noted around other rational inputs.

Deadzones are related to short period limit cycles – the integrator output will then feature a
ramp, but his ramp can level out due to finite integrator gain and never reach the required
value to “break out” of the given limit cycle and produce a different output pattern (with a
different average value). See slide 17 in lecture 4.

3. Measure the width of the main dead zone for 0 input and relate this to the integrator
gain, compare it to that predicted on page 78 of the course text for A=10. How does
MOD2 with finite integrator gains of 10 compare to MOD1 with finite integrator gain
100 examined in lab 1? Comment on any consequences for analogue modulator
design; is MOD2 more, less or equally (in)tolerant of low integrator gain?
dc input (green) and output (red)

The observed width of the dead zone around input_dc=0 is 0.016; this is in line with
theory, which predicts a dead zone extending from -0.75/(A^2) to +0.75/(2A^2), and is
indeed smaller than the dead zone of width 0.02 obtained with a MOD1 for A=IGAIN1=50.
MOD2 is much tolerant to low integrator gain, as the size dead-band is proportional to
1/A^2 rather than 1/A (note that A=10 would be unrealistically low in practice and was
chosen here to exaggerate the effect of finite integrator gain).

1.6 Sine Wave Input

We will now simulate the behaviour of MOD2 in response to a sine wave input, and
compare it to the MOD1 behaviour seen in lab 1.

The parameter sinfreq=4882.8125 Hz and sinamp =0.707 set the frequency and amplitude
of the input sine wave.

Close the Simulink windows from the previous section.

Open “sin_to_mod2.mdl” and ensure modctrl.igain1=inf, modctrl.igain2=inf and

modctrl.dgain1 = 0 (this can be achieved by re-executing “init_vars”).

Run the simulation.

You will see a FFT of the modulator output showing a large input tone and a rising
quantisation noise spectrum with some tones above 100 kHz.
Type “Qout_SNDR” to see the plot with log axes and the value of baseband signal to
noise+distortion ratio (SNDR) for an oversampling factor of 64.

1. Estimate and comment on the slope of this graph; is it what you would expect?
2. Comment on the spur near 15 kHz. What is this (think about the signal frequency)?
3. Comment on the slope, SQNR and presence or absence of tones compared to the
behaviour of MOD1 seen in lab1. Does MOD2 behave more like an “ideal”
modulator?
Modulator output spectral density (Units/sqrt(Hz))
0
10
Simulated:
SQNR = 70.4 dB Brickwall LPF @ fs/(2.OSR)
-2
10
ENOB = 11.4

10 -4
Unit/sqrt(Hz)

10 -6

10 -8

10 -10

10 -12
101 10 2 10 3 10 4 10 5 10 6
Frequency(Hz)
The slope is 40dB/dec (c.f. 20dB/dec for MOD1). Note that y-axis needs to be multiplied by
20dB to convert amplitude into decibels. The spur near 15kHz is the third harmonic of the
input sinewave; it arises due to distortion (in our theory we assumed a linear model for the
quantiser but it is in fact non-linear - see Section 3.3.1 in the Schreier textbook). However,
on the whole, the spectrum is a lot “cleaner” (and closer to the spectrum that the idealised
model predicts) than in the case of MOD1, and the SQNR is 15dB higher than for MOD1.

Double click on the time scope to observe the waveforms at the nodes in the modulator.

Zoom into a few cycles of the LOOPERR, INT1OUT, INT2OUT and QUANTOUT
waveforms.

1. Note the amplitudes of the LOOPERR, INT1OUT and INT2OUT waveforms.

2. Can you see the sine wave captured in the modulator output QUANTOUT in the
varying density of 1s and -1s in its output sequence?
3. Is this MOD2 a good ADC? That is, is the sine wave at the low-pass filter output a
good representation of the input sine wave (ignore any phase shift here, as it
predominantly caused by the specific low-pass filter used here)?

LOOPERR, INT1OUT, and INT2OUT have amplitude of ~1.7, ~2, and ~4, respectively
(there is therefore a modest level of quantiser overload). The sinewave is indeed seen to
be encoded in the density of 1s and -1s in the quantiser output. In this example, the input
is faithfully reproduced at the LPF output (apart from a delay or phase-shift, but as long as
this delay is constant over all frequencies in the signal band, it would not be a problem in
practice).

Increase the signal amplitude to sinamp=0.97 and rerun the simulation and then type
“Qout_SNDR”.

1. Note and comment on any changes in the integrator waveforms, output spectrum
and SNDR compared to those obtained with sinamp=0.707. Pay particular
attention to the integrator amplitudes and compare to those seen using MOD1. You
may wish to refer to sections 3.2 and 3.3 of [1] and recall the utility
“calc_quant_gain” from lab 1.

“Ballooning” can now be observed in INT2OUT (the magnitude of the signal exceeding 20
at times). This leads to significant quantiser overload (we recall that the non-overload
range of a binary quantiser is -2 -> +2). As a result, the quantiser becomes highly non-
linear (and its effective gain reduces), resulting in increased noise and distortion (as
reflected by a higher noise floor and more spurious peaks in the spectrum). The end result
is a 18dB drop in SQNR (or a loss of 3-bits of resolution).

Reset sinamp=0.707 and set modctrl.isat1=3 and modctrl.isat2=3. Rerun the simulation
and Qout_SNDR.

1. Note and comment on any changes in the integrator waveforms, output spectrum
and SNDR compared to those obtained with no integrator output swing limits. How
tolerant is MOD2 of integrator overload?
Whilst the time traces are relatively similar to the case of no integrator output limits, the
spectrum reveals the emergence of significant spurious peaks (pointing to increased
distortion and limit cycling), and a ~4dB drop in SQNR. Thus it can be argued that MOD2
is not tolerant of integrator saturation.

1.7 Sine Wave Amplitude Sweep

We will now study the signal to quantisation noise of MOD2 in response to a range of sine
wave amplitudes.

Close “sin_to_mod2.mdl” and any plot windows and set modctrl.isat1=inf, modctrl.isat2=inf
(again, it is a good idea to simply re-execute “init_vars” to reset all modulator control
variables) and target_modulator=’mod2’.

Run the routine “sweep_sin_ampl_sqnr”.

The sweep_testbench.mdl window will appear. After a short delay you will see a plot of
signal to quantisation noise ratio (SQNR) versus input amplitude in decibels relative to the
modulator full-scale input (dBFS), where 0 dBFS corresponds to sine wave amplitude = 1.

1. Note the peak value of SQNR and compare this to the theoretical SQNR from the
formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 (
)
2L + 1
where the modulator order L=2, the oversampling factor OSR=64, and number of
bits N=1.
 2. Why isn’t the peak SQNR achieved for maximum signal (0 dB)? What has
happened?
3. Compare the SQNR versus amplitude plot to that seen for MOD1 in lab 1.

The peak SQNR is observed to be ~71.5dB (achived at around -2dBFS or sin_amp=0.79).

The theoretical SQNR is 85.19. Hence the peak SQNR falls short of the theoretical value
by ~13dB. This is due to quantiser overload as the input amplitude approaches 1, leading
to reduced noise supression and increased distortion (more spurious spectral content
within the signal band) and hence a reduction in SQNR (or, more precisely, SNDR).

Compared with MOD1, the plot no longer “flat-lines” at low input amplitudes. In MOD1
there were idle tones preventing the reproduction of small input signals at the output. With
MOD2, this is no longer the case. The SQNR drops faster in MOD2 near full scale due to
massive quantiser overload.

Now try constraining the integrator outputs to observe the effect versus signal amplitude.

Set modctrl.isat1=2 and modctrl.isat2=2 in the Matlab Command Window and re-run the
simulation.

1. How does adding integrator output limits affect the amplitude plot? Is signal scaling
important if using MOD2?
SQNDR (dB)

The peak SQNR has reduced by more than 6dB and the plot shows an increased level of
fluctuation (indicating tonal behaviour at some amplitudes). Thus, signal scaling is
important in MOD2 (to ensure that the integrator output limits are not reached).
Reset the integrator limits to modctrl.isat1=inf and modctrl.isat2=inf.

Set the finite integrator gains to modctrl.igain1=10 and modctrl.igain2=10.

1. How has the SQNR graph changed (hint: think about the dc input dead-zones seen
earlier)? Is the modulator ever likely to be a good noise-shaping ADC with integrator
gains of only 10?
SQNDR (dB)

The dead zone resulting from the finite integrator gain causes a drastic drop in SQNR at
small signal amplitudes (< ~-40dBFS). There is also a drop of ~13dB in peak SQNR, due
to the reduced suppression of in-band quantisation noise. It is therefore likely that a MOD2
with integrator gains of only 10 would not be suitable ADC in practice.

1.8 Second Order Modulator Topology Comparison

In the LAB2 directory you will find a range of alternative second order delta-sigma
modulator implementations. These are discussed in the course text [1] in Chapter 3
section 3.4.

Reset all modulator parameters (isats, igains etc.) by typing “init_vars” and select one of
these modulators by typing, as appropriate for your choice:

target_modulator=’mod2_boserwooley”
target_modulator=’mod2_silvasteensgard”
target_modulator=’mod2_errorfeedback”

and use the Simulink test bench and Matlab scripts to examine the properties of these
modulators relative to MOD2.

1. Study the peak SQNR properties of these modulator topologies and compare to
basic MOD2 (you should also examine and comment on integrator output ranges
versus signal input range etc. and think about how practical this would make these
modulators to implement with real integrators)
 2. Investigate the reason why ’mod2_errorfeedback’ is never used in an analogue
implementation ([1] Chapter3, p82). There are some hint comments on the
modulator’s Simulink schematic.

The SQNR simulations of the three topologies give near identical results to the basic
MOD2. This is due to the underlying NTF being the same. The differences relate to the
size of the internal signals as well as to demands on the circuit implementation. To give
examples, the Silva-Steensgaard structure (a feedforward topology) is tolerant to non-
linearity in the integrator stages (as the input to these stages does not contain the input
signal u). Furthermore, the quantisation error can be directly obtained (from INT2OUT),
reducing circuit requirements for multi-stage modulators (see Lab 5). In Boser-Wooley, the
speed (slew rate) requirement on the stages is reduced (delaying integrators are used, so
they only need to settle individually within the sampling interval, rather than coupled
together), and the structure enables dynamic range scaling. By dynamic range scaling we
mean that the integrator outputs can be scaled to fit within a sensible range, rather than
being too small which results in thermal noise becoming significant or too large and hitting
the voltage rails.

If ’mod2_errorfeedback’ was used in an ADC, the loop filter would need to be implemented
in analogue electronics, and would require careful component matching to ensure the ‘-2’
coefficient is achieved precisely. Any mismatch would result in a deviation from the desired
MOD2 NTF, and reduced suppression of in-band quantisation noise.

Summarise the key features of these different architectures. You may wish to refer to the
comments in the course text [1].

1.9 Learning review

This laboratory expanded on the previous MOD1 laboratory by examining the properties of
the basic second order modulator MOD2 and some other implementations of second-order
modulators.

Compared to MOD1, you should have noticed that MOD2 behaves much more like an
ideal modulator than MOD1:

1. Tonal limit cycles are still seen for dc inputs, but the strong signal-band limit-cycle
behaviour seen with MOD1 was less apparent.
2. Related to the above, the modulator output spectrum for sine-wave inputs (and with
no quantiser dither) generally follows the shape of the NTF better, lacking the many
strong idle tones superimposed on the NTF that are usually seen with MOD1.
3. Considerably higher SQNRs can be achieved at a given OSR by MOD2.
 4. As there are now two integrators providing dc gain before the quantiser, dead zone
behaviour when using real integrators with finite dc gain is much improved over
MOD1.
5. Care must be taken to avoid integrator clipping in (all) real modulators if high SQNR
is to be achieved.

Consequently, unlike MOD1 which is plagued by non-ideal behaviours, basic MOD2 and
its variants, such as those examined in section 1.8 above, are commonly seen in practice.

Despite the good performance of MOD2 seen in this laboratory, achieving extremely high
SQNRs (e.g. >> 100 dB) may still require unacceptably high OSRs. Recall that for a given
signal bandwidth of interest (e.g. a 24 kHz audio band), increasing the OSR will increase
the speed that any analogue circuits in the modulator must operate at (e.g. for an OSR of
64 the audio modulator will be running at Fs = 24x2x64 = 3072 kHz). If the OSR
requirement becomes too high to achieve a SQNR target then the modulator design may
become unacceptable in other regards, such as:

• excessively high power consumption to achieve very fast integrator settling in

analogue modulators, or low adder delays in digital modulators.
• excessively high power consumption to achieve very low quantiser delays,
• often a sufficiently fast clock may not be available in the system and so a dedicated
modulator clock must then be generated, e.g. by adding a PLL with its associated
circuits costs and power requirements (the modulator clock requirement can be
further complicated by the fact that the modulator data must then synchronise to the
rest of the system, ideally without the further complication of needing sample rate
conversion if the modulator and system clocks do not have simple ratios such as
1:2, 1:1.5 etc.)
• in extreme cases the circuit speeds required to achieve the necessary OSR may
even exceed the various speeds limits for the medium in which the modulator is to
be realised (e.g. available MOS transistor fT and/or channel transit times in ICs).

In high SQNR applications, a higher order modulator such as a MOD3 (a topic for the next
laboratory) or MOD4 operating at moderate OSR can thus be a better solution than MOD2
operating at very OSR. However increasing the modulator order above 2 can bring other
problems such as possible modulator loop instability as each integrator adds further loop
phase, degrading phase margins (basic MOD3 will be seen to be completely unstable and
hence unusable). The next laboratory will examine some of these effects and different
approaches to successfully implementing third and higher order modulators.

References:
[1] Schreier, Temes: Understanding Delta-Sigma Data Converters, Wiley-Blackwell 2004.
 Sigma-Delta Data Converters
Laboratory Session 3
1.0 Objectives

This laboratory comprises 2 sets of exercises.

In the first set of exercises, we will study the properties of third order modulator topologies.
Modulators with noise-shaping order > 2 can be unstable for some or even all possible
inputs, usually displaying chaotic limit cycle behaviour unrelated to the input signal when
unstable. We will see that careful architecture selection for single-loop modulators, which
entails controlling the form of NTF to limit its maximum gain and hence noise levels in the
loop and using multi-bit quantisation can both be used to improve high order modulator
stability and increase the stable input range.

In laboratory 5 we will look at another approach to creating stable high-order modulators

based on cascading stable low-order modulators. You will refer back to many of the results
from this laboratory in laboratory 5, so you are strongly encouraged to keep good notes of
your results for this laboratory!

In the second set of exercises, you will learn how to use a widely-used, MATLAB-based
Sigma-Delta Toolbox to synthesise NTFs to meet a given SQNR target and then generate
coefficients for some generic higher order modulator structures capable of realising those
NTFs as circuits or code (like Simulink). This toolbox was written by one of the course text
authors (Schreier) and is described in depth in the text [1]. Four different modulator
structures are supported by the toolbox: Cascaded Integrators FeedBack (CIFB),
Cascaded Integrators FeedForward (CIFF), Cascaded Resonators FeedBack (CRFB),
Cascaded Resonators FeedForward (CRFF). See page 128-134 of [1] for a derivation and
analysis of these structures.

1.1 Setup

You may wish to consult the course textbook as you are following the laboratory,
“Understanding Delta Sigma Modulators” By R. Shreier and G. Temes, which is available
online at:
http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508

You should still have a copy of all the Matlab laboratory materials in a directory called
“EdUni” created at the start of Laboratory 1; if not then please consult the laboratory 1
hand-out for instructions on how to create this Matlab.

Change directory into this location by typing “cd EdUni”.

In this directory there are general utility routines:

sweep_testbench.mdl

In the directory “LAB3” there are a number of files that will be used in this exercise:

MakeModulator.m
mod3.mdl
mod3_4bit.slx
mod3_crff_1bit.mdl
mod3_crff_2bit.mdl
mod3_crff_3bit.mdl
mod3tb_cifb_1bit.mdl
mod3tb_cifb_2bit.mdl
mod3tb_cifb_3bit.mdl
mod3tb_cifb_3bitTBQ.mdl
mod3tb_ciff_2bit.mdl
mod3tb_crfb_2bit.mdl
mod3tb_crff_2bit.mdl
mod4tb_cifb_3bit.mdl
plotpoles.m

As in laboratory sessions 1 and 2, we will also require the utilities held in the directory
“ELEE11080_ROUTINES”.

The directory ‘delsig’ contains the toolbox files, which we will be using in this lab.

Note: The Sigma-Delta toolbox can be freely downloaded from The Mathworks website;
link below http://www.mathworks.co.uk/matlabcentral/fileexchange/19-delta-sigma-toolbox.

In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.

In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current

Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directories “LAB3” and “delsig”.

Type “init_vars3” into the Matlab Command Window. This routine sets the default values
for common variables used in the various forthcoming exercises (it is identical to “init_vars”
used in previous laboratories except it selects the Blackman-Harris window in the “psdctrl”
structure for computing power spectral densities. Do not use a Hann window in this
laboratory as the default settings will give SQNR estimates corrupted strongly by the
window skirts.)

You are now ready to begin the lab 3 exercises set 1.

1.2 Third Order Modulator Simulink Model

Fig. 1 mod3.mdl schematic

Right-click on “mod3.mdl” in “LAB3” and select “Open F4”. You should now see the third
order modulator schematic (MOD3) shown in Figure 1. This modulator is obtained from
MOD2 in the same way as MOD2 was derived from MOD1 – by replacing the quantiser
with another MOD1 – and consists of the following main elements:

1. Three non-delaying integrators each composed of a 1/z unit delay element in

feedback to an adder. Descending into any of the integrator blocks you will see a
gain block precedes the delay element and can represent any finite integrator gain
at dc, and a saturation block represents the clipping effect of, e.g., finite power
supply voltages or digital word lengths in real modulators. Further details were
given in the lab 1 notes. The integrators are the core blocks responsible for noise
shaping in the modulator.

2. A midrise quantiser. This is a single-bit quantiser with output states -1 and 1 as

described in the lab 1 notes and used in labs 1 and 2.

3. A delaying feedback loop from the quantiser output to the input, where the two
signals are subtracted and the error signal LOOPERR is applied to the integrator.
The delay in the feedback represents the time to quantise, sample and feed back
the integrator output – usually a single clock cycle.

4. A random dither source input scaled by a gain block modctrl.dgain1 (default 0: no

dither) applied at the input of the quantiser.

Notes:

The default sampling frequency, Fs, is chosen as 1MHz. The default oversampling ratio,
OSR, is 64. The signal band of interest extends to Fs/(2.OSR), i.e. from 0 Hz to 7812.5 Hz.

1.3 MOD3 Time Domain Operation for DC Input

We will now examine how the third order modulator sigma-delta ADC behaves with a DC
input. You may wish to compare with your results for MOD1 and MOD2 dc behaviour from
labs 1 and 2.

Close “mod3.mdl” then open “sweep_testbench.mdl” and right click on the block marked
“dut”. Edit “model reference parameters” to “mod3.mdl” and then double click on the block
to open the mod3.mdl schematic from within the test bench. Now double click on any one
of the small pairs of blue icons by each of the integrator or quantiser outputs to open the
time waveform viewer scope.

Set the DC input level to 0 by typing “input_dc = 0” into the Matlab command window or by
right clicking on the input_dc entry in the workspace pane and editing its value to 0.

Select the dc test source in the test bench by typing “swpctrl.select = 2” in the Matlab
Command Window and then run the simulation by selecting “Simulation > Start” or
pressing <ctrl>T in the “sweep_testbench.mdl” window (NOT in the “mod3.mdl” window).

You will see the integrator and quantiser outputs appear in the time scope window.

Click on autoscale (binoculars icon) to scale the integrator and quantiser waveforms.
 1. Does the quantiser output follow a repeating limit cycle as seen for MOD1 and
MOD2 with rational dc input levels (and no dither)?
2. Comment on the integrator outputs, in particular note their magnitudes and the
scales of the axes.
3. What does this tell you about the stability of this basic MOD3 modulator? Recall the
idea of BIBO (bounded input bounded output) stability – do the integrator outputs
appear bounded? So is the modulator stable?

No limit cycle is seen in the quantiser output. Observing the integrator outputs reveals the
modulator to be unstable: the amplitude of the outputs grows unboundedly.

Now, try re-running the simulation for a few other input levels for input_dc such as “–pi/10”
and “+0.4367”.

1. Can you find any input that doesn’t make the integrator outputs grow unboundedly?
So is this modulator stable, conditionally stable, or completely unstable? (Don’t
spend more than a minute or two on this, just try a few input levels and draw a quick
conclusion.)

The basic MOD3 modulauor is completely unstable, regardless the input.

We will not focus on the details of modulator stability during the laboratory, but after the
laboratory you are encouraged to read and try the material in Appendix 1 which explains
why this modulator is unstable; this appendix covers some very general concepts that
underpin most modulator stability/instability cases.
1.4 An Improved Third-order CRFF DSM Loop with DC Input

The previous exercise highlighted that basic MOD3 is completely unstable with dc inputs.
You should not be surprised to learn it is unstable with sine wave inputs (you could try this
later) or indeed any useful input signal. This does not mean however that all third and
higher order modulators are completely unstable. Various (sometimes heuristic)
techniques exist for creating (possibly) stable high order modulators, some of which, and
the reasons behind them, are covered in the lectures and course text.

Close the “mod3.mdl” window and the timescope if they are still open. You should still
have “sweep_testbench.mdl” open.

Now right click on “dut” in the “sweep_testbench.mdl” schematic and edit the model
reference parameters to “mod3_crff_1bit.mdl”.

Double click on the dut component to see the new modulator architecture, which is of the
type “CRFF” discussed in section 4.4 and appendix B of [1], and uses additional
feedforward paths to the quantiser input to modify the NTF to aid stability.

Note that integrators 1 and 3 are now delaying integrators; double click on integrators 1
and 2 to see their internal schematics and compare. Note also that compared to MOD3 the
feedback paths returns only to the first integrator input and has no delay.

This example uses architectural modification (the feedforward paths to the summer before
the quantiser) to change the loop NTF from

• NTF = (1-z-1)3 = (z-1)3 / z3 (basic MOD3)

to

• NTF = (z-1)3 / (z-0.5903)(z2 – 1.363z + 0.5792) (new modulator)

Note that the 3 NTF poles (highlighted in red) have been moved from all at z=0 to all
closer to z=1 for the new modulator. Note also that both NTFs still have the same 3 zeros
at dc (z=1) that are responsible for the 3rd-order noise shaping. Figure 2 compares the
magnitude responses of these NTFs.
Fig. 2 Comparison of the basic MOD3 and CRFF-modified MOD3 NTFs.

Two important differences between the NTF magnitude responses to note are:

• The maximum NTF gain (at Fs/2, i.e. at z=-1) is reduced to x1.71 (4.6 dB) from x8
(18 dB).
• The signal-band (low frequency) NTF is now 21dB higher than the basic MOD3
NTF.

Reducing the maximum gain reduces the level of high-frequency noise at the quantiser
input. High levels of quantiser input noise can badly saturate the quantiser and the
resulting change in effective quantiser gain can cause NTF poles outside the unit circle,
causing instability (see Appendix 1 for an illustration of this). Reducing the noise level can
thus enable stable operation.

The penalty for achieving stability is that while the new NTF has lower gain at high
frequencies, the gain is now 21 dB higher in the signal pass-band (exercise: now confirm
this 21 dB low-frequency NTF increase by hand calculation; you should be able to do it
very easily if you notice that the NTFs given above differ only in their denominators/poles -
so choose the right frequency to compare the NTF denominators at).

The ratio of the NTF is r=(z-0.5903)(z2 – 1.363z + 0.5792)/z3

Evaluating this at DC (z=1) gives r=(1-0.5903)(1-1.363 + 0.5792)=0.088577,

or expressed in decibels: r=20log10(0.088577)=-21.054dB -> MOD3 NTF is 21dB is lower

Since the signal-band NTF is 21 dB higher than MOD3’s then 21 dB more in-band
quantisation noise will result, i.e. SQNR for a given signal will be about 21 dB less than a
true (1-z-1)3 NTF modulator could achieve; this reduced maximum achievable SQNR is the
cost we pay here for achieving stability in our 3rd order modulator loop.
(Notes: Note that it is impossible to reduce the high-frequency NTF gain without
increasing the NTF gain at lower frequencies. This follows directly from the Gerzon-Craven
equal-areas theorem illustrated in Figure 3:

Fig. 3 Illustration of the equal areas theorem.

This theorem follows directly from a result from complex analysis showing that – on a log
gain axis – areas A and B must be equal for physically realizable noise transfer functions.
There is thus a fundamental trade-off between stability and achievable SQNR. Any attempt
to reduce high frequency NTF gain to aid stability will reduce area B and so area A must
reduce correspondingly. Area A can only reduce by raising the NTF curve towards 0 dB,
i.e. by having more quantisation noise at low frequencies and hence obtaining a lower
maximum possible SQNR.)

Double click on one of the blue timescope icons in “mod3_crff_1bit.mdl” to open the time
scope. Set “input_dc = 0” and then run the simulation by selecting “Simulation > Start” or
pressing <ctrl>T in the “sweep_testbench.mdl” window. Once the simulation completes
type “mean(Qout)” to see the mean/dc value of the modulator output and “Qout_SNDR” to
see the output spectrum.

1. Observe the integrator outputs. Are they now bounded? Is the modulator stable?
2. Compare the mean modulator output with input_dc? Are they a good match? Has
the modulator implemented a dc accurate analogue to digital conversion; i.e. what
sort of error do you see between input_dc and mean(Qout)?
3. Zoom in on a few cycles of Qout and look also at the output spectrum. Is this
modulator tonal for dc input 0 as seen with MOD2 and MOD1?
input_dc=0

Modulator output spectral density (Units/sqrt(Hz))

100 Simulated:
SQNR = -8.4 dB Brickwall LPF @ fs/(2.OSR)
ENOB = -1.7

10-5

10-10

10-15

10-20
101 102 103 104 105 106
Frequency(Hz)

The integrator outputs are now bounded, so the modulator is stable, and the mean
modulator output matched the input level (0) exactly. As with MOD1 and MOD2, the
behaviour is again tonal, with tones at 125KHz and 375kHz (however, just as with MOD1
and MOD2 the tones are well outside the signal band).
Repeat the above exercise for input_dc values from +0.2 to +0.6 in increments of 0.2 and
then to +1.0 in increments of 0.1.

1. Does the modulator stay stable for all inputs up to the maximum possible full-scale
limit of +1? If not then roughly what is the stable dc input range (do not try finding
this to high accuracy, +/- 0.05 is accurate enough)? Note the integrator output
signal ranges as the stable limit is approached. What happens to them?
2. Is the modulator an accurate converter for dc inputs inside the stable input range?
3. Is this modulator tonal for rational dc inputs in its stable input range (as seen for
MOD1 and MOD2 in previous labs)? How could you address this if it could be a
problem?

input_dc=0.2
input_dc=0.4
Unit/sqrt(Hz) input_dc=0.6
Unit/sqrt(Hz)
input_dc=0.7
input_dc=0.75
Unit/sqrt(Hz)
input_dc=0.8 (similar plots are obtained for input_dc=0.9)
Unit/sqrt(Hz)
input_dc=1

The modulator becomes unstable between input_dc=0.75 and input_dc=0.8, the amplitude
of INT3OUT growing rapidly as the stabe limit is approached. Within the stable input
range, the modulator is an accurate coverter for DC inputs (as far as the mean value of
Qout is concerned, however it is still possible to get in-band limit cycles for some input
levels, try, e.g., input_dc=0.01!). Just as with MOD1 and MOD2, certain rational DC inputs
will lead to in-band tones, so it is prudent to use some dither to avoid problem inputs (this
is in fact true for any modulator structure!).

We note that although the modulator appears to be stable for input_dc=1, in practice any
small disturbance (even thermal noise) would throw off the modulator and lead to the
integrator outputs becoming unbounded.

Recall from previous laboratories that for analogue modulators where the integrators may
have a finite dc gain “A”, MOD1 required very high gain to minimise dead zones (its dead
zone width is proportional to 1/A) and MOD2 was much more tolerant of low gains as the
two integrator gains are multiplied before the input reaches the quantiser (dead zone width
is proportional to 1/A2).

We will now examine the tolerance of our stable third-order modulator to dc gain.

Close all Simulink windows and type “target_modulator=’mod3_crff_1bit’” and then run
“sweep_dc_dc” to obtain a dc transfer function of the modulator for dc inputs around zero
with ideal integrators having infinite dc integrator gains (default settings from “init_vars3”).
Do not close this window for now and keep a copy of this transfer function plot for later.

Then set the dc gain of all integrators to 10 by typing “modctrl.igain1=10”,

“modctrl.igain2=10” and “modctrl.igain3=10” and then run “sweep_dc_dc” again and
compare the results. Again, please keep a copy of this plot.

1. Compare the dc transfer functions obtained with ideal integrators and integrators
with gain 10. Are any dead zones visible at the sweep resolution (steps of 0.001)? If
so then how do they compare with MOD1 and MOD2 with these integrator gains (if
you do not have these results in your lab book and need to re-run the MOD1 and
MOD2 results then remember to add LAB1 and LAB2 to your Matlab path and set
“target_modulator” to “’mod1’” or “’mod2’” before running “sweep_dc_dc”).
2. Note the width of the dead zone centred on dc input 0.
 Modulator dc transfer function around dc = 0.000
for modulator mod3c rff 1 bit

0.15

0.1
dc input (green) and output (red)

dc input (green) and output (red)

0.05

-0.05

-0.1

-0.15
-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1
dc input

IGAIN=inf IGAIN=10

The deadzones are considerably smaller than in the case of MOD1 and MOD2, only the
deadzone around input_dc=0 (with width 0.006) is readily visible, it is only when one
zooms into the plot that small deadzones (around simple rational inputs) can be seen.

Reduce the gain of all integrators identically from 9 to 4 in steps of -1 (i.e. gains 9,9,9 then
8,8,8 etc.) and note the widths of the dead zone around 0 input in each case.

1. What power of the gain does the width of the dead zone around input_dc=0 depend
on? Is this what you would expect intuitively?
2. Is achieving high enough dc integrator gain to supress dead zones likely to be a
major issue for real implementations of this type of third-order (or higher-order)
modulator design?

The width of the deadzone is seen to be (approximately) proportional to 1/A^3 (the power
of 3 arising from the order of the modulator). Thus the size of the dead zone will diminish
rapidly as A is increased and is likely to be insignificant for practical values of A.

1.5 CRFF Third-order Loop with Sine Wave input.

Close all Simulink windows except “sweep_testbench.mdl” (open it if it is not already open)
and ensure the Model Reference Parameter of dut is set to “mod3_crff_1bit.mdl”. Select
the sine wave input of “sweep_testbench.mdl” by typing “swpctrl.select = 1” in the Matlab
Command Window. As before, the workspace variable “sinamp” sets the amplitude of this
sine wave and “sinfreq” sets the frequency.
Reset all integrator gains to +inf (a quick way to do this is to execute “init_vars3” again in
the command window).

Set “sinamp = 0.1” and “sinfreq = 4882.8125” if they are not already set to these values.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window. Once complete, type “Qout_SNDR” in the Matlab
Command Window to see the modulator output spectrum and simulated SQNR.

1. Estimate the slope of the output spectrum in the passband? Is this what you would
expect? Why?
2. Note the reported signal to noise ratio given by “Qout_SNDR” and compare it to the
theoretical maximum given by the formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 (
)
2L + 1
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=1.
→ Recall that this is the theoretical SQNR for a full-scale input sinamp = 1 (i.e. 0
dB). We have used sinamp = 0.1 (-20 dB), so modify your calculation appropriately
when comparing.
→ Recall also the comment at the start of section 1.4 about the 21 dB passband
penalty incurred by modifying the NTF to achieve stability and note that the above
formula applies only for a (1-z-1)L NTF.
3. How does the simulated SQNR compare with those obtained previously for MOD2
and MOD1? Does this modulator give worse, comparable, improved, or much
improved SQNR at this OSR?

Modulator output spectral density (Units/sqrt(Hz))

100
Simulated:
10-2 SQNR = 70.7 dB Brickwall LPF @ fs/(2.OSR)
ENOB = 11.4
10-4

10-6

10-8

10-10

10-12

10-14
101 102 103 104 105 106
Frequency(Hz)

Slope in the passband is 60dB/dec, which is consistent with the order of the modulator
(3×20=60dB/dec for a 3rd order modulator).
The SQNR predicted by theory is 112.8dB-20dB-21.1dB = 71.1dB (which is very close to
the 70.7dB observed in the above simulation).

Note that the SQNR is 18dB higher than what we saw with MOD1, and similar to that for
MOD2, despite the input amplitude being 17dB lower.

Repeat the above exercise for “sinamp = 0.8”.

1. Explain your result. You may wish to look at the time domain waveforms using the
time scope (double-click on dut and then the blue icons as before then re-run) and
comment on the integrator outputs.
Modulator output spectral density (Units/sqrt(Hz))
100

Simulated:
10-1
SQNR = -23.9 dB Brickwall LPF @ fs/(2.OSR)
ENOB = -4.3
10-2
Unit/sqrt(Hz)

10-3

10-4

10-5

10-6
101 102 103 104 105 106
Frequency(Hz)
The SQNR has collapsed as the modulator has become unstable, due to sinamp=0.8
being beyond the modulator’s stable input range.

Close all windows and type “target_modulator = ‘mod3_crff_1bit’” in the Matlab Command
Window.

Obtain a plot of SQNR versus input amplitude by running “sweep_sin_ampl_sqnr”. You

should make a copy of this plot for reference in the next section.

1. Note the amplitude giving maximum SQNR and compare this to the maximum
stable dc_input. Are they roughly the same? Would you expect this, i.e. is the
maximum stable dc input generally a good indicator of the maximum stable sine
amplitude?
2. Make a note of the maximum SQNR value.
The amplitude giving maximum SQNR is -5dBFS = 10^(-5/20) = 0.56. This is somewhat
below the maximum stable sine amplitude of 10^(-3/20) = 0.707, which is in turn consistent
with the maximum stable dc input identified in section 1.4 above (this is not surprising: as
soon as the instantaneous value of an input sinewave exceeds the stable dc input, then
instability is expected to occur). The maximum SQNR is 84.9dB.

1.6 CRFF Third-Order Loop with Multi-bit Quantisation.

The previous exercises examined stability issues in high-order loops and demonstrated
how a stable 3rd order modulator could be constructed by using different loop architectures
than basic MOD3; in this case a “CRFF” architecture. However, this CRFF modulator is
only stable for inputs in the range of (approximately) [-0.7:0.7]. One other way we can
often further improve loop stability and extend the stable input range is to progress from
using a single-bit quantiser and feedback path to multi-bit quantisation and feedback.
Multi-bit quantisers have better defined gain than single-bit quantisers as more than 2
points define the slope of the quantiser input/output characteristic (i.e. effective gain); you
may recall this from the quantiser gain exercises from lab 1 if you had time to try them.
See also sections 2.1.1 and 6.1 of [1].

Close the Simulink windows from the previous section except for “sweep_testbench.mdl”
and the output of “sweep_sin_ampl_sqnr” (or, better, make a hard copy of it as you will
need to refer back to it shortly).

Right click on “dut” in “sweep_testbench.mdl” and edit the model reference parameters to
“mod3_crff_2bit.mdl”.

Double click on the dut to see the modulator schematic. This looks the same as in the
previous exercise, but now the 1-bit quantiser with output step size 2 (-1 to +1) has been
replace with a 2-bit quantiser with step size 2/3 (switching thresholds -2/3, 0 and +2/3 and
output levels -1, -1/3, +1/3 and +1). You can double-click on the quantiser to see what has
been changed.

Double click on any of the blue icons to open the time scope for the integrator and
quantiser outputs.

Reset the sine wave and dc inputs by typing “sinfreq = 4882.8125”, “sinamp = 0.707” and
“input_dc = 0” and then run the simulation by selecting “Simulation > Start” or pressing
<ctrl>T in the “sweep_testbench.mdl” window.

Type “Qout_SNDR” to see the modulator output spectrum. Use the magnifying glass to
zoom in on the 2-bit quantiser output in the time-scope view and note how it resembles the
sine wave much more obviously than in the 1-bit case.

1. Estimate and comment on the slope of the SQNR graph; is it still what you would
expect?
2. Note the reported signal to noise ratio given by “Qout_SNDR” and compare it to the
theoretical maximum given by the formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 ()
2L + 1
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=2. Recall that this is the theoretical OSR for a full-scale input sinamp = 1
(0dB). We have used sinamp = 0.707 (-3 dB), so modify your calculation
 appropriately when comparing and again recall the NTF penalty comment from
earlier.

The slope of the spectrum in the passband is still ≈60dB/dec, as expected (given that the
order of the modulator has not changed).

The SQNR predicted by theory is 118.9dB-3dB-21.1dB = 94.8dB (which is similar to the

96.6dB observed in the above simulation, the small discrepancy could be due to
inaccuracies in the simulated spectrum and extraction of SQNR).

Close all Simulink windows and obtain a plot of SQNR versus input amplitude by typing
“target_modulator=’mod3_crff_2bit’” and then running “sweep_sin_ampl_sqnr”. Compare
your results with those obtained for the 1-bit quantisation case.

1. What is the maximum SQNR level? How does this compare with the 1-bit case?
2. At what amplitude is the maximum SQNR obtained? Has the stable input range
improved compared to the CRFF with 1-bit quantisation?
3. Compare the SQNR of the 1-bit and 2-bit modulators for a selection of inputs within
their stable ranges, e.g. -10, -30 and -40 dB relative to full-scale (dBFS). Are they
the same? Has adding the extra quantiser bit only extended the 1-bit plot to higher
stable inputs, or has it also improved SQNR for all inputs? If so then why would this
happen (don’t spend too long on this, ask a demonstrator for comment)?
SQNDR (dB)

The max SQNR is 97.7dB, compared with 84.9dB in the 1-bit case. This increase is
greater than the 6.02dB increase expected by adding a single bit to the quantiser (and the
resulting reduction in step size), due to the stable input range having been expanded.
The amplitude giving maximum SQNR is now -2dBFS = 10^(-2/20) = 0.79, and the
maximum stable sine amplitude is at least 10^(-1/20) = 0.89 (c.f. 0.707 in 1-bit case).

The SQNR has improved for all input amplitudes (by around 10dB for most of the input
range).

Now select a 3-bit (8 levels) quantiser by typing “target_modulator = ‘mod3_crff_3bit’”, this

has a quantiser with equally spaced input switching thresholds at (-6/7, -4/7, -2/7, 0, 2/7,
4/7, 6/7) and outputs levels (-1, -5/7, -3/7, -1/7, 1/7, 3/7, 5/7, 1).

Re-run the sweep “sweep_sin_ampl_sqnr” and compare with the 1-bit and 2-bit
quantisation cases.

Open “sweep_testbench.mdl” if it is not already open. Set “sinamp = 0.95” and double click
on dut in “sweep_testbench.mdl” and then double click any of the blue icons to activate the
time scope. Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window.

1. How far does the stable input range extend now compared to the 1-bit and 2-bit
modulators?
2. How does the peak SQNR for the modulator with a 3-bit quantiser compare with that
estimated using the formula
π 2L
) ?
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 (
2L + 1
Remember to account for the NTF penalty and the signal amplitude at peak SQNR.
3. How does the SQNR versus amplitude plot compare with the 1-bit and 2-bit cases?
Explain the differences.
4. Zoom in on a few cycles of “quantout” in the time-scope for sinamp = 0.95. Can you
see how this 3-bit DSM tracks even more closely the large input sine wave using all
8 quantiser levels?
SQNDR (dB)
The modulator is now stable for sine amplitudes up to 1 (it is only barely stable at 1), peak
SQNR being achieved at an amplitude of around 10^(-1/20) = 0.89.

The SQNR predicted by theory is 124.9dB-1dB-21.1dB = 102.8dB (which is broadly similar

to the 107.4dB observed in the above simulation, the discrepancy could be due to
inaccuracies in the simulated spectrum and extraction of SQNR).

Compared to the 2-bit case, not only has the stable input range being extended, the SQNR
has been raised for all input amplitudes (by an amount commensurate with the 6.02dB
gain expected from the additional bit of resolution added to quantiser).

The shape of the quantiser output now follows the input a lot more closely then before.
The loop error is substantially reduced, as reflected by the lower INTOUT waveforms.
Even at sinamp=0.95, quantiser overload is avoided.

2.0 Sigma-Delta Toolbox

This directory (delsig) has been included in the archive downloaded earlier.

Type “clear” into the Matlab Command Window to clear all variables from the previous
exercises.

Type “init_vars3” into the Matlab Command Window. This routine sets the default values
for common variables used in the various forthcoming exercises.

You are now ready to begin part 2.

We have seen in the first part of this laboratory that stable 3rd (and higher) order
modulators can be implemented with judicious choice of loop architecture to achieve
stability. A natural question that thus arises is “how can I choose/design a loop architecture
for my high-order modulator?” Traditionally this has been something of a skill, requiring
experience in analysing and trying many possible architectures to find ones that work best.
We will not discuss hand-design of modulator loops in this course, but basically it involves
choosing a candidate filter type, such as a Butterworth high-pass filter for the modulator
open-loop filter response, and then trying to locate its poles and zeros to achieve the
desired stability/SQNR trade-off for the closed-loop NTF. Some additional considerations
are also needed, such as scaling the open-loop transfer function to ensure the NTF
impulse response has h(0) = 1; this is a key physical realisability requirement for NTFs –
see page 96 of [1] and Appendix 1.

Luckily, much of the hard work can now be performed using a (very popular and widely-
used) Matlab toolbox utility which allows users to implement a useful range of high-order
loop types and reports key performance parameters such as stable input range.

The Sigma-Delta toolbox is a utility which can be used to synthesize complex Nth order
modulator structures using Matlab without the need of doing any mathematical analysis by
hand. The toolbox has many capabilities as listed below:

 Discrete time modulator design

 Continuous time modulator design
 Quadrature modulator design
 Low pass and Band pass modulators
 Supports 6 different loop filter types
 Synthesize coefficients for all these loop filters
 Simulate and analyse the modulator NTF synthesized

In this lab we are going to use the toolbox to generate coefficients for discrete time
modulators similar to the ones we have been using in previous labs, so we will not cover
toolbox functions needed to do design/analyse other types of modulators. However the
interested student can consult Chapter 8 and Appendix B, page 391-392 of [1], which lists
key toolbox functions.

When starting a new modulator design, the empirical results given in figures 4.14, 4.15
and 4.16 on pages 112-113 of [1] provide very useful guidelines for getting a feel for OSR,
order and quantiser levels you should be considering for your modulator design.

2.1 Third Order CIFB Modulator Synthesis

We will design a 3rd order modulator with 1-bit quantiser and 64x oversampling ratio. From
Figure 4-14 in [1], this should give us a (maximum possible) SQNR ≈ 95 dB. We will
define these parameters as variables in Matlab workspace which will be used by toolbox
functions throughout the lab.

Step-[3] In the Matlab command line, type and enter following toolbox variables:

Order = 3
nLev = 2
OSR = 64
form = ‘CIFB’

‘Order’ defines the order of the modulator, ‘nLev’ defines the number of quantiser levels
(which is 2 for 1-bit/binary quantiser), OSR = Oversampling Ratio and Form defines the
modulator structure to be realised, taking values ‘CIFB’, ‘CIFF’, ‘CRFB’, ‘CIFB’ as
described in [1].

Now we can synthesize the NTF of the modulator using the toolbox function
‘synthesizeNTF()’

synthesizeNTF() needs following input parameters to generate a NTF:

1. Order of the modulator (already defined by Order).

2. Oversampling ratio OSR (already defined by OSR).
3. The parameter Opt enables optimized zero placement (section 4.3.1, page 107 [1]).
The default value Opt = 0 will place all zeros of the NTF at dc (z=1). Setting Opt =1
will distribute zeros throughout the baseband of the NTF to increase SQNR; we will
study an example of this later.
4. H_inf defines the maximum out of band gain of the NTF. The default value is H_inf
= 1.5 (see the Lee Criterion in section 4.2.1 of [1]).
5. F0 is the centre frequency for band pass modulators. The default value is 0 Hz for
lowpass modulators.

Step-[4] To synthesize the NTF, in the Matlab command window type:

H = synthesizeNTF(Order,OSR)

H=

(z-1)^3
----------------------------------
(z-0.6694) (z^2 - 1.531z + 0.6639)

Matlab will display the synthesised NTF in the Command Window and the Matlab variable
H holds the synthesized NTF in zero/pole/gain (ZPK) format.

Note that the NTF numerator is (z-1)3 corresponding to 3 NTF zeros at dc (z=1). We would
expect 3 NTF zeros for a 3rd-order lowpass modulator (we will see shortly that they need
not all be at dc and there are some advantages to moving some zeros slightly away from
dc). Note too that the poles are not all at z=0 - as was the case for the (unstable) basic
MOD3 - but are now in the right-hand plane, i.e. closer to z=1 to again reduce the high-
frequency NTF gain (and increase the low-frequency NTF gain).

We have not defined other parameters required by this function (Opt, H_inf, F0); if not
defined then default values shown above will be used by the function.

Once the NTF is synthesized, there are options to simulate and analyse the NTF using
toolbox functions given in Appendix B of [1]. However we will not dwell long on these
functions in this exercise since we already have a set of routines to do the analysis inside
the ‘ELEE11080_ROUTINES’ directory.

Synthesizing a NTF is usually the first step in creating a circuit implementation of a

modulator having that NTF. Many ways exist to do this and the toolbox supports
realisations using four popular structures; see Appendix B and in particular pages 410-415
of [1]:
Cascaded Integrators FeedBack (CIFB)
Cascaded Integrators FeedForward (CIFF)
Cascaded Resonators FeedBack (CRFB)
Cascaded Resonators FeedForward (CRFF)

To implement a given NTF using any of the architectures shown on pages 412-415 of [1],
it is necessary to find appropriate values for the parameters shown on these figures (a1,
a2, …, b1, b2, …, c1, c2, …, g1, etc.) to realise the synthesised NTF. The toolbox function
realizeNTF() can be used to find values for these parameters:

realizeNTF() receives following parameters:

1. H, which is the NTF in ZPK format.

2. Form, which is the type of the modulator (CIFB, CIFF, CRFB or CRFF).
3. stf is a custom STF in ZPK format. In this exercise we will not set this parameter;
synthesizeNTF() then assumes the STF to be 1.

and outputs variables which represent the coefficients of the target modulator structure as
shown on pages 412-415 of [1]:

1. Matrix a represents feedback coefficients from the quantiser to the integrators.

2. Matrix b represents feedforward coefficients from the input to the integrators.
3. Matrix c represents forward path coefficients between integrators
4. Matrix g represents resonator coefficients for finite NTF zeros

Step-[5] In Matlab type the following command to obtain the modulator coefficients using
realizeNTF():

[a g b c] = realizeNTF(H,form)

a=

0.043983 0.28814 0.79974

g=

b=

0.043983 0.28814 0.79974 1

c=

1 1 1

Matrices a, g, b and c are displayed in the Matlab command window. The a, b, and c
matrices each have 3 elements and in this case g has only one coefficient set to zero as
there is no resonator loop and so all NTF zeros are at dc (Opt = 0). All the c coefficients
are 1 as dynamic range scaling has not yet been performed.
Coefficients returned by realizeNTF() are those of an unscaled modulator. An unscaled
modulator may have large integrator output swings and these must be rescaled to suitable
amplitudes to facilitate real implementation of the modulator (e.g. to avoid integrator
saturation). The scaling also must not change the STF or NTF. This is known as Dynamic
Range Scaling. See page 268-270 of [1] for more details about dynamic range scaling.

The toolbox provides functions for implementing dynamic range scaling, but they do not
operate directly on the [a g b c] matrices, instead they require the modulator to be
described using an ABCD state-space representation of the loop filter. The ABCD matrix is
built using the a, g, b and c matrices in a way that also encapsulates how the coefficients
interact inside the modulator to create the next quantiser output and integrator output
states from the present states and modulator input; see section 8.3.1in [1] for details and
also the end of the Matlab command file “simulateDSM.m” in “delsig”. The toolbox
simulates all modulators using ABCD state-space representations.

The toolbox function scaleABCD() can be used to set scaling factors for each stage in the
modulator to set the integrator signal ranges. scaleABCD() receives input in ABCD matrix
form and outputs a scaled ABCD state-space description of the modulator.

To enable use of scaleABCD(), the unscaled coefficients [a,g,b,c] generated earlier must
first be converted to ABCD format using the function stuffABCD().

Step-[6] To convert [a,g,b,c] to ABCD matrix form, type the following in command in the
Matlab Command Window:

ABCD = stuffABCD(a,g,b,c,form)

ABCD =

1 0 0 0.043983 -0.043983
1 1 0 0.28814 -0.28814
0 1 1 0.79974 -0.79974
0 0 1 1 0

1. Note that one of the D matrix entries (bottom right corner of ABCD, see [1] page
410) is always zero. Why is this? (Hint: what would happen if y(k) = v(k) was
possible, i.e. if the quantiser output could propagate back around the loop to the
quantiser input with zero propagation delay?)

The coefficient in question would represent a direct path (with no delay) from the quantiser
output to the quantiser input, making the modulator unrealisable (any change in the output
of the quantiser would immediately change the input to the quantiser, making the
behaviour of the modulator indeterministic).

Step-[7] Now dynamic range scaling can be applied. This is achieved by simulating the
modulator inside the toolbox to find the integrator ranges and then applying suitable
dynamic range scaling to adjust their ranges. A side-effect of this simulation is that the
maximum stable input range is also estimated.

In the Matlab Command Window type and execute the following command:

[ABCDscaled umax] = scaleABCD(ABCD,nLev)

xlim =

1 1 1

ABCDscaled =

1 0 0 0.36365 -0.36365
0.11056 1 0 0.26339 -0.26339
0 0.3631 1 0.26545 -0.26545
0 0 3.0128 1 0

umax =

0.74667

scaleABCD() returns the scaled ABCD matrix and umax, the maximum possible input to
the modulator, estimated using simulation (the toolbox uses optimised Matlab, so can do
all this simulation very quickly). Function scaleABCD() also takes in some optional
parameters, see described in more detail on page 402 of [1].

Compare the matrices ABCD and ABCDscaled to see the differences due to scaling.

The scaled ABCD matrix can be transformed back to coefficients suitable for circuit
realisation (i.e. a, g, b and c coefficients suitable to plug into the standard form modulators)
using the mapABCD() function.

Step-[8] To convert the scaled ABCD matrix back to [a,g,b,c] coefficients, type and
execute the following in the Matlab command window:

[a g b c] = mapABCD(ABCDscaled,form)

a=

0.36365 0.26339 0.26545

g=

b=

0.36365 0.26339 0.26545 1

c=

0.11056 0.3631 3.0128

The output from mapABCD() will be used directly in the Simulink .mdl files in the LAB3
directory for each modulator form.

2.2 Third Order CIFB Modulator Simulink Simulation

We can simulate the synthesized modulators using the routines we used in labs 1 and 2.

In the last exercises we synthesized coefficients for a 3rd order CIFB structure with a 2
level (1-bit) quantiser. A Simulink model for this structure is in the model
‘mod3tb_cifb_1bit.mdl’ in the LAB3 directory.

Step-[9] Open ‘sweep_testbench.mdl’ and set Model reference parameter of ‘dut’ block to
‘mod3tb_cifb_1bit.mdl’. Also set target_modulator variable to ‘mod3tb_cifb_1bit’.

init_vars3 executed earlier sets sinamp to 0.707 (note that umax was estimated as ≈ 0.75
by the toolbox, so this is within the stable input range) and sinfreq to 4882.8125 Hz. If they
have been changed then reset them to these values now (you may wish to re-execute
“init_vars3”).

Repeat step [5] from earlier to get unscaled [a g b c] coefficients.

Set swpctrl.select = 1 in Matlab command window to enable sinusoid input for test bench.
Run the simulation by selecting “Simulation > Start” or by keystroke Ctrl+T in the
“sweep_testbench.mdl” window.

Type “Qout_SNDR” in the Matlab Command window to see the simulated SQNR for the
modulator implemented using unscaled coefficients. Make a copy of your result.

Type “integ_stats(INT1OUT)” to observe the range of signals at the first integrator output.
Repeat this for INT2OUT and INT3OUT. Keep copies of your results.

Now repeat steps [6-8] to get scaled [a g b c] coefficients and re-run the simulation. Use
integ_stats() to get the integrator signal statistics after scaling.

1. Compare the scaled integrator signal ranges with the unscaled integrator signal
ranges.
2. Check that the scaled integrator outputs been scaled to stay within the range -1 to
+1 (the default for scaleABCD() unless otherwise specified).

Type “Qout_SNDR” in the Matlab Command window to see modulator output spectrum
and simulated SQNR for the modulator with scaled coefficients.

1. Observe the SQNR and compare it with other third order structures from LAB3 and
the estimated maximum possible SQNR from figure 4.14 in [1].
2. Compare the SQNR for the scaled and unscaled modulators. Explain your results.
Unscaled coefficients
Modulator output spectral density (Units/sqrt(Hz))
10 0
Simulated:
SQNR = 82.1 dB Brickwall LPF @ fs/(2.OSR)
10-2
ENOB = 13.3

10-4

10-6

10-8

10-10

10-12
101 102 103 10 4 10 5 106
Frequency(Hz)

Scaled coefficients
Unit/sqrt(Hz)

Output summary for integrator INT3OUT

MAX = 0.418
0.045
MIN = -0.427
0.04 mean = -0.001
std dev = 0.153
0.035

0.03

0.025

0.02

0.015

0.01

0.005

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Integrator output range (split into 50 bins)

With the scaled coefficients, the range of integrator outputs fills a good proportion of the -1
to +1 range, and the integrator outputs stay within the -1 to +1 range. On the other hand,
for the case of unscaled coefficients, the output range for INT1 is too small (which means
that thermal noise may become an issue, whist INT3 exceeds the -1 to +1 range, which
may in practice (for a circuit implementation) lead to integrator saturation (and a drop in
SQNR). We note that the SQNR plots are identical in both cases, because dynamic range
scaling has no effect on the modulator NTF.
The max SQNR is similar to that achieved by the 3rd order CRFF with 1-bit quantiser in
section 1.5 above, but lower than the best possible SQNR with a 3rd, 1-bit quantiser, as the
NTF zeros have not been optimised yet (but are at DC).

Step-[10] To obtain a plot of SQNR versus input amplitude for the synthesized modulator
with scaled coefficients, first type target_modulator=’mod3tb_cifb_1bit’ and then run
“sweep_sin_ampl_sqnr”.

1. How does the Amplitude vs SQNR plot compare with that seen earlier for
mod3_crff_1bit?
Signal-to-quantisation-noise-and-distortion versus 4883 Hz sine input amplitude
for modulator mod3tb cifb1 bit

100

80
X -3
Y 82.4817
60
SQNDR (dB)

40

20

-20

-40
-60 -50 -40 -30 -20 -10 0
Input amplitude (dBFS)

The SQNR plots are very similar.

2.3 Third Order CIFB Modulator toolbox Simulation

It is also possible to use the sigma-delta toolbox to perform simulation and analysis of the
NTF.

Type the following commands into the Matlab command window:

[snr_pred amp]=predictSNR(H,OSR)
plot(amp,snr_pred)
[snr amp]=simulateSNR(H,OSR)
plot(amp,snr)
SQNR

Predicted Simulated

Toolbox function predictSNR() predicts the ideal SQNR versus amplitude based on a
theoretical method that applies only for modulators with binary quantisers.
The function simulateSNR() performs actual transient simulation of the modulator to find
SQNR versus amplitude; this is done in essentially the same manner as
ELEE11080_ROUTINES function “sweep_sin_ampl_sqnr”, but using ABCD format and
optimised Matlab (i.e. not Simulink) for speed.

Both functions return 2 arrays containing the test input amplitudes and the corresponding
predicted/simulated SQNR at each amplitude. 0 dB is always set to be the maximum
possible input level based on the biggest possible DAC feedback level (which depends on
nLev – see the warning note later).

Compare these plots with the plot obtained from Step 10 above. In general, we favour the
use of Simulink to perform such steps as it is easier to observe internal modulator signals
and study non-idealities such as finite integrator gain and saturation.

The SQNR plots provided by the toolbox are similar to that obtained with Simulink

2.4 Visualising the NTF poles and zeros

Additional toolbox commands such as plotPZ() are useful to observe pole and zero
positions of the NTF in ZPK format.

To plot poles and zeros of NTF (‘H’ in ZPK form) execute following command in the Matlab
command window:

plotPZ(H)

1. Note that the circles representing NTF zeros are all at z=1, i.e. at dc.
2. Note all the poles are positioned not at z=0 (as was the case for basic/ideal MOD3)
but closer to z=1 to reduce high-frequency NTF gain to aid stability.

2.5 NTF zeros optimisation

We can further improve the SQNR by optimised NTF zero placement as described in
section 4.3 of [1]. Optimisation entails creating resonator loops within the loop filter (by
having non-zero g coefficients) to move some of the NTF zeros slightly away from z=1 so
that they are spread throughout the signal-band defined by the OSR and not just at dc.
This allows better suppression of quantisation noise throughout the entire signal-band to
achieve higher SQNRs. Follow the steps below to achieve zero optimisation:
To optimize the NTF by introducing zeros on the unit circle, re-run the synthesizeNTF()
command (step [4]) as shown below in the Matlab Command window:

H = synthesizeNTF(Order,OSR,1)

The additional “1” parameter enables zero placement optimisation.

H=

(z-1) (z^2 - 1.999z + 1)

---------------------------------
(z-0.6692) (z^2 - 1.53z + 0.6637)

1. Note the zeros of the NTF reported by synthesizeNTF(). Are they now all at z=1?

zero(H)

ans =

1+ 0i
0.99928 + 0.038014i
0.99928 - 0.038014i

Plot the poles and zeros of NTF (‘H’ in ZPK form) by executing the following command in
Matlab command window:

plotPZ(H)
1

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1
-1 -0.5 0 0.5 1

Zoom in to observe the zeros on the right hand side of the unit circle.

1. What frequencies are the zeros at? Are the zeros inside or outside the signal band?

To get a quick estimate of the zero frequencies, note that the zeros are roughly at
z=1+/-0.04j and that the unit-circle arc from z=1 to z=-1 (representing all real
frequencies from dc to Fs/2) has length π. You will check your prediction later when
plotting the modulator noise spectrum.

The angle corresponding to the complex zeros is angle(0.99928+0.038014i)=0.038rad,

which corresponds to a frequency of 0.038/pi*Fs/2=0.006Fs = 6kHz (which is inside the
signal band).
Now re-execute steps [5 – 8] above to create a 3rd order CIFB modulator with optimised
NTF zeros and scaled coefficients.

a=

0.40275 0.30442 0.30764

g=

0.0039857

b=

0.40275 0.30442 0.30764 1

c=

0.11603 0.36256 2.6018

Note that the coefficient of g is very small compared to the other a, b and c values. This
can be difficult to realise in some analogue forms (e.g. requiring a capacitor much smaller
than the minimum capacitor unit size in integrated switched capacitor implementations)
and so you should check SQNR sensitivity to “suitably large” (judgment required)
variations of g.

To see clearly the effects of the zeros on the modulator noise and SQNR, we first need to
increase the spectral resolution of our PSDs.

In the Matlab Command Window, type:

sinamp = 0.707;
swpctrl.trantime = 0.5;
psdctrl.framesize = 65536;

Then run the simulation by selecting “Simulation > Start” or by keystroke Ctrl+T in the
“sweep_testbench.mdl” window (open it if you need to).

Type “Qout_SNDR” in the Matlab Command window to see modulator output spectrum
and simulated SQNR.

Generate a plot of SQNR versus input amplitude by running “sweep_sin_ampl_sqnr”

1. Note the dip in the in-band spectrum due the NTF zero close to passband edge. Is
the frequency of this notch where you estimated the zeros to be earlier?
2. Compare the SQNR versus amplitude plots with and without optimised zeros.
Unit/sqrt(Hz)

The dip is indeed at f≈6KHz are estimated above.

The max SQNR has increased by 7dB through the optimalisation of NTF zeros.

Make a (gross) +50% change in coefficient g by typing “g = 1.5*g”. Remember that it may
be tricky to implement g accurately in some analogue modulators.

Run the simulation by selecting “Simulation > Start” or by keystroke Ctrl+T in the
“sweep_testbench.mdl” window.

Type “Qout_SNDR” in the Matlab Command window to see modulator output spectrum
and simulated SQNR.

1. Observe the shift in the zero position and the change in SNDR and peak SQNR
before and after the change in the coefficient g. Has the SQNR changed by much?
Note: remember to set the sinewave amplitude back to sinamp = 0.707
Unit/sqrt(Hz)

The effect of the +50% change in ‘g’ is relatively modest: the zero position is shifted
to~7.4kHz, the SQNR drops by 3.4dB.
2.6 Additional modulator test benches provided

Some additional modulator Simulink schematics have been provided for you to experiment
with in conjunction with the toolbox. Open and explore different .mdl files in the directory
‘LAB3’.

NOTE – TOOLBOX QUANTISER AND DYNAMIC RANGE SCALING

Be aware that the toolbox uses a multi-level quantiser style that is different from the multi-
level quantiser style used earlier, and this should be accounted for when scaling signal
ranges.

The quantisers used in earlier Simulink exercises had fixed output ranges of [-1,+1] and
additional quantisation levels for multi-bit quantisers were added by shrinking the
quantisation step size (LSB), ∆, so that all levels resided within the [-1,+1] range. This is
arguably reflective of what would happen in circuit implementation practice; the supply
voltage limits the maximum signal ranges and so a smaller LSB size is necessary if more
quantisation levels are needed. Since the quantiser output is fed-back directly to the
modulator input (the implicit feedback DAC in our Simulink models has a gain of 1) then
the maximum possible stable input range is [-1,+1]; the loop cannot provide enough
feedback to give zero steady-state loop error for larger inputs.

By contrast, the toolbox quantiser always has step-size ∆=2 and thus its output range
increases as the number of quantisation levels increases; see page 411 of [1]. The
modulator maxim possible input range (as set by the maximum DAC feedback levels)
becomes [ -(nLev-1), (nLev-1) ] when using the toolbox quantiser. For example:

• You will notice that the reported stable input range (umax) from scaleABCD()
increases correspondingly for nLev > 2.
• Note also the comment at the top of “simulateSNR.m” in the “delsig” directory about
the size of a 0 dB (i.e. full-scale) input sine-wave being defined in terms of nLev.

If you use the default integrator range scaling (+/-1) in scaleABCD() then you may need to
do additional coefficient scaling to convert a multi-bit toolbox design to one using the [-1,
+1] output range quantiser type. This is because the input and output ranges may be much
larger than the integrator ranges if nLev > 2 but default +/-1 integrator scaling is used.

For example, scaleABCD() with a 3-bit quantiser (nLev = 8) might report a stable input
range (umax) of [-6, +6] even though the integrators are scaled to a [-1, +1] range. If you
then implement your synthesized modulator using the [-1, +1] quantiser then the modulator
stable input range will scale to [-6/7, +6/7] (good) but all the integrator outputs will also
shrink to the range [-1/7, +1/7] (not so good). We have seen earlier that integrator
saturation is to be strenuously avoided, but there are circuit implementation disadvantages
to making the integrator output ranges too small. For example, in analogue circuits the
integrator feedback capacitors will become large and take more chip area (i.e. cost), and
the quantiser input capacitors may be tricky to implement due to large capacitor size ratios
being needed. Generally you should scale the integrator outputs to be as large as is safe
to do so (i.e. keeping just enough margin to avoid integrator saturation over anticipated
circuit operating variations).

Some suggested ways to proceed with synthesizing multi-bit designs via the toolbox to use
the [-1, +1] output range quantiser are:
 1. (Not recommended) synthesize with nLev = 2 to give quantiser output range [ -1,
+1] and integrator ranges [-1, +1] (the scaleABCD() default) and then substitute a
quantiser with more levels within the range -1 to +1. Simulate extensively to ensure
the resulting modulator behaves to specification.

2. (Recommended) adjust the scaling factor in scaleABCD() to match the integrator

ranges to the quantiser range. If you then replace the toolbox quantiser with one
having input and output range [-1, +1] then all of the input, output and integrator
ranges will all correspondingly scale-down to the range [-1, +1].

Since you are now synthesizing with the correct number of quantiser levels for your
intended design, the toolbox will give better results using this approach:

• scaleABCD() should give better scaling and umax estimates.

• You can design directly for more aggressive (i.e. higher) maximum NTF gain
(H_inf) to achieve higher SQNR. A multi-bit design may be stable for H_inf
values well above the stable limit for a single-bit design.

2.7 Multi-level synthesis example

We will now synthesize a 3rd order modulator with a 3-bit (8 level) quantiser and CIFB
architecture to illustrate dynamic range scaling for a multi-level design. Two test benches
are provided for this particular modulator to highlight and emphasise range scaling
considerations:

• mod3tb_cifb_3bit.mdl has a quantiser with variable step size ∆ = 2/(nLev-1) and

fixed output range [-1,+1].
• mod3tb_cifb_3bitTBQ.mdl has a toolbox-compatible quantiser with fixed step size
∆ = 2 and variable output range [ -(nLev-1), +(nLev-1) ].

In the Matlab Command window type:

OSR = 64
Order = 3
nLev = 8
form = ‘CIFB’

Repeat steps [4-6] from earlier to get the unscaled [a g b c] coefficients for the Simulink
model and create the unscaled ABCD modulator representation. You can view the NTF
poles and zeros by typing:

plotPZ(H)
Now perform the default dynamic range scaling (+/-1) by typing in the Matlab Command
Window:

[ABCDscaled umax] = scaleABCD(ABCD, nLev)

ABCDscaled =

1 0 0 0.39075 -0.39075
0.15344 1 0 0.39277 -0.39277
0 0.45821 1 0.49952 -0.49952
0 0 1.601 1 0

umax =

6.5333

1. Make a note of the reported umax value. Is it within the range [-1, +1]? Why not?

The toolbox assumes a quantiser output range of [ -(nLev-1), +(nLev-1) ] = [-7,+7], so the
maximum possible stable input range for a modulator becomes [-7,+7].

Now generate the scaled [a g b c] coefficients by typing and executing:

[a g b c] = mapABCD(ABCDscaled, form)

Open ‘sweeptestbench.mdl’ and edit the Model Reference Parameter of ‘dut’ to

‘mod3tb_cifb_3bitTBQ.mdl’. This is the test bench using the tool-box compatible quantiser.
Click on one of the timescope icons to open the signal viewer.

Next type in the Matlab Command Window:

sinfreq = 4882.8125
sinamp = 0.95*umax

Run the simulation by selecting “Simulation > Start” or by keystroke Ctrl+T in the
“sweep_testbench.mdl” window and then type and execute in the Matlab Command
Window:

Qout_SNDR
integ_stats(INT1OUT)
integ_stats(INT2OUT)
integ_stats(INT3OUT)

to see the modulator SQNR performance and summaries of the integrator signal ranges.
Keep notes of these results.

1. What is the input signal range? What are the integrator ranges – are they within the
range [-1,+1]? Is this what you would expect from default scaleABCD() behaviour?

The input signal range is [- 6.2067, +6.2067]

 Unit/sqrt(Hz)

Relative frequency (probability density per bin)

Relative frequency (probability density per bin)

The integrator outputs fit nicely withing the [-1,+1] range, as expected from the dynamic
range scaling.

Now we will re-simulate the modulator but using the test bench with the quantiser having
output range [-1,+1]. Edit Model Reference Parameter of ‘dut’ to ‘mod3tb_cifb_3bit.mdl’
and then execute the following Matlab Command:

sinamp = 0.95*umax/(nLev-1)

(This is necessary to scale the input signal to the new maximum input range [-1,+1].)

Run the simulation by selecting “Simulation > Start” or by keystroke Ctrl+T in the
“sweep_testbench.mdl” window and then type and execute in the Matlab Command
Window:

Qout_SNDR
integ_stats(INT1OUT)
integ_stats(INT2OUT)
integ_stats(INT3OUT)

1. Compare the SQNR plot and number with that obtained using the toolbox quantiser.
How do they compare? Why do you get this result?
2. Compare the integrator signal ranges with those obtained using the
‘mod3tb_cifb_3bitTBQ.mdl’ test bench. Explain your results. Are the toolbox default
integrator scaling ranges good for multi-bit designs - explain?
The SQNR plot is the same as before, as dynamic range scaling does not effect the NTF.

The integrator output ranges are too small (1/7 of what they were before) because the
toolbox is assuming a quantiser output range of [-7,+7], but it is in fact [-1,+1].

The last example showed how the integrator ranges were scaled by a factor 1/(nLev-1)
when using the toolbox default synthesis settings for a quantiser with output range [-1,+1].
As explained earlier, this is generally not a good approach to dynamic range scaling when
circuit implementation practicalities are considered; we would generally prefer all signals to
have similar ranges. We will now see how to synthesize so that all signals (maximum
possible input range, output range and integrator signals) occupy the range [-1, +1].

In the Matlab Command Window, type and execute:

[ABCDscaled umax] = scaleABCD(ABCD, nLev,0,nLev-1)

ABCDscaled =

1 0 0 2.7352 -2.7352
0.15344 1 0 2.7494 -2.7494
0 0.45821 1 3.4967 -3.4967
0 0 0.22872 1 0

umax =

6.5333

This will scale the integrator outputs to the range [ -(nLev-1) to (nLev+1) ] instead of the
default range [-1, +1]. This now matches the maximum possible input range when using
the toolbox quantiser, and so all signal ranges should scale to [-1, +1] if the modulator is
then implemented using the [-1, +1] quantiser.

Now type and execute:

[a g b c] = mapABCD(ABCDscaled, form)

a=

2.7352 2.7494 3.4967

g=

b=

2.7352 2.7494 3.4967 1

c=

0.15344 0.45821 0.22872

to generate the Simulink model coefficients from the scaled ABCD modulator description.
Run the simulation by selecting “Simulation > Start” or by keystroke Ctrl+T in the
“sweep_testbench.mdl” window and then type and execute in the Matlab Command
Window:

Qout_SNDR
integ_stats(INT1OUT)
integ_stats(INT2OUT)
integ_stats(INT3OUT)

1. Compare the SQNR plot and number with that obtained using the toolbox quantiser.
How do they compare? Why do you get this result?
2. Compare the signal ranges at the integrator outputs and the quantiser
output/modulator input. How do these now compare?

There is no change in the SQNR plot as dynamic range scaling does not affect the NTF.
The integrator stages now have the desired dynamic range scaling: the outputs nicely fill
the [-1,1] range without exceeding this range.

Hopefully this exercise has highlighted how to use the toolbox to design for our quantiser
with fixed output range [-1, +1] so that you also achieve the correct/desired integrator
range scaling. You are encouraged to try synthesizing modulator parameters for other
Simulink schematic test benches provided in ‘LAB3’ and then simulating your resulting
designs to check you understand how to use to toolbox effectively. Note that all other test
benches provided have the [-1,+1] quantiser type.

3.0 Learning Review

This laboratory examined the issue of stability in creating third (and higher) order
modulators and examined 2 approaches to synthesising stable high-order designs with
wide stable input range:

• Single-loop architectures with signal paths added to limit the maximum gain of the
NTF to improve loop stability.
• Using multi-bit quantisers to help stabilise the NTF and hence loop ([1] section 6.1)

Single-loop designs offer good tolerance to errors such as finite dc integrator gain and
small gain matching errors in the signal paths. However, they can be difficult to stabilise
due to having long chains of integrators in the NTF path, and may not give as aggressive
noise-shaping in the signal passband as the penalty for reducing the maximum NTF gain.
Various heuristic rules, such as Lee’s Rule, exist for modifying the NTF via changing to
loop topology/architecture to obtain stability, but extensive simulation is still required to
ensure that, for example, exceeding the stable input range does not result in the loop
locking-up indefinitely (there are ways of detecting this and resetting the integrators, but
these are beyond the scope of this course). Luckily, toolboxes such as the Delta-Sigma
toolbox described in [1] now exist to aid high-order, single-loop modulator design.

Using multi-bit quantisation brings many advantages (see section 6.1 of [1] for a full list),
such as:

• Reduced in-band noise due to using a smaller quantisation step.

• Improved quantiser gain and hence NTF stability, allowing more aggressive NTF
designs for lower passband noise and wider stable input range.

However, a major problem with adding multi-bit feedback paths is that even slight
nonlinearity in the DAC feedback path (e.g. due to random component variations) to the
first integrator can have disastrous consequences for the modulator performance. This
topic is examined in laboratory 4.
There are thus a wide range of trade-offs in choosing a suitable modulator topology for
high SQNR applications requiring loop orders >= 3. Given the empirical/heuristic nature of
much DSM theory, experience and experiment play a large role in choosing an appropriate
architecture. However, with the advent of tools such as the Schreier Delta-Sigma Toolbox
to aid architecture selection, this is now a considerably easier task than before.

References:
[1] Schreier, Temes: Understanding Delta-Sigma Data Converters, Wiley-Blackwell 2004.
Appendix 1: A closer look at MOD3 1-bit’s instability (and stability issues in general)

(Note: This material is not examinable and is here just for completeness/interest. You don’t
need to read it or try the exercises, but if you ever plan to design DSMs in the future then it
is definitely worth acquiring some familiarity with it and/or the related material in [1].)

The first exercise of this lab showed that MOD3 with a 1-bit quantiser was completely
unstable for all input signals. Later exercises showed that by modifying the modulator
architecture to CRFF type to reduce NTF out-of-band-gain (OBG), stability could however
be achieved. So just why was basic MOD3 unstable? How could high OBG lead to
instability? Correspondingly, why did reducing the OBG stabilise the modulator?

It is tempting at first glance to think that basic MOD3 is unstable because it comprises 3
integrators in cascade, giving 270o phase shift in the loop formed by the integrators and
the feedback DAC. However the CRFF modulator also has 3 integrators in cascade in a
feedback loop and is stable. More fundamentally, basic loop stability analysis for MOD3
shows that this “intuition” is wrong.

Recall that the NTF for MOD3, which describes the dynamics of how the noise circulates
around the modulator loop and appears at the modulator output, is:

NTF = (1 - z-1)3

= (z - 1)3 / z3

This transfer function has 3 zeros at z = 1 and 3 poles at z = 0. Since all 3 poles are well
inside the |z|=1 unit circle this system should be stable. So why did simulation show the
modulator to be unstable for any input signal?

Quantiser gain and stability

(You may wish to review sections 2.1.1, 3.2, 3.3.1 of [1] to refresh your memory about the
concept of effective quantiser gain and its effect on NTFs. Section 4.2 covers many of the
key stability concepts introduced here.)

It is important to realise that the NTF stated above was derived for MOD3 using a
modulator model where the nonlinear 1-bit quantiser is replaced with a linear model
comprising a unity gain transfer function with added quantisation noise. You should be
well-aware by now that this approximation is commonly made so that standard linear
system analysis methods can be employed:

Fig. 4 Linearised quantiser model (1-bit example)

Key questions to ask here are: just why was unity gain chosen for the quantiser model? Is
this a valid choice for single-bit MOD3? What happens if the gain is not 1? We know that,
especially for single-bit quantisers, effective quantiser gain can be very signal dependent
and should be checked by extensive simulation ([1] section 2.1.1).

Consider what happens to MOD3 if the quantiser gain has some general value “k”.
Reanalysing with a quantiser gain “k” yields:

NTF = (z - 1)3 / [ z3 + 3(k-1)z2 + 3(1-k)z + (k-1) ]

The roots of the NTF denominator - i.e. the poles of the system - depend on the gain k. For
k=1 we get the NTF stated previously with a 3 poles at z=0, but what might k≠1 do to the
pole locations?

In the LAB3 directory you will find a Matlab command script called “plotpoles.m”. This
script uses the Matlab built-in function roots() to find and plot (in blue) on the z-plane the
loci of the poles of the new MOD3 NTF as the quantiser gain k varies from 1 to 0. The
script also plots the unit circle in red so you can see if the poles move outside it for any
values of k.

In the Matlab command window, type “plotpoles” to run the script and plot the loci of the 3
poles as the modulator gain varies from 1 to 0.

You can read plotpoles.m to see exactly what the script does (it doesn’t attempt to be
elegant or sophisticated at all).

1. Comment on the pole locations as k decreases from 1 to 0.

The pole loci plot shows that for k < 0.5 the two complex poles of the NTF move outside
the unit circle and so system instability can be expected.

We thus see a mechanism for MOD3 to be unstable. We next ask: was the quantiser gain
always less than this critical value for our 1-bit MOD3 example? If so, then why?

To answer these questions, we need to know how big the quantiser input noise will be for
MOD3 even with an input signal of 0.

Noise at the quantiser input (and NTF realisability in general)

Consider how quantisation noise enters a discrete-time DSM feedback loop and then
circulates around the loop. Figure 5 shows for the MOD3 CRFF example how a
quantisation error E[n] introduced at the quantiser can eventually get back to the quantiser
input, and hence also quantiser output, via the feedback paths (integrator gain blocks
omitted for clarity).

In Figure 5:

• Blue dashed lines indicate paths with no delay from the quantisation noise input E
to the modulator output Y.
• Red dashed paths indicate one time-step delay paths from E to Y.
• Purple dashed paths indicate two time-step delay paths from E to Y.
(Remember that our quantiser is delayless here; all delays are due to integrators.)

Fig. 5 Quantisation error propagation around the modulator feedback loop.

Important comment: One very important thing to note here is ([1] section 4.1):

• The only delayless path is directly from E to Y. There can be no zero delay
paths around the modulator feedback loop back to the quantiser output
(which is also the modulator output, Y).

A delayless feedback path could result in an ill-defined system that tries to oscillate in an
infinitely fast limit cycle or diverge infinitely fast to ±∞, and so is not allowed for physically
realisable modulators (discrete or continuous time). This means that the NTF impulse
response must have h(0)=1, i.e. if you apply an impulse at E it appears immediately at Y,
and Y cannot change further in response to the impulse until at least one time-step later to
allow for any feedback path delays. The requirement that h(0)=1 for the NTF (equivalently
NTF(z=∞)=1) may seem esoteric, but it is of fundamental importance as it places strict
limits on what NTFs are physically realisable. This is why you cannot choose any old high-
pass transfer function for your NTF to give great in-band SQNR while keeping OBG low for
stability – invariably it will not satisfy h(0)=1 and thus be physically unrealisable. This is
basically another manifestation of the equal-areas theorem restriction given earlier.

Assuming a stable loop, after many quantisation error samples, {E[n]}, have been
introduced into the modulator loop and been allowed to circulate, there will be steady-state
quantisation noise power signals at the quantiser input and output, even in the absence of
any signal (X=0). If we can determine the magnitude of the noise at the quantiser input,
then we can tell if the quantiser input is overloaded, giving low effective gain.

The quantiser output is just the modulator output, so clearly we have

(Quantiser output noise)(z) = NTF.E(z)

and from the definition of quantisation noise,

(Quantiser out)(z) = (Quantiser in)(z) + E(z) ,

we can see easily that the noise at the quantiser input is simply:

(Quantiser input noise)(z) = [NTF(z) – 1].E(z)

Already we can see that if the NTF has high OBG then the noise at the quantiser input
could be very large.

MOD3 example in depth

Assuming for now that k=1 so that our NTF is indeed (1 – z-1)3, then what will be the
magnitude of the quantiser input noise? We aim to find whether or not we will violate our
k=1 assumption and in reality have k<0.5, leading to MOD3 instability.

It can be shown that for a white noise signal with power enoise2 processed by a filter with
transfer function/impulse response

H(z) = h(0) + h(1).z-1 + h(2).z-2 + h(3).z-3 + …

that the resulting steady-state noise power at the filter output is

Noise power = enoise2 . Σn [ h(n) ]2

For our ideal MOD3, expanding NTF = (1 – z-1)3 gives for the quantiser input:

HQIN(z) = [ NTF(z) – 1 ] = (1 – 3z-1 + 3z-2 – z-3) – 1

= -3z-1 + 3z-2 – z-3

(Aside: observe that hNTF(0)=1, as must be true for any physically realisable modulator;
thus hNTF(0) always cancels the -1 term in the [NTF-1] transfer function from loop input E
the quantiser input.)

Recalling that for a busy quantiser we can approximate the quantisation noise as a white
noise with enoise2 = ∆2/12, the quantiser input noise power is then:

Noise power = enoise2 . Σn [ hQIN(n) ]2 (A.1)

= ∆2/12 . [ (-3)2 + 32 + (-1)2 ]
= ∆2/12 . [ 19 ]

Thus the quantiser input sees 19 times more noise power than the quantisation noise itself
carries. If this noise signal considerably exceeds the quantiser output range [-1, +1] then a
low effective quantiser gain can be expected.

For a 1-bit quantiser with output levels [-1, +1], ∆ = 2 and the predicted quantiser input
noise power (i.e. mean-square signal magnitude) is:

Input noise power = (22 / 12) . 19

= 6.333

The rms input signal level is √(6.333) ≈ 2.51. This is much larger than the [-1, +1] quantiser
output range, so considerable compression via the quantiser is expected, i.e. low gain and
hence possible MOD3 loop instability. (Using a model of the input noise as predicted
above to drive a 1-bit quantiser with output range [-1, +1] gives quantiser gain ≈ 0.32 -
details of how this was derived are not important here).
We thus see that MOD3 with single-bit quantisation will be unstable even with no input
signal; its own quantisation noise is sufficient to overload the quantiser and drive it into
compressive operation, forcing the system poles outside the unit circle.

You may perceive a slight chicken-and-egg logical issue above:

We used a NTF that assumes that k=1 to compute the quantiser input noise power,
only to conclude that k=1 cannot be true for a real MOD3 with a nonlinear 1-bit
quantiser. Does this prove instability? Not conclusively. If, perhaps, the quantiser
input noise power falls rapidly as k decreases then perhaps the modulator stabilises
with, say, k≈0.7? Do we have to re-analyse with every k between 0.5 and 1 to
confirm there is really no stable configuration? We could, though that may get
tedious as the NTFs become more algebraically difficult to manipulate.

The analysis is still useful however, even if it seems self-contradictory: from the
linearised model results, we know that k<0.5 suggests trouble, and also that k=1
implies serious quantiser input overload that will push k<<1. So we have a strong
indication that this modulator is likely to be unstable, which can be verified by
simulation. Moreover, we also understand the origin of any instability For the
purpose of this exercise, the main point is that it illustrates some key principles
underlying modulator stability in general, namely how quantiser overload can make
system poles move to unstable positions.

Note also that k drops towards 0.5 for MOD3, the system poles approach the unit
circle, causing NTF gain peaking which causes further quantiser overload rather
than reducing the input noise level, ensuring irrecoverable instability. Recall from
the first exercise that the integrator outputs grew unboundedly in MOD3 simulation.

In summary: the high out-of-band noise gain means that even with no input signal, the
quantiser will saturate (i.e. have low gain) due to overloading its input with its own highly
gained quantisation noise as it circulates around the modulator loop. If low quantiser gain
moves system poles outside the unit circle, as it does for MOD3, then instability can result.

This explains why as a general principle in modulator design, moving NTF poles to limit
the maximum NTF gain can stabilise an otherwise unstable modulator, as seen in the lab
examples going from MOD3 to MOD3_CRFF. As also seen and explained in the lab,
maximum achievable SQNR is lowered, which is the cost paid to widen the stable input
range. It is also the principle underlying Lee’s Rule, which suggests not to have OBG>1.5
for a modulator with a 1-bit quantiser [1].

Note that NTF modification is not the only route to stabilising a modulator. MOD3 could
also be stabilised by reducing the quantisation noise level to avoid overloading the
quantiser input. One way to achieve this is to use multi-level quantisation so that ∆ is
smaller while the quantiser output range remains [-1, +1]. Even for already stable
modulators, adding more quantisation levels will widen an existing stable input range; this
is exactly why you saw the stable input range increase for the MOD3_CRFF examples in
the lab exercises as the number of quantisation levels was increased from 2 (1-bit) to 8 (3-
bit).

In the LAB3 directory you will find a version of MOD3 with a 4-bit (16 level) quantiser
(having ∆ = 2/15) called “mod3_4bit.slx”.
Repeat the first laboratory exercise using this modulator instead of “mod3.mdl”.

1. Is this modulator stable for some inputs now? What is the stable input range?
2. For stable inputs, you can use the “calc_quant_gain.m” script in
ELEE11080ROUTINES to compute the effective quantiser gain. What typical
effective gain does it report when the quantiser is stable?
3. What do you think limits the stable input range? What might happen at the quantiser
input is there is a large dc input present at the modulator input? Again, you can use
calc_quant_gain.m to observe how the gain varies as input_dc increases from 0.

We can also use this 4-bit MOD3 example to confirm the analyses given above for the
noise power at the quantiser input leading to equation (A.1) (and hence hopefully convince
you that the analysis is valid).

Type “init_vars3” to ensure all variables are set to sensible values.

Next type “swpctrl.select=1” to select the sinewave input and then “swpctrl.trantime=0.1”.
Type “sinamp=0.2” to select a small input signal – the purpose of this signal is to keep the
quantiser busy and so ensure that the white quantisation noise approximation is correct.

Run the Simulink simulation and then type “integ_stats(INT3OUT)” to see the statistics for
the 3rd integrator output. Note that output of the 3rd integrator is the quantiser input.

1. What is the effective quantiser gain reported by calc_quant_gain.m? Will equation

(A.1) be valid?
2. Use equation (A.1) above to estimate the quantisation noise power at the quantiser
input. Remember that ∆=2/15 for the 4-bit quantiser. Take the square root to get the
rms noise signal level.
3. How does the rms noise level you obtained above compare with the standard
deviation reported by integ_stats(INT3OUT)?

Remember that the quantiser input contains both the quantisation noise signal and
the stimulus sinewave. Since for a busy quantiser the noise is (as good as)
uncorrelated with the signal, σINT3OUT2 = σNOISE2 + (SIGNAL POWER)

You should get a very good agreement with theory!

You can also use dc inputs to check the theory, but in this case you must add some dither
to break-up the tonal limit-cycle behaviour (failing to do so will violate the busy
quantiser/white quantisation noise assumption and so (A.1) will not apply).

Type “swpctrl.select=2” to select the dc input.

Then type “modctrl.dgain1 = 1/15”; note that this sets the size of the dither to exactly
match the expected quantisation noise characteristics, i.e. evenly distributed random
numbers between -1/15 and +1/15.

Finally type “input_dc=0.001”; this is needed to completely disrupt the limit-cycle behaviour
as otherwise the dither is just not quite large enough to do so (you could confirm this by
repeating the experiment with input_dc=0 so see that the modulator is still quite strongly
tonal).
Run the Simulink simulation and then type “integ_stats(INT3OUT)” to see the statistics for
the 3rd integrator output. Note that output of the 3rd integrator is the quantiser input.

.
1. Use calc_quant_gain.m to confirm that the quantiser gain is close to 1.
2. How does the rms noise level reported at the quantiser input by
integ_stats(INT3OUT) compare with (A.1)?

Bear in mind that dither adds noise in addition to the quantiation noise. As the dither
has been intentionally configured to match the quantisation noise power, and given
that it is uncorrelated to the quantisation noise (it’s a random number sequence):

(total noise power) = (quantisation noise power) + (dither noise power)

= 2.(quantisation noise power)

so you need to multiply (A.1) by 2 to get the total power (or by √2 if working with
rms signal levels).

Again, you should get a very good agreement with theory!

 Sigma-Delta Data Converters
Laboratory Session 4
1. Introduction

In this fourth laboratory, we will study the properties of multi-bit feedback DACs, both
within the feedback loops of modulators and also as stand-alone blocks.

Laboratory 3 illustrated how multi-bit quantisation gives well-defined quantiser gain (little
variation with input signal provided that the input does not saturate the quantiser) which
can in turn give well-defined NTF (remember that changing the quantiser gain changes the
NTF) and so improves modulator stability (see section 6.1 of [1]). If multi-bit quantisation is
used then clearly the feedback will also be multi-bit. In the case of an analogue modulator,
a DAC is needed to convert the digital quantiser output back to analogue feedback for the
integrators. However, while single-bit DACs are inherently linear because they have only 2
output states and a straight line can always be fitted perfectly to 2 points, a linear multi-bit
DAC circuit needs perfectly matched components, and real DACs are thus nonlinear. One
problem with using a multi-bit feedback DAC is that DAC nonlinearity will not be shaped by
the loop NTF and thus directly affects the modulator linearity (quantiser/ADC nonlinearities
are shaped by the NTF and are much less critical).

This laboratory will:

1. Demonstrate the need for excellent feedback DAC linearity in high SNDR
converters through examining via simulation the effects of nonlinearities due to DAC
element mismatch.
2. Demonstrate how DACs in oversampled systems can be made perfectly linear (in a
time-average sense) through various dynamic element matching (DEM) techniques.
3. Examine some basic properties of these DEM techniques.

By the end of this laboratory you should have a practical feel for the serious problems
feedback DAC linearity can cause in analogue modulators, and some methods for
addressing this key problem in multi-bit Delta-Sigma ADC design.

1.1 Lab 4 Setup

You may wish to consult the course textbook as you are following the laboratory,
“Understanding Delta Sigma Modulators” By R. Shreier and G. Temes, which is available
online at:
http://xplqa30.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508.

You should still have a copy of all the Matlab laboratory materials in a directory called
“EdUni” created at the start of Laboratory 1; if not then please consult the laboratory 1
hand-out for instructions on how to create this Matlab workspace (and please don’t delete
it again!).

Change directory into this location by typing “cd EdUni”.

In this directory there are general utility routines:

sweep_testbench.mdl
In the directory “LAB4” there are a number of files that will be used in this exercise:

DEM_testbench_DACerrors.mdl
DEM_testbench_DACerrors_9lev.mdl
init_DAC_3ele.m
init_DAC_8ele.m
mod2_2bit_noDEM.mdl
mod2_butterfly_scramble.dml
mod2_butterfly_scramble2.mdl
mod2_dwatest.mdl
mod2_ilatest.mdl
mod2_randac.mdl
mod2_randac2.mdl

As in previous laboratory session, we will also require the utilities held in the directory
“ELEE11080_ROUTINES”.

In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.

In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current

Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directory “LAB4”.

Type “init_vars” into the Matlab Command Window. This routine sets the default values for
common variables used in the various forthcoming exercises.

You are now ready to begin the lab.

1.2 Mismatch Effects in the Feedback DAC in a Modulator

Before examining DEM methods, we will first investigate the consequences of employing a
nonlinear feedback DAC in an analogue modulator without making any attempt to address
the nonlinearity. This exercise should highlight just how critical feedback DAC linearity is to
achieving high SNDR performance.

Background

The following exercise assumes you now understand how a multi-bit quantiser and DAC
should behave, see [1] section 2.1 if you need to refresh your understanding.

Open the Simulink schematic “mod2_2bit_noDEM.mdl”.

This schematic contains a standard MOD2 second-order modulator seen previously in

Laboratory 2, comprising 2 non-delaying integrators with a feedback delay, but now
implemented with a 2-bit quantiser and feedback.

Previously we have used the Simulink quantiser block to implement 1-, 2- and 3-bit
quantisers. Here the quantiser and feedback DAC are implemented more like real circuits
so that we can directly examine the effects of circuit component errors on linearity and
hence overall modulator behaviour.

Double-click on the quantiser block to view its schematic details. This flash-ADC
implementation of a 2-bit quantiser tests the analogue input value against 3 threshold
levels and generates a digital thermometer-coded output as shown in Figure 1. A N-bit
digital thermometer code can represent N+1 levels (c.f. 2N levels for a N-bit binary code),
with the level being represented by the number of ‘1’s in the code. The title “thermometer
code” reflects how the ‘1’s fill the code word from one end to the other as the code value
increases, similarly to how the rising mercury in a thermometer reflects rising temperature.

Fig 1. Transfer function of the (ideal) 2-bit quantiser with thermometer-coded output.

Recall that the quantiser output is a digital signal but the modulator input is analogue and
an analogue feedback signal is required; i.e. a DAC is required to create the feedback
signal.

Double-click on the DAC block to view its schematic details. Unlike binary-weighted DACs
such as R-2R ladder DACs, this is a thermometric DAC. The DAC comprises a number of
unit elements, each of which has a nominal value of 1 and is controlled by one bit of the
input digital thermometer code. The DAC output is created by summing those unit
elements where the corresponding digital input bit is ‘1’. For example, for the digital input
code 011 the DAC output will be 0 + 1 + 1 = 2. See Figure 2.

For our DAC the magnitude of each unit element is held in the Matlab array variable
DACctrl.uelement[]. Ideally all DAC elements have matched unit values i.e.
DACctrl.uelement=[1 1 1] and so the ideal DAC outputs are exactly 0, 1, 2 and 3. In reality,
these elements have small random mismatches due to manufacturing errors e.g.
DACctrl.uelement=[1.0112 0.9973 0.9934], resulting in a nonlinear DAC; see Figure 2.

(Note that binary-weighted DACs can also be very nonlinear as a result of manufacturing
variations. The reason why we use a thermometric DAC here is to enable the use of the
DEM methods we still study later; these cannot be applied to binary-weighted DACs.)
Fig 2. Transfer function of ideal and real 2-bit thermometer DACs

Note here that each input thermometer code always selects the same DAC elements to
form the DAC output, and hence always gives the same error due to any DAC element
errors for a given thermometer code input to the DAC.

1. Confirm that if you cascade the above ideal quantiser into the above ideal DAC then
multiply the DAC output by 2/3 and subtract 1 that you get an overall transfer
function of 1, that is, a line drawn through the mid-points of the steps and treads
after scaling and offsetting gives an analogue transfer function [DAC output level] =
[Quantiser input level].

For example, the mid-point of the range of analogue quantiser inputs giving output
code 001 is -1/3. If you then input code 001 to the DAC the ideal DAC analogue
output will be 0+0+1 = 1. Multiplying this DAC output by 2/3 and then subtracting 1
gives a modified DAC output 1.2/3-1 = -1/3, which is the same as the original
quantiser input.

This hopefully clarifies the purpose of the 2/3 gain and (-1) bias components
highlighted in yellow in the Simulink schematic. We now have an effective quantiser
gain of 1 and the feedback signal range (which defines the maximum possible input
signal range) is now [-1 +1].

Set the “Manual Switch” to the upper position to select the quantiser output as feedback.
This is equivalent to having an ideal feedback DAC. Run the simulation by typing <ctrl-T>
or selecting Simulation > Start from the pull-down menu.
You will see FFT plots showing the feedback, quantiser output and DAC output
waveforms. With no mismatch (ideal linear DAC), these waveforms are very similar – there
is a small shift in power level of the normalised feedback output and the DAC/quantiser
waveforms because of the different signal ranges [-1,+1] and [0,3]. Notice the second
order noise shaping due to the modulator. You can see this more clearly by running
“Qout_SNDR_ac” (this is just a version of Qout_SNDR that first removes any dc signal
component).

1. Make a copy of this plot for later reference and note the SNDR value.
Unit/sqrt(Hz)

Double-click on the “Scope” block to examine the time-domain plots of the DACin, DACout
and feedback waveforms. Perform an “autoscale” to see these more fully.

1. Note how the multi-level feedback tracks the input signal (as seen in lab 3)
2. Note also that all feedback DAC values in the lower trace are exactly -1, -1/3, +1/3
or +1 (i.e.an ideal DAC).

Now set the “Manual switch” to the lower position (by clicking on it if required) to select the
real DAC output instead of the ideal DAC implied by direct feedback from quantiser.

Type “DACctrl” to check that all DAC elements are 1 (ideal) and re-run the simulation by
typing <ctrl-T> or selecting Simulation > Start from the pull-down menu. Use
“Qout_SNDR_ac” to see the quantiser output spectrum and SNDR value.

1. Check that you get the same results as in the implied ideal DAC case above
(because the actual DAC has no element errors and so is ideal).

Now add some element mismatch to the DAC by typing “DACctrl.uelement = [1.05, 1.0,
0.95]” in the Matlab command window or running the Matlab script “init_DAC_3ele” in
“LAB4”. This represents DAC elements with +5%, 0% and -5% mismatch.
(5% is about 25-100 times worse than typically achievable in integrated circuits, but we
wish to emphasise the effects of the mismatches here. Note also that for simplicity we will
keep the sum of the DAC elements = 3; clearly this will not be true in practice for random
errors and so a real DAC will have a small gain error, but such a gain error does not affect
linearity.)

Run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu. Type “Qout_SNDR_ac” to see the output spectrum and noise performance. Make a
copy of this plot. Use the time-scope to zoom in on “Raw DAC output” and note the output
levels.

1. Note the “Raw DAC” output levels. Would you expect these levels given the
element mismatches and how the thermometer DAC works?

The Raw DAC output levels are 0, 1.05, 2.05, 3 (see ‘DACout’ variable in the workspace).
Denoting he DAC elements by u_1, u_2, u_3, this corresponds to 0, u_1, u_1+u_2,
u_1+u_2+u_3, as would be expected from a thermometer DAC.

2. Comment on the change in the output spectrum? What has changed from the ideal
feedback DAC case? There are 2 main changes - can you explain each of them?
(This is an important point, so please ask if you are unsure.)
Unit/sqrt(Hz)

Compared to the previous spectrum, two main changes have occurred (both as a result of
the DAC nonlinearity): (1) harmonics of the signal frequency have appeared (due to the
signal being distorted), (2) the noise floor has flattened and risen in the signal band (due
the high frequency quantisation noise being intermodulated into the signal band).

3. What effect have these +/- 5% errors had on the SQNR? Has it degraded slightly,
badly or very badly?
The SQNR has dropped by more than 30dB (corresponding to a 5-bit loss in resolution).
This is a dramatic degradation in the performance of the modulator.
Now type “DACctrl.uelement = [1.0025 1.0 0.9975] in the Matlab command window. This
represents DAC elements with +0.25%, 0% and -0.25% errors, which is a fairly
representative matching level for integrated circuit components (some processes may be a
bit better, some a bit worse, and you can always get much worse if you do bad circuit
layout!).

Run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu. Type “Qout_SNDR_ac” to see the output spectrum and noise performance.

1. Compare the output spectrum and SNDR to those obtained with an ideal DAC? Is
there still significant degradation? Could we make an 80 dB SNDR converter in
practice? What about a 98 dB converter (the performance required for faithful
conversion of 16-bit CD audio)?

Modulator output spectral density (Units/sqrt(Hz))

100

Simulated:
10-1
SQNR = 77.6 dB Brickwall LPF @ fs/(2.OSR)
ENOB = 12.6
10-2
Unit/sqrt(Hz)

10-3

10-4

10-5

10-6

10-7
101 102 103 104 105 106
Frequency(Hz)

The degradation is now more modest (a loss of 5dB SQNR and 1-bit of resolution), and an
SNDR of 80dB may just about be achievable with this converter (sinamp=0.922 gives
80.1dB). However, 98dB would require significant changes (e.g., in terms of OSR, or
number of stages), which may be impractical in terms of the circuit implementation. Even if
the desired SNDR was achieved, the high level of harmonic distortion may not be
acceptable.

1.3 Random Element Selection DEM

In Section 1.2 we saw how feedback DAC nonlinearity can distort not only the input signal
when seen at the modulator output (causing signal harmonics to appear), but also the
quantisation noise itself, leading to the high out-of-band quantisation noise intermodulating
with itself and appearing in the signal band as a white noise. We also noted that for typical
IC device matching, it is difficult if not impossible to design high-performance converters
without addressing feedback DAC errors. Assuming that we don’t want to apply very
expensive device trimming methods or devise additional calibration methods and circuits,
cheap and simple methods for dealing with the DAC nonlinearity are essential if we wish to
take advantage of multi-bit quantisation to improve NTF stability and stable input range.

Note that in section 1.2 a given DAC input code always selected the same DAC elements
to create the DAC outputs. A simple scheme can be employed to decorrelate the
mismatch error from the DAC code by selecting elements at random. In Section 1.2, the
analogue output corresponding to input code 011 (“2”) was always generated using the
first two DAC elements with values 1.05 and 1.0 giving an output of 1.05+1.0=2.05. Thus
the error is directly correlated to the DAC code because the DAC output always uses the
same DAC elements.

A randomisation process can instead be employed to select the elements to be used to

represent each code. For example, for input code “2” there are 3 different unit element
combinations

• (element 1 + 2) = (1.05 + 1.0) = 2.05

• (element 1 + 3) = (1.05 + 0.95) =2
• (element 2 + 3) = (1.0 + 0.95) = 1.95

that can be chosen from at random with equal probability of selection to create the DAC
output whenever the DAC input code is “2”.

All the above combinations will be chosen with equal frequency over a suitably long time
when generating DAC outputs for input code “2”, and so the average DAC output level
corresponding to input code “2” is now:

• (2.05 + 2 + 1.95) / 3 = exactly 2

Confirm that the average DAC output levels for all random element sections for DAC input
codes “0”, “1” and “3” are also exactly 0, 1 and 3 and hence that the DAC now looks
perfectly linear (in a time averaged sense).

You should be able to convince yourself that for a DAC with “N” elements, the average
DAC analogue output for input digital code “m” is “m x (average value of all the DAC
elements)” when using random selection (see sections 6.4 and 6.4 of [1]).

Since the DAC output is now of the form “output = m x (a constant)”, you can see that the
DAC output is now a linear function of its input code “m”.

Since we now select different DAC elements at random every time a certain code is input
to the DAC, and we do so in an attempt to linearise the DAC (i.e. get the same result as
having perfectly matched unit elements), this is an example of a Dynamic Element
Matching method.

To investigate this technique, close all Simulink windows and the open Simulink model
“mod2_randac.mdl”.

Type “init_vars” to reset all variables including the DAC elements and ensure that the
manual switch is in the lower position; this selects the real feedback DAC (which is now
idealised again).
Run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu. Type “Qout_SNDR_ac” to see the output spectrum and noise performance. Open
the Timescope to see the DAC input and output values.

1. Check that DACout = DACin on the Timescope, i.e. that the DAC is ideal.
2. Confirm that you get a second order shaped spectrum in the signal band and that
the SQNR is as seen for the ideal DAC case in section 1.2.

Now type “DACctrl.uelement = [1.05 1 0.95]” in the Matlab command window and run the
simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down menu.

Type “Qout_SNDR_ac” to see the output spectrum and noise performance. Keep a copy
of this plot (or keep the window open). Open the Timescope to see the DAC input and
output values.

Note that we have not yet enabled the DAC randomisation.

1. Check DACout has the levels you expect for each input code.
2. Confirm the passband spectral performance, harmonics and SNDR are the same as
seen in section 1.2 for +/-5% DAC errors.

Modulator output spectral density (Units/sqrt(Hz))

10 0

10-1
Simulated:
SQNR = 52.6 dB Brickwall LPF @ fs/(2.OSR)
ENOB = 8.4
10-2

10-3

10-4

10-5

10-6
101 102 103 104 105 106
Frequency(Hz)
Now enable randomisation by typing “DACctrl.dodem = 1” in the Matlab command window
and run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu.

Type “Qout_SNDR_ac” to see the output spectrum and noise performance. Open the
Timescope to see the DAC input and output values.

1. Look at DACout: does it always have the same value now for, say, DACin = 2? If
not then what values does it have? Are these what you would expect from the
randomiser given our DAC element values?

The output for DACin = 2 is now randomised, it is u_1+u_2=2.05, or u_1+u_3=2 or

u_2+u+3 = 1.95 with equal probability (the average output being 2, i.e., free of mismatch
error)
2. Compare the quantiser output spectrums for a DAC with +/-5% errors with and
without randomisation? Are they exactly the same? If not then what big qualitative
difference do you see between them? Why? What does this tell you about the DAC
linearity?
Unit/sqrt(Hz)

No signal harmonics can now be seen, indicated the DAC has effectively been linearised.

3. Is the noise level (reported in the SNDR) the same with and without randomisation?
Has randomisation improved SNDR? Do both spectrums show the same noise, or
is it different (i.e. from a different source, not just a different level)? If different then
how could you show that? (Don’t spend too long thinking about this – ask a
demonstrator.)

The noise level in the signal band has somewhat increased. However, the source of this
noise is different from before (even though it still has a flat spectral profile). Whereas
previously the elevated noise floor was due to high frequency quantisation noise being
intermodulated into the signal band by the DAC nonlinearity, here it is due to the white
noise that is effectively injected into feedback path by the DAC element randomisation
process.
 4. Is randomisation a sufficiently good technique to make high-performance analogue
DSM modulators – has it got rid of both signal harmonics and the excess baseband
noise?

It is unlikely to be a sufficiently good technique in practice, as it only manages to eliminate

signal harmonics, the excess baseband noise can become worse.

1.4 Three alternative DEMs: DWA, ILA and a butterfly scrambler

In the last section you saw that simple randomisation DEM did indeed linearise the
feedback DAC, evidenced by the fact that the signal harmonics vanished, but it also
replaced the passband white noise caused previously by out-of-band quantisation noise
intermodulating via the DAC nonlinearity with a different white noise caused by the
sequence of randomised DAC errors now having a white noise spectrum. Consequently,
simple element randomisation alone is not sufficient to address DAC nonlinearity; it does
eliminate nonlinearity, but adds a broad-band white noise too.

In this section we will look at some simple DEM methods that not only linearise the
feedback DAC in a time average sense by swapping the DAC elements around, but swap
the elements in such a way that the noise spectrum resulting from the element swapping is
not white, but first-order noise-shaped so that it is suppressed in the signal passband.

Close all Simulink windows.

Open the schematic “DEM_testbench_DACerrors.mdl”. We will use this schematic to

evaluate more advanced dynamic element matching (DEM) techniques which de-correlate
the mismatch error from the signal and shape the mismatch error in the frequency domain.

This schematic contains a multiplexer selecting 4 different input source types, selected by
the variable “dem_select”; dc, arbitrary repeating sequence, sinusoidal, uniform random
number.

These inputs can be applied to four DEM algorithms:

Data weighted averaging (DWA)

Individual level averaging (ILA)
A butterfly network-based scrambler
Simple random selection (RS) as seen earlier.

DWA and ILA are discussed in the course text [1] and you may wish to refer to that as you
do this exercise. The DWA, ILA and RS algorithms are coded as embedded Matlab
functions and their source code can be viewed by double clicking on the relevant block.
The butterfly scrambler [2] is implemented as a Simulink schematic. The algorithms are
controlled by the DACctrl data structure.

Select the random noise input source by typing “dem_select=4” in the Matlab command
window. We will use the mismatched DAC elements from the previous sections
(DACctrl.uelement = [1.05, 1.0, 0.95]), so check you have these set, and set them if you
do not.
Turn off the DWA, ILA and RS DEM algorithms by typing “DACctrl.dodem=0” in the Matlab
control window. Run the simulation by typing <ctrl-T> or selecting Simulation > Start from
the pull-down menu (and ignore the butterfly scrambler output for now).

(Note that the butterfly scrambler method is not controlled by DACctrl.dodem and the test
bench blanks the associated DAC output when DACctrl.dodem = 0; ignore any butterfly
scrambler results when DACctrl.dodem = 0.)

1. Note the shape (flat, low-pass, high-pass etc.) of noise spectrums of the DAC errors
for each DEM method and any relevant noise level
2. Note the DEM noise levels in dBW/Hz (they should all be the same as they use
identical DACs and no DEM is enabled yet to differentiate them).

The noise spectrum has a flat profile.

Now enable dynamic element matching by typing “DACctrl.dodem = 1” in the Matlab

command window and run the simulation by typing <ctrl-T> or selecting Simulation > Start
from the pull-down menu.

1. Comment on the noise spectrums now for all four DEM methods? Are they flat or
noise-shaped? Explain why in each case.
2. Estimate (from comparing the spectrum plots) which DEM method is best here
(lowest noise at low frequencies). Why might ILA be the worst for signal-band
noise? (Apologies for the fact that the spectrums are in separate scope windows,
which makes comparison harder, but we’ve not yet figured out how overlay them all
in the same window, as versions of Simulink prior to R2013a allowed!)
The noise spectrum for element randomisation is flat, whereas those for DWA, ILA and
butterfly scrambling show first-order noise-shaping (due to mechanisms in these schemes
to use all DAC elements equally often. Amongst the latter three DEM schemes, DWA
reuses all elements the fastest, and ILA takes the longest to reuse all elements; as a
result, DWA gives the lowest noise in the signal-band, and ILA in the highest.

You should have found that DWA, ILA and the butterfly scrambler all give first-order noise-
shaping of the DAC output noise resulting from the DEM scrambling operations. However,
not all give the same shaped-noise level and in this case DWA gave the lowest noise
because it reuses all the elements the fastest and hence has the highest effective
oversampling ratio for noise-shaping.

One problem with all these simple DEM algorithms is that, like simple MOD1, they can
generate additional tones when fed with dc or simple periodic inputs, as this can lead to
the same DAC elements being selected repeatedly. This can sometimes result in signal-
band tones either directly or via intermodulation with tones from the modulator (limit cycles
and dc tones).

We will not deal with methods for suppressing these tones in this course but you should be
aware of this issue and it is instructive to see them in practice. (We will note in passing
though that dithering your modulator effectively can often help considerably, as creates a
more noise-like input to the DEM, free from modulator tones and limit-cycles for sine input,
and noise-in tends to give noise-out).

Select the dc input source by typing “dem_select=1” in the Matlab command window. Set
the dc input value by typing “dem_dcin=2”.
 1. Comment on the spectrums of each DEM method. Is there a strong tone present?
Why does this occur? If you are not sure then proceed to the next exercise.

For a DC input, element randomisation results in a DAC output error consisting of white
noise. DWA, ILA and butterfly produce a strong tone at 333.333 kHz (due to the element
selection cycling between the same sets of elements in the same repeating sequence)
On you lab-book, draw - for 6 or so cycles - the element selection results for our DAC with
elements 1.05, 1 and 0.95, when using DWA element rotation with fixed input 2.

(Start with selection “1.05 + 1”).

1. Can you see a repeating pattern in the DWA sequence? How does it compare to
the tone you saw in the previous section?

Yes – see above. It has a period of three samples, corresponding to the fs/3 =
333.333KHz tone seen in the spectrum.

2. (Don’t spend too much time on this; proceed if you can’t complete it). Can you
figure out a general rule for the tones expected from DWA for a DAC with “N”
elements and repeated input code “r”? Under what conditions could a signal-band
tone be generated directly?

Period of the tone = lcm(N,r)/r where lcm is the least common multiple. When the least
common multiple is a high number, the resulting tone can therefore be in the signal band.

Repeat the above exercise with dem_dcin = 0, 1 and 3 (you may also wish to open the
scope to explain your results).

1. Explain the results you get in each case.

For dem_dcin = 0 and dem_dcin = 3 we get no error in the DAC output (as no elements
are used/all elements are used in each conversion).

For dem_dcin = 1, the results are similar to dem_dcin = 2. The tone for DWA and ILA is
still at fs/3 = 333.333 kHz (as lcm(N,r)/r is again 3), although that for butterfly has moved to
fs/6=166.667 kHz.
Even more exotic tones can be generated for periodic inputs to the DEM algorithms, such
as modulator limit cycles.

Type “dem_select=2” to select a repeating input code sequence 1, 1, 2, 1, 1, 2,…

Run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu.

1. Comment on the tones seen for DWA, ILA and the butterfly scrambler. What is the
lowest tone frequency now in terms of the sample frequency Fs?
2. For DWA, sketch the element selections for a few cycles of the repeating input
sequence “1, 1, 2,…” and see if you can see the origin of the resulting output tones
(i.e. periodic behaviour in the element selection).
3. Compare it to the lowest tone’s period to the period of the input sequence and the
period of the lowest tone seen for DC input in the last exercise. Can you see how
multiple high frequency tones arising from DEM scrambling and those present in the
input sequence can interact to create lower-frequency tones that may fall within the
signal passband? (This is why out-of-band tones in DWA are considered a hazard –
they can interact with other tones to move in-band.)
For DWA and ILA we see tones at fs/9, 2fs/9 and 4fs/9. For butterfly, there is an additional
tone at 3fs/9=fs/3.

The lowest tone’s period is 9, whereas the period of the input sequence is 3. Previously,
for DC inputs of 1 and 2, DWA and ILA produced a tone with period 3. This illustrates that
in practice a high frequency tone fd produced by DEM scrambling can interact with a tone
in the input sequence fi and produce a lower frequence tone (in this example, the periods
of f1 and fd being multiplied) which may in some cases fall within the signal band, lowering
the performance of the modulator.

(If you have time later there is an expanded version of this exercise using 9-level DACs
you may wish to investigate: DEM_tesbench_DACerrors_9lev. Type “init_DAC_8ele” first
to create a bigger set of 8 mismatched DAC unit elements. For now though please
continue to the next section.)

1.5 Data Weighted Averaging DACs within a Sigma-Delta Modulator

The previous section examined the stand-alone behaviour of the dynamic element-
matched DACs, primarily because if we had examined these methods in situ in a DSM,
then confusion could have arisen as to whether any tones or noise-shaping observed was
due to the DEM or the modulator, or an interaction of both.

In this section we will now examine DWA when applied inside a DSM.

Close all windows from the previous section. Open the schematic “mod2_dwatest.mdl”.
Type “init_vars” to reinitialise all variable then type “DACctrl.uelement = [1.05 1 0.95]”.

Check the sine wave input is set to “sinamp=0.707” and “sinfreq=4882.8125”. To smooth
the modulator spectrum plots to aid determining the order of noise-shaping, add some
dither by typing “modctrl.dgain1 = 0.1”. Ensure the “Manual Switch” is in the top position
(ideal feedback DAC) and run the simulation by typing <ctrl-T> or selecting Simulation >
Start from the pull-down menu. Once the simulation is complete, run “Qout_SNDR_ac”
and keep a copy of the resulting spectrum plot for the ideal modulator.

1. Estimate the order of the noise-shaping when using the ideal DAC in the feedback
path. Is it what you expect?
2. Make a note of the SQNR.
40dB/dec noise shaping is seen as would be expected from a MOD2

Ensure DEM is disabled by typing “DACctrl.dodem=0” in the Matlab command window. In

the Simulink schematic set the “Manual Switch” to the lower position to insert the non-ideal
DAC in the feedback path.

Re-run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu and run “Qout_SNDR_ac” once the simulation completes. Make a copy of the
spectrum plot.

1. Measure the order of the noise-shaping when using the real DAC with no DEM in
the feedback path. Is it what you expect?
2. Make a note of the SQNR and the amplitudes of any harmonics.
Unit/sqrt(Hz)

The DAC nonlinearity leads to a flat noise profile in the signal band, with no apparent noise
shaping (due to out-of-band quantisation noise being intermodulated into the signal band).

Now enable DWA DEM by typing “DACctrl.dodem=1” in the Matlab command window.

Re-run the simulation by typing <ctrl-T> or selecting Simulation > Start from the pull-down
menu and run “Qout_SNDR_ac” once the simulation completes. Make a copy of the
spectrum plot.

1. Note the SNDR and compare it to the ideal DAC case. Are they the same? Has
DWA completely removed the effects of the DAC mismatches? Are there possible
tones visible?
 2. Estimate the slope of the noise spectrum in the signal passband. Is it what you
expect for a 2nd order modulator? If not then what is happening here?
Unit/sqrt(Hz)

The spectrum is now similar to the ideal case with the following main differences: (1) the
slope of the noise spectrum is no longer 40dB/dec but closer to 20dB/dec in the signal
band (and the SNDR has dropped by ≈4dB as a result), (2) there appear to be some minor
additional tones (as highlighted above).

The reason for (1) is that DWA provides first-order noise shaping of DAC element
mismatch noise. Whilst this is better than random element selection (which provides no
noise shaping), it still leads to an increase in the signal-band noise compared with the
ideal DAC case.

1.7 Other DEM methods applied to the MOD2 example

Repeat the above exercise for the Simulink schematics “mod2_ilatest.mdl”,

“mod2_butterfly_scramble2.mdl” and “mod2_randac.mdl”.

(Your do not need to repeat the exercise for “mod2_butterfly_scramble.mdl” and

“mod2_randac2.mdl”. These are there primarily for interest to show some variants on how
to implement these functions.

“mod2_randac2.mdl” is a Simulink variant on the RS function that runs more slowly but
allows the number of elements to be varied dynamically, and is intended only for
simulation purposes.

“mod2_butterfly_scramble.mdl” implements the butterfly scrambler as originally described

by its inventors [2]; intended for DACs with 2N elements (4, 8, 16, …), which have 2N+1
output levels. As our DAC requires 3 elements for 4 output levels, a dummy “0” element
must be added to use the original 22 element scrambler, and this would need to be
replicated in any real hardware implementation of this modulator (clearly not desirable).
Note that in order to run this simulation, you must first type “DACctrl.uelement = [1.05 1
0.95 1]” to add the extra DAC element.)

1. Which of DWA, ILA and the butterfly scrambler gives the best suppression of the
DAC errors in the signal passband? Which is worst? Why? What about any tones?
 Unit/sqrt(Hz)

Unit/sqrt(Hz)
ILA Butterfly Random

Ordering from best to worst, in terms of DAC error suppression, we get: DWA, Butterfly,
ILA, Random (the latter providing no noise shaping of DAC mismatch noise). DWA
provides the best suppression, as it is the quickest in using all DAC elements, but has a
tendency to produce tones.

Choose one of DWA, ILA or butterfly scrambling and determine the level of mismatch
which can be suppressed by that algorithm whilst maintaining an SNDR>80dB. Adjust the
mismatch level by changing “DACctrl.uelement”; e.g. [1.1, 1.0, 0.9] represents 10%
element mismatch (remember: for now please ensure that the sum of the DAC elements is
exactly 3; it clearly won’t be in reality, but if it isn’t then it adds a gain error to the feedback
path).

1. How does the element matching level required compare with typical device
matching limits on modern IC processes (approximately 0.025% to 0.25%
depending on process)?
Unit/sqrt(Hz)

DWA can cope with a 4% element mismatch and still give an SNDR>80dB as shown
above. This level of element mismatch is one or two orders of magnitude higher than what
can be achieved in modern IC processes.

For your chosen DEM method that you are investigating, try changing the oversampling
ratio to see what effect it has on the in-band shaped DAC noise for DACctrl.uelement =
[1.05 1 0.95]

1. Does the in-band DAC noise vary with OSR as would be expected for first order
noise shaping?
 OSR = 64 OSR = 128

Doubling the OSR (by changing OSR = 128 and Fs = 2MHz in Simulink) raises the SQNR
by around ~9dB (or equivalently, the in-band noise reduces by ~9dB). This is consistent
with first-order noise shaping (note 30*log10(OSR) term in theoretical equation), and is
only a modest gain in SQNR.

If you wish to make an ADC with a very high SQNR but are limited by DEM noise from the
feedback DAC then raising the oversampling ratio will further suppress the in-band DEM
noise. However, for 1st order shaping methods you may need a significant increase in the
OSR and this will likely make circuit implementation of your modulator much more difficult.

Another way to proceed is to use a DEM method with higher-order noise shaping; several
of these exist (e.g. see [3] or section 6.4.3 and figure 6.11 in [1]) but they are beyond the
scope of this course.

Another approach, which is particularly useful for low OSR applications, though somewhat
more hardware intensive than simple DEM methods, is to use DAC calibration (see section
6.5 of [1]).

If all else fails, you could resort to single-bit quantisation and feedback (but you may then
have a small stable-input range)!

1.7 Additional material

If you have time later there is an expanded version of exercise 1.4 using 9-level DACs you
may wish to investigate: DEM_tesbench_DACerrors_9lev. Type “init_DAC_8ele” first to
create a bigger set of 8 mismatched DAC unit elements.

(Highly recommended) The introductory notes to this lab commented that quantiser
errors dues to circuit element mismatches are less important than DAC errors. To
convince yourself of this, you may also wish to experiment with changing the threshold
levels in the 2-bit quantiser from their ideal values -2/3, 0 and 2/3 for the
“mod2_dwatest.mdl” test bench while using and ideal DAC. (e.g. try varying them
randomly by +/- 0.1). You should find that the modulator is much more tolerant of quantiser
threshold errors because the resulting quantisation noise errors – like all quantisation
noise – are shaped by the modulator NTF when referred to the modulator input. It is thus
very unlikely that quantiser threshold errors will be a problem for most DSM-based ADCs
unless these errors are very large and the required ADC performance is extremely high.
1.8 Learning review

In this laboratory you have examined the consequences of having mismatched elements in
the feedback DACs of analogue modulators with multi-bit feedback. Until effective
methods for addressing this issue were invented, modulators were limited to single-bit
quantisation and feedback with the attendant issues that brings; high quantisation noise,
poorly defined quantiser gain affecting the NTF, difficulty in adding dither without further
overloading the quantiser etc.

It has been shown how the nonlinearity resulting from even tiny DAC element mismatches
can have catastrophic consequences for an analogue DSM, causing both signal distortion
(harmonic distortion) and quantisation noise distortion (causing high white noise in the
signal passband).

One method to address this problem would be to individually trim the DAC elements at
production test, but this is generally prohibitively expensive of commodity devices (one of
your instructors has used a production-trimmed 18-bit precision Nyquist DAC before that
cost $900).

You have seen how some simple element selection methods, known as dynamic element
matching (DEM), can both linearise the DAC and also shape the noise resulting from the
element scrambling to keep as much of this noise as possible out of the signal passband.
Compared to element trimming, these have the advantage of adding only a very modest
digital complexity and cost to the modulator and will also track any element drift due to
aging. As such, DEM methods are almost universally used for creating high-performance
and cheap DSM-based ADCs and DACs with multi-level quantisation.

References:
[1] Schreier, Temes: Understanding Delta-Sigma Data Converters, Wiley-Blackwell 2004.
[2] Kwan, Adams, Libert, “A stereo multibit Sigma-Delta DAC with asynchronous master-
clock interface”, IEEE JSSC, vol. 31, no.12, Dec. 1996, pp 1881-1887
[3] Henderson, Nys, “Dynamic element matching techniques with arbitrary noise shaping
function”, ISCAS96, vol. 1, 12-15 May 1996.
 Sigma-Delta Data Converters
Laboratory Session 5
1.0 Objectives

In laboratory 3 we looked at the possibility of creating stable, high-order DSMs through

careful loop architecture choice to control the maximum NTF gain and/or using multi-bit
quantisation. We saw that while this approach can yield effective high-order loop designs,
it is mathematically intensive (the Schreier toolbox helps greatly in this regard) and
extensive simulation is required to check that instability does not happen for any
envisioned modulator inputs. We also saw that there can be in-band SQNR loss as a
penalty for reducing out-of-band NTF gain to improve modulator stability.

Another popular approach to implementing high-order modulators (particularly when the

art of devising stable, high-order single-loop DSMs was much less mature - which wasn’t
that long ago) is to cascade unconditionally stable first or second-order DSMs to create a
stable higher-order noise-shaping modulator. These are known as “Multi-stAge noise
SHapers”, or more commonly, “MASH” DSMs. Section 4.5 and in particular sections 4.5.2
and 4.5.3 of the course text [1] discuss how MASH modulators work and you are advised
to consult it before commencing this laboratory’s exercises to familiarise yourself with how:

• MASH modulators cancel the quantisation errors from the first stage(s) of the
modulator to leave only a high-order shaped error from the last stage.
• Mismatches between the analogue and digital processing in analogue MASH
modulators (ADCs) can limit the achievable SQNR due to causing incomplete
cancellation of quantisation error(s) from the first stage(s).

Note that this laboratory makes frequent comparison to the MOD3 results from
laboratory 3; you were advised to and should have kept good notes of your results
from that laboratory.

1.1 Setup

You may wish to consult the course textbook as you are following the laboratory,
“Understanding Delta Sigma Modulators” By R. Shreier and G. Temes, which is available
online at:
http://xplqa30.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508.

You should still have a copy of all the Matlab laboratory materials in a directory called
“EdUni” created at the start of Laboratory 1; if not then please consult the laboratory 1
hand-out for instructions on how to create this Matlab.

Change directory into this location by typing “cd EdUni”.

In this directory there are general utility routines:

sweep_testbench.mdl

In the directory “LAB5” there are a number of files that will be used in this exercise:
mod3_1plus1plus1MASH.mdl
mod3_2plus1MASH.mdl
mod3_2plus1MASH_v2.mdl
mod3_2plus1SMASH.mdl

As in previous laboratory sessions, we will also require the utilities held in the directory
“ELEE11080_ROUTINES”.

In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.

In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current

Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directory “LAB5”.

Type “init_vars3” into the Matlab Command Window. This routine sets the default values
for common variables used in the various forthcoming exercises (it is identical to “init_vars”
used in previous laboratories except it selects the Blackman-Harris window for computing
power spectral densities. Do not use a Hann window in this laboratory as the default
settings will give SQNR estimates corrupted strongly by the window skirts.)

You are now ready to begin the lab.

1.2 A third order MASH modulator

Right click on “mod3_1plus1plus1MASH.mdl” in “LAB5” and select “Open F4”. You should
see the third-order MASH modulator shown in Figure 1. This modulator achieves third-
order noise shaping by cascading 3 first-order (MOD1) loops and is thus commonly
referred to as a “1+1+1” MASH modulator.

Fig. 1 MASH modulator (1+1+1) schematic

The modulator comprises:

 1. Three cascaded MOD1 blocks, the first two of which use 2-bit quantisation and
feedback (to stabilise their quantiser gains and hence well-define their NTFs – for
reasons explained below) and the last of which uses 1-bit quantisation and
feedback.
2. Subtract/difference blocks (highlighted in green) are used to derive the quantisation
errors “E1” and “E2” for the first 2 stages by subtracting the quantisers’ inputs from
their outputs. Remember: (quantiser output) = (quantiser input) + (quantisation
error).
3. Each derived quantisation error is then passed to the next modulator stage.
4. Finally, the (digital) outputs of each quantiser, which contain various combinations
of the individual quantisation errors shaped by the STFs and NTFs of the sub-
modulators, are re-assembled digitally (yellow highlighted blocks) to generate the
overall modulator output.

The yellow highlighted comments on the schematic show how the individual modulator
digital outputs are combined by digital arithmetic circuits (the blocks also highlighted in
yellow) to cancel the quantisation errors E1 and E2 from stages 1 and 2 so as to leave
only:

• the stage 3 quantisation error E3 processed by the product of the (first-order) NTFs
of all 3 modulator stages, thus giving third-order noise-shaping of E3, and
• the input signal processed by the STFs of all 3 modulator stages.

Take a few minutes to work through the combinations of the modulator outputs as
highlighted on the Simulink schematic to convince you that all E1 and E2 error terms are
cancelled and that the above statements are true.

Note that to achieve the desired perfect cancellation of E1 and E2, the STFs and NTFs of
each modulator encoded in the digital arithmetic circuits must exactly match the true STF
and NTF of each modulator, and this is where analogue MASH modulators in particular
can fall down in practice. Finite integrator gains, gain errors caused by component
mismatches, signal-dependent quantiser gain etc. can result in the individual sub-
modulator NTFs being poorly defined or variable, giving difficultly in cancelling exactly
error terms involving them via the digital recombination of the individual modulators’
quantiser outputs.

The essence of the problem is that several large quantities must be subtracted to leave a
well-defined much smaller quantity, and this approach is always very sensitive to errors.
For example, using our 1+1+1 MASH example, two NTF2.STF3.E2 terms:

• one generated by the third MOD1, and

• one derived digitally from the output of the second MOD1

must be cancelled to remove any trace of the E2 quantisation error. As both terms are
generated by different means, even relatively small differences between, say, the real
NTF2 and the assumed version of it used in the digital logic can cause the terms to differ
by enough that after they are subtracted the residual E2 quantisation error terms are much
greater than the desired third-order shaped E3 term, thus badly degrading the overall
SQNR (and giving a second-order noise-shaping characteristic in the signal band if E2
errors dominate).
In this exercise we will examine the operation of this MASH modulator and get a feel for its
sensitivity to some of these analogue/digital path matching errors.

1.2.1 DC Input behaviour of the 1+1+1 MASH DSM

Close all Simulink windows from the last section and then open “sweep_testbench.mdl”
and right click on the block marked “dut”. Edit “model reference parameters” to
“mod3_1plus1plus1MASH.mdl”.

Double-click on “dut” in “sweep_testbench.mdl” to descend into the modulator in a new

window. As explained above, this 1+1+1 MASH modulator implements a third order noise
shaping loop by cascading 3 first order loops (c.f. figure 4.26 of [1).

Double-click any of the blue timescope icons in the modulator schematic to open the time
scope.

Ensure all modulator variables are reset (by rerunning “init_vars3”) and then type
“swpctrl.select = 2” to select the dc input. Ensure “input_dc = 0” and run the simulation by
selecting “Simulation > Start” or pressing <ctrl>T in the “sweep_testbench.mdl” window.

Type “Qout_SNDR” to see the modulator output spectrum and “mean(Qout)” to see the dc
content of the modulator output.

1. Observe the integrator outputs. Are they bounded? Is the modulator stable?
2. Compare the mean modulator output with input_dc? Are they a good match? Has
the modulator implemented a dc accurate analogue to digital conversion (i.e. what
sort of error do you see between input_dc and mean(Qout)?
3. Zoom in on a few cycles of Qout and look at the output spectrum. Is this modulator
tonal for dc input 0 as seen with the earlier single-loop third-order modulator?

Modulator is stable (integrator outputs are bounded). Mean(Qout) is very close to 0, so the
modulator is performing a dc-accurate analogue to digital conversion. The output has
strong tones, though they are all out-of-band.

Repeat the above exercise for input_dc values from +0.25 to +1.25 in increments of 0.25.
(You could also check a negative value to convince yourself that the modulator input range
is symmetric around zero.)
 1. Does the modulator stay stable for all inputs up to the maximum possible full-scale
limit of +1? How does this compare to the CRFF modulators from lab 3?
2. Is the modulator an accurate converter for dc inputs inside the stable input range;
what sort of error do you see between input_dc and mean(Qout)?
3. Is this modulator tonal for rational dc inputs in its stable input range (as seen for
MOD1 and MOD2 and the CRFF MOD3)? How could you address this?

input_dc = 0.25

Unit/sqrt(Hz)

input_dc = 0.5
Unit/sqrt(Hz)

input_dc = 0.75
Unit/sqrt(Hz)
input_dc = 1

Unit/sqrt(Hz)
In all of the above cases, Mean(Qout) is very close to input_dc, so the modulator is
performing a dc-accurate analogue to digital conversion. The output has strong idle tones,
although they are out-of-band for the dc input levels considered. In practice it would be
prudent to use dither to eliminate tones. We note that the modulator is stable up to (and
including) an input of 1, which is not the case for a higher-order, single-loop structure.

input_dc = 1.25

Modulator output spectral density (Units/sqrt(Hz))

100
Simulated:
SQNR = -135.9 dB Brickwall LPF @ fs/(2.OSR)
-2
10 ENOB = -22.9

10-4
Unit/sqrt(Hz)

10-6

10-8

10-10

10-12
101 102 103 104 105 106
Frequency(Hz)
The modulator has now become unstable, due to input_dc being > 1.

In laboratory 3 section 1.4, we saw that the single-loop CRFF third-order modulator with 1-
bit quantisation still performed well even for very modest integrator dc gains, as all 3 gains
multiply together before quantisation to suppress dead-zone behaviour, provide signal-
band noise-shaping near dc, etc.

We will now examine the tolerance of the 1+1+1 MASH third-order modulator to finite dc
gain in the integrators, looking firstly at dead-zone behaviour.

Close all Simulink windows and type “target_modulator=’mod3_1plus1plus1MASH’” and

then run “sweep_dc_dc” to obtain a dc transfer function of the MASH modulator for dc
inputs around zero with infinite (default) dc integrator gains. Do not close this window (as
always, keeping a hard-copy such as a screen grab is recommended).

Now set the dc gain of all integrators to 10 by typing “modctrl.igain1=10”,

“modctrl.igain2=10” and “modctrl.igain3=10” and then run “sweep_dc_dc” again and
compare the results with the infinite integrator dc gain result for the MASH MOD3
modulator and the CRFF MOD3 with finite integrator gains of x10 from section 1.4 of
laboratory 3.
 1. Compare the dc transfer functions for the 1+1+1 MASH DSM obtained with ideal
infinite gain integrators and integrators with gain 10. Are dead zones visible with
finite integrator gain? Does the overall slope of the output match the slope of the
input (i.e. does output = input as desired)?
2. If dead zones and slope errors are visible then how do they compare with those
seen for the CRFF MOD3 with integrator gains of 10? If the differences are large
then what has happened; why should one third order modulator design be much
more sensitive to the integrator gains than another in terms of dead zone behaviour
and overall modulator accuracy? Explain.
3. Considering both their stable dc input range and the dead zone behaviour; identify
two trade-offs involved in choosing the MASH versus single-loop approach to high-
order modulator design.
dc input (green) and output (red)

IGAIN = inf IGAIN = 10

There are noticeable deadzones, including a deadzone of width ≈0.034 around 0. Even
outside deadzones, there is a significant error between the input and output. By
comparison the deadzone around 0 for a 1-bit CRFF MOD3 (with the same integrator gain)
was only 0.006 in width (and other dead zones or slope errors were barely visible on the
plot).

The explanation for this as follows: in a higher-order single loop structure, the size of the
deadzone is inversely proportional to the product of the integrator gains, so for CRFF
MOD3 it is ~1/A^3. However, in the case of a cascaded multi-stage structure, non-
idealities in the first stage (such as an input-output offset due to finite integrator gain) will
not get cancelled when the outputs of the various stages are digitally filtered and
combined. Thus, for a MASH with a MOD1 as first stage, the dead zone of the overall
modulator will be ~1/A however many stages there are in the structure.

Thus, comparing MASH with single-loop designs, MASH offers a wider stable input range
(as it is guaranteed to be stable for inputs up to 1), but dead zones will also be larger (for
the same integrator gain A).

1.2.2 1+1+1 MASH Third-order Loop with Sine Wave input.

Close all Simulink windows except “sweep_testbench.mdl” (open it if it is not already

open). Double click on the dut to open the 1+1+1 MASH modulator schematic and then
double click any of the blue time scope icons to open the time scope.
Select the sine wave input of “sweep_testbench.mdl” by typing “swpctrl.select = 1” in the
Matlab Command Window. As before, the workspace variable “sinamp” sets the amplitude
of this sine wave and “sinfreq” sets the frequency.

Reset all integrator gains to +inf (a quick way to do this is to execute “init_vars3” again in
the command window) and then type and execute
“target_modulator=’mod3_1plus1pus1MASH’” in the Matlab Command Window.

Set “sinamp = 0.707” and “sinfreq = 4882.8125” if they are not already set to these values.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window. Once complete, type “Qout_SNDR” in the Matlab
Command Window to see the modulator output spectrum and simulated SQNR.

1. Estimate the slope of the output spectrum in the passband. Is this what you would
expect?
2. Note the reported signal to noise ratio given by “Qout_SNDR” for sinamp = 0.707
and compare it to the theoretical maximum for a third-order modulator given by the
formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 (
)
2L + 1
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=1 (note that we expect an error based only on E3, which is a 1-bit quantiser).
Recall that this is the theoretical OSR for a full-scale input sinamp = 1 (0dB). We
have used sinamp = 0.707 (-3 dB), so modify your calculation appropriately when
comparing.
3. Zoom in on the modulator output in the time scope for sinamp = 0.707. How does it
compare with the 1-bit CRFF modulator outputs? (Just comment here, don’t look for
deep meaning.)

Modulator output spectral density (Units/sqrt(Hz))

0
10
Simulated:
SQNR = 106.1 dB Brickwall LPF @ fs/(2.OSR)
-2
10
ENOB = 17.3
Unit/sqrt(Hz)

10 -4

10 -6

10 -8

10 -10
10 1 10 2 10 3 10 4 10 5 10 6
Frequency(Hz)

The slope in the passband is ≈60dB/dec as it would be expected from a 3rd order structure.
This can be verified by taking two points from the plot: e.g. A1=3.386e-9 at f1=2441Hz and
A2=7.401e-8 at f2=7446Hz → slope≈20log10(A2/A1)/log10(f2/f1)=55.3dB/dec.

The SQNR predicted by theory is 112.8dB-3dB = 109.8dB (which is similar to the 106.1dB
observed in the above simulation).

For a 1bit CRFF the modulator output can only be -1 or +1. Thus, for a sinewave input, we
see the density of -1s and +1s in the output sequence varying as per the sinewave. For
the MASH structure, on the other hand, Qout can take on a range of values (due to the
use of 2-bit quantisers in the first two stages, and digital recombination), and now it is the
envelop of Qout that is displaying the sinewave.

Set “sinamp = 0.1” and run the simulation by selecting “Simulation > Start” or pressing
<ctrl>T in the “sweep_testbench.mdl” window. Once complete, type “Qout_SNDR” in the
Matlab Command Window to see the modulator output spectrum and simulated SQNR.

1. How does the simulated SQNR for sinamp = 0.1 compare with that obtained
previously for the CRFF MOD3 with 1-bit quantisation? Are both third-order
modulators with 1-bit quantisation identical for passband performance? If not then
why? What can differ? (Hint: recall from lab 3 the comments about stability, the
Gerzon-Craven theorem and signal-band penalties.)
2. How do the shapes of the noise spectra (i.e. the NTFs) of the CRFF and MASH
modulator compare near Fs/2 (500 kHz)? Why do they differ (think about Lee’s Rule,
see section 4.2.1 of [1], and the comments in lab 3 about modifying the NTF)?
Unit/sqrt(Hz)

1+1+1 MASH CRFF

We get a higher simulated SQNR for 1+1+1 MASH compared with CRFF due to higher
noise suppression in the pass-band. To understand this, it is best to refer to Figure 2 in the
lab sheets for Lab 3. An ideal 1+1+1 MASH corresponds to the MOD3 curve, so it has
lower NTF in the pass-band (leading to higher SQNR in the ideal case). For CRFF on the
other hand (because it is a higher-order single loop design), we need to reduce the high
freq NTF gain (as per Lee's rule) to ensure stability. However, as a consequence, the NTF
in the low frequency range is raised (due to the Gerzon-Craven theorem), leading to lower
SQNR. This of course assumes a 1+1+1 MASH with perfect matching between NTF1,
NTF2 and the digital H filters which cannot be fully achieved in practice.

In terms of the shape of the high-frequency end of the spectrum, in the case of MASH it
rises (largely) linearly, whereas for CRFF it plateaus out as Fs/2 is approached.

We will now investigate the sensitivity of the 1+1+1 MASH modulator to integrator finite dc
gain errors in the sub-modulators with the sine wave input.

Close all windows and type “target_modulator = ‘mod3_1plus1plus1MASH’” in the Matlab

Command Window.

First, obtain a plot of SQNR versus input amplitude for the MASH modulator with ideal
integrators by running “sweep_sin_ampl_sqnr”. Make a copy of this plot for reference.
 1. Note the amplitude giving maximum SQNR and the peak SQNR and compare these
to the maximum results for the CRFF modulators with1- to 3-bits quantisation.
2. Note the maximum signal to noise ratio and compare it to the theoretical maximum
for a third-order modulator given by the formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 ()
2L + 1
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=1 (note that we expect an error based only on E3, which is a 1-bit quantiser).
SQNDR (dB)

The peak SQNR is 108.8dB (similar to theoretical prediction of 112.8dB) and is obtained at
full scale amplitude (sinamp=1). We note that for CRFF MOD3 we obtained a peak SQNR
of 84.9dB (at -5dBFS/0.56) in the 1-bit case and a peak SQNR of 107.4dB (at -
1dBFS/0.89) with 3-bit quantisation. Thus assuming ideal integrators (and no coefficient
mismatch etc.), the 1+1+1 MASH will provide significantly higher SQNR than the 1-bit
CRFF MOD3, and a similar SQNR as the 3-bit CRFF MOD3.

Now investigate the sensitivity of the 1+1+1 MASH modulator to integrator finite gain.

Set the third loop integrator dc gain to 50 by typing “modctrl.igain3=50” then re-run the
amplitude sweep by typing “sweep_sin_ampl_sqnr”. Keep the resulting the plot window
open.

Now set only the second loop integrator dc gain to 50 by typing “modctrl.igain3=inf”,
“modctrl.igain2=50” and then re-run by typing “sweep_sin_ampl_sqnr”. Keep the resulting
plot window open.

Finally, set only the first loop integrator gain to 50 by typing “modctrl.igain2=inf”,
“modctrl.igain1=50” and then re-run by typing “sweep_sin_ampl_sqnr”. Keep the resulting
plot window open.

1. Compare all 4 plots (all integrators ideal and each of only one with finite dc gain 50).
2. Is the MASH modulator SQNR equally sensitive to low integrator gain in all sub-
modulators?
3. If not then which sub-modulator loop is most sensitive to low gain and which is least
sensitive. Why is this? Explain why the overall SQNR has widely different sensitivity
to the different integrators being non-ideal; if you are not sure then proceed to the
next section (and ask a demonstrator if you still aren’t sure).
 Signal-to-quantisation-noise-and-distortion versus 4883 Hz sine input amplitude
for modulator mod3 1 plus1plus1MASH

70

65
X0
Y 65.6603
60
SQNDR (dB)

55

50

45

40
-60 -50 -40 -30 -20 -10 0
Input amplitude (dBFS)

IGAIN3=50 IGAIN2=50 IGAIN1=50

The SQNR is most sensitive to first loop integrator being non-ideal (44dB drop in peak
SQNR); it is also quite sensitive to the second loop integrator being non-ideal (17dB drop)
but changes only minimally (<1dB drop) when the third loop integrator is made non-ideal.

This is because finite IGAIN1 leads to NTF1 deviating (increasing in the signal band) from
the model assumed in the digital filters, and thus we get inaccurate cancellation of the first
stage quantisation noise, resulting in first-order-shaped noise leaking into the output of the
modulator (in fact the shaping will be even less as a finite integrator gain increases the
NTF in the pass band). On the other hand, in the case of a finite IGAIN2, it is second-
order-shaped noise that appears in the output (which has lower power in the signal band).
A finite IGAIN3 purely affects the level of third-order-shaped noise in output (which is of
lower power still).

To get a better feel for what happened in the last experiment, we will now look at what
happens to the modulator output spectrum as the integrators are made non-ideal.

Close all windows except “sweep_testbench.mdl” (open it if it was closed by running

“sweep_sin_ampl_sqnr”).

Reset all integrators to ideal and also reset all other simulation variables by typing
“init_vars3”. To make the PSD results of this experiment clearer, now type
“swpctrl.trantime = 0.1” and “modctrl.dgain1 = 0.1”.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window. Once complete type “Qout_SNDR” in the Matlab
Command Window to see the modulator output spectrum and simulated SQNR. Keep this
window open (and/or make a hard-copy).

Set the gain of the third loop integrator dc gain to 20 by typing “modctrl.igain3=20” then re-
run the simulation and type “Qout_SNDR”. Keep the resulting the plot window open.

Now set the second loop integrator dc gain to 20 by typing “modctrl.igain2=20” (no need to
reset igain3 to inf again) and then then re-run the simulation and type “Qout_SNDR”. Keep
the resulting plot window open.

Finally, set the first loop integrator gain to 20 by typing “modctrl.igain1=20” and then then
re-run the simulation and type “Qout_SNDR”. Keep the resulting plot window open.

1. Compare all 4 plots (all integrators ideal and with finite dc gains). In particular, what
are the slopes of the output noise spectrum in the pass-band in all 4 cases? What
does this tell you about which modulator noise is dominating the MASH output in
each case? Why does this modulator dominate in each case?
 Modulator output spectral density (Units/sqrt(Hz))

10 0

10-1 Simulated:
SQNR = 52.0 dB Brickwall LPF @ fs/(2.OSR)
10-2 ENOB = 8.3

10-3

10-4

10-5

10-6
10 1 102 103 104 105 10 6
Frequency(Hz)

IGAIN=INF IGAIN3=20 IGAIN2=20 IGAIN1=20

The plot for IGAIN=INF has a slope of 60dB/dec in the pass-band as would be expected
from a 3rd order modulator. The noise is thus dominated by the third stage quantisation
error (which is third-order shaped). For IGAIN3=20, the slope reduces to nearer 40dB/dec.
The noise is still mostly from the third stage quantisation error, but this noise has
increased in the signal band due to the finite integrator gain. When IGAIN2 is reduced to
20 as well, second stage quantisation error starts to dominate (due to the inaccurate
cancellation of NTF2), and therefore we see a further reduction in the slope (to near
20dB/dec). Reducing IGAIN1=20 subsequently, makes the first stage quantisation error
the dominant one (as NTF1 is no longer cancelled properly), which should, in theory be
first-order-shaped, but in fact has more of a flat profile in the signal band (the finite
integrator gain “flattening” NTF1 in the signal band).

1.3 A 2+1 MASH Third-order Modulator.

Close all Simulink windows except “sweep_testbench.mdl” (open it if it is not already

open). Right click on the dut and edit “Model Name” under “ModelReference Parameters”
to “mod3_2plus1MASH.mdl”. Double click on the dut to open the 2+1 MASH modulator
schematic and then double click any of the blue icons to open the time scope.

This MASH modulator achieves an overall third-order noise shaping by cascading a

second order and a first order modulator, and is hence commonly called a “2+1” MASH
modulator (cascading a first and second order would be “1+2” etc.). The second-order
stage is the Steensgard-Silva modulator seen in laboratory 2, now with a 2-bit quantiser to
help stabilise the quantiser gain and hence NTF, and the second modulator is again a
simple MOD1 with 1-bit quantisation.

(Possibly interesting note: this exact modulator was used to implement a 100 dB SNR
ADC present in the audio CODECs in all the early iPods and iPhones, where it was used
for production loopback testing of the audio output paths.)

A useful property here of the Steensgard-Silva modulator is that the quantisation error is
already available in analogue form at the output of the second integrator (delayed by 2
clock cycles and inverted, so giving -z-2E1), saving the need to add an additional analogue
differencing stage to compute this error, with associated scope for further analogue/digital
matching errors. The Simulink schematic “mod2_2plus1MASH_v2.mdl” shows how the
quantisation error could be obtained if you didn’t spot the fact that it was already available.

In the next experiments we will compare this modulator to the earlier CRFF 1-bit and
1+1+1 MASH third-order modulators.

1.3.1 DC Input behaviour of the 2+1 MASH DSM

Double-click any of the blue scope icons in the modulator schematic to open the time
scope.

Reset all modulator variables by rerunning “init_vars3” and then type “swpctrl.select = 2” to
select the dc input. Ensure “input_dc = 0” and run the simulation by selecting “Simulation >
Start” or pressing <ctrl>T in the “sweep_testbench.mdl” window. Type “Qout_SNDR” to
see the modulator output spectrum and “mean(Qout)” to see the dc content of the
modulator output.

1. Observe the integrator outputs. Are they bounded? Is the modulator stable?
2. Compare the mean modulator output with input_dc? Are they a good match? Has
the modulator implemented a dc accurate analogue to digital conversion (i.e. what
sort of error do you see between input_dc and mean(Qout)?
3. Zoom in on a few cycles of Qout and look at the output spectrum. Is this modulator
tonal for dc input 0 as seen with the earlier single-loop third-order modulator?

Modulator is stable (integrator outputs are bounded). Mean(Qout) is very close to 0, so the
modulator is performing a dc-accurate analogue to digital conversion. The output has
strong tones, though they are all out-of-band.

Repeat the above exercise for input_dc values from +0.25 to +1.25 in increments of 0.25.

1. Does the modulator stay stable for all inputs up to the maximum possible full-scale
limit of +1? How does this compare to the CRFF modulators?
2. Is the modulator an accurate converter for dc inputs inside the stable input range;
what sort of percentage error do you see between input_dc and mean(Qout)?
3. Is this modulator tonal for rational dc inputs in its stable input range (as seen for all
previous modulators)? How could you address this?
4.
input_dc = 0.25
input_dc = 0.5

input_dc = 0.75

input_dc = 1
 Modulator output spectral density (Units/sqrt(Hz))

10 0 Simulated:
SQNR = -126.2 dB Brickwall LPF @ fs/(2.OSR)
ENOB = -21.2
10 -2

10 -4

10 -6

10 -8

10 -10
10 1 10 2 10 3 104 10 5 10 6
Frequency(Hz)

In all of the above cases, Mean(Qout) is very close to input_dc, so the modulator is
performing a dc-accurate analogue to digital conversion. The output has strong idle tones,
although they are out-of-band for the dc input levels considered. In practice it would be
prudent to use dither to eliminate tones. We note that the modulator is stable up to (and
including) an input of 1, which is not the case for a higher-order, single-loop structure.

input_dc = 1.25
Unit/sqrt(Hz)

The modulator has now become unstable, due to input_dc being > 1.

Earlier we saw that the CRFF third-order modulator with 1-bit quantisation still performed
well even for very modest integrator dc gains, while the 1+1+1 MASH modulator did not
tolerate low integrator dc gain at all well (in fact, it was utterly terrible). We will now
examine the tolerance of the 2+1 MASH third-order modulator to finite dc gain in the
integrators.

Close all Simulink windows and type “target_modulator=’mod3_2plus1MASH’” and then

run “sweep_dc_dc” to obtain a dc transfer function of the MASH modulator for dc inputs
around zero with infinite (default) dc integrator gains. Do not close this window.

Now set the dc gain of all integrators to 10 by typing “modctrl.igain1=10”,

“modctrl.igain2=10” and “modctrl.igain3=10” and then run “sweep_dc_dc” again and
compare the results with the CRFF and 1+1+1 MASH modulators.
 1. Compare the dc transfer functions for the 1+1+1 DSM and 2+1 DSM with all
integrators ideal and all integrators with dc gain 10. Which modulator is more
tolerant of low integrator gain? Explain why you get the result you do.
2. How does the 2+1 MASH DSM compare with the CRFF 2-bit modulators for dead-
zone behaviour? Which would you expect to have the smallest dead-zone around
input=0?
(For fairness, because the MOD2 stage in the MASH modulator uses 2-bit
quantisation, we must compare with the 2-bit CRFF modulator; dead-zone widths
decrease as the quantisation levels move closer, so can always be reduced by
adding more quantisation levels.)
dc input (green) and output (red)

IGAIN = inf IGAIN = 10

The 2+1 MASH is much more tolerant to low integrator gain than the 1+1+1 MASH, as
demonstrated by the significantly smaller deadzones on the dc output vs dc input plot. This
is because the size of deadzones is set by the first stage, which is now a MOD2, making
deadzones proportional to 1/A^2 rather than 1/A.
dc input (green) and output (red)

The 2-bit CRFF MOD3 has smaller still deadzones (the deadzone around dc_input=0 has
width 0.002 compared with 0.004 for 2+1 MASH). This is to be expected, as the
deadzones are proportional to 1/A^3.
1.3.2 2+1 MASH Third-order Loop with Sine Wave input.

Close all Simulink windows except “sweep_testbench.mdl” (open it if it is not already

open). Double click on the dut to open the 2+1 MASH modulator schematic and then
double click any of the blue scope icons to open the time scope.

Select the sine wave input of “sweep_testbench.mdl” by typing “swpctrl.select = 1” in the

Matlab Command Window.

Reset all integrator gains to +inf (a quick way to do this is to execute “init_vars3” again in
the command window) and ensure “target_modulator=’mod3_2pus1MASH’”.

As before, the workspace variable “sinamp” sets the amplitude of this sine wave and
“sinfreq” sets the frequency. Set “sinamp = 0.707” and “sinfreq = 4882.8125” if they are not
already set to these values.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window. Once complete, type “Qout_SNDR” in the Matlab
Command Window to see the modulator output spectrum and simulated SQNR.

1. Estimate the slope of the output spectrum in the passband? Is this what you would
expect?
2. Note the reported signal to noise ratio given by “Qout_SNDR” for sinamp = 0.707
and compare it to the theoretical maximum for a third-order modulator given by the
formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 ( )
2L + 1
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=1 (note that we expect an error based only on E3, which is a 1-bit quantiser).
Recall that this is the theoretical OSR for a full-scale input sinamp = 1 (0dB). We
have used sinamp = 0.707 (-3 dB), so modify your calculation appropriately when
comparing.
3. Zoom in on the modulator output in the time scope for sinamp = 0.707. Does it look
like there are many quantisation levels? Should there be (does it use multi-level
quantisation)? Does the MASH modulator output follow the input sine wave as seen
as before with the 3-bit CRFF modulator? If not then why not?
The slope in the passband is ≈60dB/dec as it would be expected from a 3rd order structure.

The SQNR predicted by theory is 112.8dB-3dB = 109.8dB (which is similar to the 104.9dB
observed in the above simulation).

There are multiple levels in the modulator output to the use of a 2-bit quantiser in the first
stage, and the fact that the quantiser outputs of the two stages are digitally filtered and
recombined.

The modulator output (or its envelop) is seen follow the input sinewave, but not as clearly
as in the case of the 3-bit CRFF modulator (due to an increased level of out-of-band
quantisation noise).

We will now investigate the sensitivity of the 2+1 MASH modulator to integrator finite dc
gain errors in the sub-modulators with the sine wave input.

Close all Simulink windows and check “target_modulator = ‘mod3_2plus1MASH’” in the

Matlab Command Window.

First, obtain a plot of SQNR versus input amplitude for the MASH modulator with ideal
integrators by running “sweep_sin_ampl_sqnr”. You may wish to make a copy of this plot
for reference.

1. Note the amplitude giving maximum SQNR and the peak SQNR and compare these
to the maximum results for the CRFF modulators with 1- to 3-bits quantisation and
the 1+1+1 MASH DSM.
2. Note the maximum signal to noise ratio and compare it to the theoretical maximum
for a third-order modulator given by the formula:
π 2L
SQNR = 6.02.N + 1.76 + (20 L + 10) log10 (OSR) − 10 log10 ()
2L + 1
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=1 (note that we expect an error based only on E3, which is a 1-bit quantiser).
 SQNDR (dB)

The peak SQNR is 108dB (similar to theoretical prediction of 112.8dB) and is obtained at
an amplitude of -2dBFS (0.79). By comparison, for the 1+1+1 MASH, we got a similar
peak SQNR value of 108.8dB, but at full scale amplitude (as the first stage is MOD1 rather
than MOD2 it is unaffected by quantiser overload as the input amplitude approaches 1).

For CRFF MOD3 we obtained a peak SQNR of 84.9dB (at -5dBFS/0.56) in the 1-bit case
and a peak SQNR of 107.4dB (at -1dBFS/0.89) with 3-bit quantisation. Thus assuming
ideal integrators (and no coefficient mismatch etc.), the 2+1 MASH will provide significantly
higher SQNR than the 1-bit CRFF MOD3, and a similar SQNR as the 3-bit CRFF MOD3.

Now investigate the sensitivity of the 2+1 MASH modulator to integrator finite gain with
sine wave input.

Set the third loop integrator dc gain to 50 by typing “modctrl.igain3=50” then re-run the
amplitude sweep by typing “sweep_sin_ampl_sqnr”. Keep the resulting the plot window
open.

Now set only the second loop integrator dc gain to 50 by typing “modctrl.igain3=inf”,
“modctrl.igain2=50” and then re-run by typing “sweep_sin_ampl_sqnr”. Keep the resulting
plot window open.

Finally, set only the first loop integrator gain to 50 by typing “modctrl.igain2=inf”,
“modctrl.igain1=50” and then re-run by typing “sweep_sin_ampl_sqnr”. Keep the resulting
plot window open.

1. Compare all 4 plots (all integrators ideal and only one with dc gain 50).
2. Is the MASH modulator SQNR equally sensitive to low gain in all integrators?
3. If not then which integrators(s) give most sensitive to low gain and which is(are)
least sensitive. Why is this?
4. Compare the results obtained for the 2+1 MASH modulator against those obtained
with the 1+1+1 MASH modulator? Which MASH modulator is most sensitive to low
integrator gain? Why?
 IGAIN3=50 IGAIN2=50 IGAIN1=50

The SQNR is equally sensitive to the first two integrators having low gain (14dB drop in
SQNR), whilst a low gain in the 3rd integrator (belonging to the MOD1 stage) has hardly
any effect on the SQNR. This is because finite IGAIN1 and IGAIN2 both lead to NTF1 –
the NTF of the MOD2 stage - deviating from the model assumed in the digital filters, and
thus we get inaccurate cancellation of the first stage quantisation noise, resulting in
second-order-shaped noise leaking into the output of the modulator (in fact the shaping will
be even less as a finite integrator gain increases the NTF in the pass band). On the other
hand, a finite IGAIN3 purely affects the level of third-order-shaped noise in output (which is
of lower power than the first stage quantisation noise in the signal band).

On the whole, 2+1 MASH is less sensitive to low integrator gain, as the (dominant)
quantisation noise leaking into the output due to improper NTF cancellation is from a first
stage that is MOD2 rather than MOD1. Setting all integrators to IGAIN=50 does not have
the catastrophic effects on SQNR as with 1+1+1 MASH.

As done for the 1+1+1 modulator, to get a better feel for what happened in the last
experiment, we will now look at what happens to the modulator output spectrum as the
integrators are made non-ideal.

Close all windows except “sweep_testbench.mdl” (open it if it was closed by running

“sweep_sin_ampl_sqnr”).

Reset all integrators to ideal and all other simulation variables by typing “init_vars3”. To
make the results of this experiment clearer, then type “swpctrl.trantime = 0.1” and
“modctrl.dgain1 = 0.1”.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window. Once complete type “Qout_SNDR” in the Matlab
Command Window to see the modulator output spectrum and simulated SQNR.

Set the dc gain of the third integrator to 20 by typing “modctrl.igain3=20” then re-run the
simulation and type “Qout_SNDR”. Keep the resulting the plot window open.

Now set the second integrator dc gain to 20 by typing “modctrl.igain2=20” then

“modctrl.igain3=inf” and then re-run the simulation and type “Qout_SNDR”. Keep the
resulting plot window open.

Now reset the second integrator gain and set the first to 20 by typing “modctrl.igain2=inf”
then “modctrl.igain1=20” and then then re-run the simulation and type “Qout_SNDR”. Keep
the resulting plot window open.
Finally, set all gains to 20 by typing “modctrl.igain2=20” and then then re-run the
simulation and type “Qout_SNDR”. Keep the resulting plot window open.

1. Compare all 5 plots (all integrators ideal, with only one with dc gain 20 and with all
set to 20). What are the slopes of the output noise spectrum in the pass-band in all
5 cases? What does this tell you about which integrator - or, rather, sub-modulator -
is dominating the output quantisation noise in each case? Why does this modulator
dominate in each case?
Modulator output spectral density (Units/sqrt(Hz))

10 0
Simulated:
SQNR = 81.9 dB Brickwall LPF @ fs/(2.OSR)
-2
10
ENOB = 13.3
Unit/sqrt(Hz)

Unit/sqrt(Hz)
10 -4

10 -6

10 -8

10 -10
10 1 10 2 10 3 10 4 10 5 10 6
Frequency(Hz)

IGAIN=INF IGAIN3=20 IGAIN2=20 IGAIN1=20 IGAIN=20

The plot for IGAIN=INF has a slope of 60dB/dec in the pass-band as would be expected
from a 3rd order modulator. The noise is thus dominated by the second stage quantisation
error (which is third-order shaped). For IGAIN3=20, the slope reduces to nearer 40dB/dec.
The noise is still mostly from the second stage quantisation error, but this noise has
increased in the signal band due to the finite integrator gain. When IGAIN1 or IGAIN2 is
reduced to 20, the first stage quantisation error starts to dominate (due to the inaccurate
cancellation of NTF1), and therefore we see a further reduction in the slope (to near
20dB/dec). Setting all gains to IGAIN=20 makes NTF1 deviate even further from its ideal
transfer function. Thus the cancellation of NTF1 becomes even less accurate (and NTF1
higher still in the signal band), leading to even more first stage quantisation error
appearing in the modulator output. As a consequence, the output noise spectrum rises and
becomes flatter in the signal band.

1.4 Additional MASH modulator sensitivities.

So far we have examined only the effects of integrator gain for the example 1+1+1 and
2+1 MASH modulators. However, other types of non-ideal behaviour of real modulators
can impede complete cancellation of quantisation noises from the intermediate modulator
stages in a MASH cascade. Two particular non-ideal effects are:

• Quantiser gain and its effect on loop NTF

• Gain errors in the modulator signal paths caused by analogue component
mismatches – this is usually the dominant error source in analogue modulators
where good-quality integrators are available.

Quantiser gain

Recall from laboratory session 1 and the course text [1] sections 2.1.1, 3.1, 3.2 and 6.1
that an effective gain can be defined for a quantiser, and for a single-bit (2 level) quantiser
this gain can be very dependent on the size of the quantiser input. Changes in the
effective quantiser gain as the modulator input signal changes can cause significant
changes in the NTF (and in the case of high-order loops can even result in unstable NTFs
as seen in lab 3). Since the NTFs of the sub-modulators are now input signal dependent
and not very well-defined as a result, it is not (reasonably) possible to specify them exactly
in the digital recombination arithmetic to obtain perfect cancellation of quantisation errors
from the intermediate modulators in a the MASH cascade.
Using more than 2 quantisation levels can really help stabilise the gain and hence NTF to
aid cancellation of the analogue and digital terms. This is why all the examples seen so far
used 2-bit (4 level) quantisation in those stages where quantisation error was to be
cancelled. We will not experiment with this effect here, but after the lab you may wish to
make a copy of the 1+1+1 and/or 2+1 MASH modulator and replace the 2-bit quantiser(s)
in the first sub-modulator(s) with a copy of the 1-bit quantiser from the final sub-modulator
and then see if you can achieve as stable third-order noise shaping.

Note that in this case all the modulator components are actually ideal, the problem is in
achieving the well-defined NTFs from the sub-modulators needed to cancel intermediate-
stage quantisation errors when the individual modulator outputs are recombined. Note
further that because this effect is due to system-level quantiser gain effects, not non-ideal
components, it can affect even an all-digital MASH modulator that uses single-bit word-
length truncation in its intermediate modulator stages.

Signal path gain

Another important error source in MASH modulator design is simple gain path errors due
to analogue component matching errors. For example, mismatches in the input capacitors
and feedback DAC capacitors of the input integrator in a switched-capacitor realisation of
an analogue modulator may result in a small gain error at the modulator input (e.g. in the
1+1+1 MASH example, component mismatches in the input to the second MOD1 loop may
result in the loop input really being 0.995E1 or 1.003E1 instead of E1).

Clearly the exact signal path gain error mechanisms are very circuit-dependent, we can
get a feel for their approximate their aggregate effect by applying overall scaling errors to
each modulator output – this is the purpose of the blue scaling blocks in the
mod3_1plus1plus1MASH and mod3_2plus1MASH Simulink models.

We will now examine the sensitivities of our modulators to such gain errors.

Close any Simulink and plot windows open and reset all modulator variables by re-
executing “init_vars3”.

Now open Simulink schematic “sweep_testbench.mdl” and edit the model reference
parameter of “dut” to “mod3_1plus1plus1MASH.mdl’

Type “swpctrl.select = 1” to ensure that the sinewave input is selected and then run the
simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window.

Once complete, type “Qout_SNDR” in the Matlab Command Window to see the modulator
output spectrum and simulated SQNR. Keep a copy of the spectrum and note the SQNR.

Now obtain a plot of the first modulator loop’s performance by typing “Qout = Qout1;” and
then again executing “Qout_SNDR”. Again, make a note of the reported SQNR.

Now introduce a -1% gain error at the input to the third modulator by typing
“modctrl.mgain3 = 0.99” and rerun the simulation and “Qout_SNDR”. Make a note of the
reported SQNR. Repeat this for gain errors or -2%, -3%, -4% and -5%
 1. Observe the change in SQNR with the gain error at the input of the third modulator.
Is there much sensitivity to errors at this point?

No gain error
Unit/sqrt(Hz)

Unit/sqrt(Hz)

Modulator output 1st stage output

3rd stage input gain error

Unit/sqrt(Hz)
-1% -2% -3% -4%

-5%
The effect of the error on the SQNR is low, with only a 5dB drop in SQNR even at 5% gain
error (the error is only affecting the cancellation of 2nd-order shaped noise from the 2nd
stage of the modulator).

Now type “modctrl.mgain3 = 1” to remove any gain error at the input of the third sub-
modulator and then type “modctrl.mgain2 = 0.999” to introduce a -0.1% gain error at the
input to the second modulator.

Run the simulation by selecting “Simulation > Start” or pressing <ctrl>T in the
“sweep_testbench.mdl” window.

Once complete, type “Qout_SNDR” in the Matlab Command Window to see the modulator
output spectrum and simulated SQNR. Keep a copy of the spectrum and note the SQNR.

As before, repeat the above procedure for gain errors of -0.5%, -1%, -2%, -3%, -4% and -
5%.

1. Observe the change in SQNR with the gain error at the input of the second
modulator. How does it compare to gain error at the third modulator input? Is there
less, similar, or much increased sensitivity to errors at this point?
2. Can you explain your results for the gain errors at the input to the second and third
modulator stages? Can you find a simple rule that explains them?
 Hints: Start with explaining the effects or gain error at the second modulator input.
First note the SQNR you found earlier for the first modulator output (“Qout1”) and
then think about how much it would need to be reduced by to be insignificant
compared to the reported SQNR for the ideal MASH modulator. Remember – the
objective is to (ideally) cancel all E1 and E2 contributions to the final output. Note
that a 99% gain error “modctrl.mgain2” corresponds to leaving a residual 1% of E1
un-cancelled at the output. What is 1% in dB? So what sort of SQNR due to the E1
residual would you expect? What is 2% in dB and so how much E1 would remain
etc.?
3. What sort of gain error can you tolerate in order to keep the overall SQNR above
100 dB? Is it reasonable to design circuits to have this sort of gain error?

2nd stage input gain error

Modulator output spectral density (Units/sqrt(Hz))
10 0
Simulated:
SQNR = 89.8 dB Brickwall LPF @ fs/(2.OSR)
10-2 ENOB = 14.6

Unit/sqrt(Hz)
10-4

10-6

10-8

10-10
101 102 103 10 4 105 106
Frequency(Hz)

-0.1% -0.5% -1% -2%

Modulator output spectral density (Units/sqrt(Hz))
10 0

Simulated:
SQNR = 86.5 dB Brickwall LPF @ fs/(2.OSR)
10 -2 ENOB = 14.1
Unit/sqrt(Hz)

-4
10

10 -6

10 -8

10 -10
10 1 10 2 10 3 104 10 5 10 6
Frequency(Hz)

-3% -4% -5%

This time, the SQNR is much more sensitive to gain errors, as these lead to first-order
shaped quantisation noise (from the 1st stage) being inaccurate cancelled, and leaking to
the modulator output (we can observed this from the appearance of tones in the spectrum,
as also present in the output of the first stage). A 5% gain error now results in a dramatic,
24dB loss in SQNR.

As observed previously, the 1st stage provides an SQNR of 56.1dB, whilst the modulator
as a whole has an SQNR has an SQNR 106.1dB (in ideal circumstances). Thus, the 2nd
and 3rd stages need to provide an additional reduction of quantisation noise of 50dB, in
other words, the first-stage noise needs to be reduced to 10^(-50/20)=0.3%, which
requires the cancellation of at least 99.7% of the first-stage noise (so the 2nd stage gain
error needs to be <0.3%).

However, with a 2nd stage gain error of 1%, the first-stage noise can only be reduced by -
20*log10(0.01) = 40dB at best (so SQNR <56.1dB+40dB=96.1dBdB, which is very close to
what is observed in simulation). Similarly, with a 2nd stage gain error of 2%, we get a noise
reduction of 20*log10(0.02) = 34dB at best (so SQNR <56.1dB+34dB=90.1dB, which is
very close to what is observed in simulation).

The modulator can tolerate a gain error of 0.5% and still achieve an SQNR>100dB. Whilst
this is achievable with CMOS technology, it may require careful design (we note that the
gain error lumps together multiple possible analogue component mismatches).
Repeat the above exercise for “mod3_2plus1MASH.mdl”.

1. How does the gain error sensitivity of the 2+1 modulator compare to that of the
1+1+1 modulator? Is it much less sensitive, similarly sensitive or much more
sensitive? Why would this be?
2. Important: Based on your observations and any knowledge of IC process matching
you may have, what sort of upper-limit is reasonable for how far MASH modulation
can be used to boost the overall modulator SQNR over the SQNR for the first
(input) modulator stage? (This is your rule-of-thumb guide as to whether or not a
proposed MASH modulation scheme will work in practice.)

Modulator output (0% error)

Unit/sqrt(Hz)

1st stage output

2nd stage input gain error

Unit/sqrt(Hz)

Unit/sqrt(Hz)

-1% -2% -3% -4% -5%

The performance of the 2+1 modulator is much less sensitive to gain error than in the
1+1+1 modulator, as the inaccurate cancellation of the 1st stage gain error leads to the
leakage of 2nd order shaped noise (rather than 1st order noise) to the output of the
modulator.

The 1st stage provides already provides an SQNR of 82.8dB, so to achieve the 104.9dB
provided by the modulator as a whole (in ideal circumstances), the 2nd stage only needs to
provide an additional reduction of quantisation noise of 22.1dB. In other words, the first-
stage noise needs to be reduced to 10^(-22.1/20)=7.9%, which requires the cancellation of
at least 92.1% of the first-stage noise (so the 2nd stage gain error needs to be <7.9%).

To get an SQNR of >100dB, the gain error has to be <13.8%, which is much more readily
achievable than <0.5% for 1+1+1 MASH.

In practice, a 1% gain error would be a conservative estimate for the level easily
achievable in modern IC processes (the mismatch effecting individual components being
around 0.1-0.2%). This equates to an upper limit of 40dB in terms of how far MASH
modulation can be used to boost the overall modulator SQNR over the SQNR for the first
modulator stage.
1.5 SMASH modulators (for interest, not examinable)

A relatively recent development is the Sturdy MASH (SMASH) modulator. These have
been a very active research topic and offer a sort of halfway-house between the stability
problems of single-loop modulators and the gain sensitivity problems of pure MASH
modulators.

In a SMASH modulator the analogue NTFs are not approximated in a digital recombination
path for the quantiser outputs. Instead, the NTF processing required for recombining the
quantiser outputs is obtained by re-using the analogue loops to ensure good NTF
matching. For example, in a 1+1 SMASH modulator, rather than generating a term such as
NTF1.E2 using a digital representation of NTF1, the second stage quantisation error is
actually processed using the first modulator loop. This ensures that the same NTFs are
seen in the signal processing and recombination paths and hence results in a modulator
much more tolerant of low integrator gain, path gain errors etc. However, the downside of
injecting later stage quantisation errors back into earlier modulator stages is that long
loops of integrators are created and stability is not guaranteed (the SMASH literature has
been suspiciously silent on the issue of stability so far).

You can experiment with a SMASH modulator variation on “mod3_2plus1_MASH_v2.mdl”

using the Simulink schematic “mod3_2plus1SMASH.mdl” in “LAB5”. In particular, you may
wish to compare the SMASH modulator’s sensitivity to effects such as finite integrator gain
and path gain errors with the MASH version. You should find it to be much less sensitive.

Next try changing “Gain5” and “Gain6” in the SMASH Simulink schematic both to 1 and
see what happens to the loop stability. Recall that the MASH variant is always stable, that
being a key basis of the MASH concept.

2.0 Learning review

This laboratory examined a new approach to obtaining high-order modulators: cascading a

series of (guaranteed stable) low-order modulators and cancelling their quantisation errors
to obtain an overall high-order NTF. These are known as MASH modulators.

Single-loop designs offer good tolerance to errors such as finite dc integrator gain and
small gain matching errors in the signal paths. However, they can be difficult to stabilise
due to having long chains of integrators in the NTF path, and may not give as aggressive
noise-shaping in the signal passband (as the penalty for reducing the maximum NTF gain
to improve stability).

MASH modulators offer unconditional loop stability with correspondingly wide input range,
and no NTF stability SQNR penalties, by being comprised only of unconditionally stable
loops. However, errors between the analogue and digital signal processing paths typically
make it difficult in practice to obtain more than 40 dB SQNR increase (roughly – this is not
a hard-and-fast figure) over the first modulator in the MASH cascade, and thus they may
not be a viable solution for all high SQNR applications.

There are thus a wide range of trade-offs in choosing a suitable modulator topology for
high SQNR applications requiring loop orders > 2, and given the empirical/heuristic nature
of much DSM theory, experience and experiment still play a large role in choosing an
appropriate architecture (single-loop, MASH, SMASH etc.).
References:
[1] Schreier, Temes: Understanding Delta-Sigma Data Converters, Wiley-Blackwell 2004.