DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING COLLEGE OF ENGINEERING,

TRIVANDRUM

ANALOG INTEGRATED CIRCUITS AND

SIMULATION LAB -ECL 331

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

COLLEGE OF ENGINEERING, TRIVANDRUM
2019
 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING, TRIVANDRUM

CERTIFICATE
This is a controlled document of Department of Electronics & Communication of College of
Engineering, Trivandrum. No part of this can be reproduced in any form by any means without the
prior written permission of the Head of the Department, Electronics & Communication, College of
Engineering, Trivandrum. This is prepared as per 2019 KTU B.Tech Electronics & Communication
scheme.

Head of Dept. Dept. of ECE

College of Engineering Trivandrum
 ELECTRONICS & COMMUNICATION
ENGINEERING
SYLLABUS

ANALOG INTEGRATED CIRCUITS CATEGORY L T P CREDIT

ECL331
AND SIMULATION LAB PCC 0 0 3 2

Preamble: This course aims to (i) familiarize students with the Analog Integrated Circuits and
Design and implementation of application circuits using basic Analog Integrated Circuits (ii)
familiarize students with simulation of basic Analog Integrated Circuits.

Prerequisite: ECL202 Analog Circuits and Simulation Lab

Course Outcomes: After the completion of the course the student will be able to

CO 1 Use data sheets of basic Analog Integrated Circuits and design and implement
application circuits using Analog ICs.

CO 2 Design and simulate the application circuits with Analog Integrated Circuits using
simulation tools.
CO 3 Function effectively as an individual and in a team to accomplish the given task.

Mapping of course outcomes with program outcomes

PO1 PO 2 PO3 PO 4 PO5 PO 6 PO7 PO8 PO9 PO PO PO

10 11 12
CO1 3 3 3 2 2
CO2 3 3 3 2 3 2 2
CO3 2 2 2 2 3 2 3

Assessment
Mark distribution

Total CIE ESE ESE Duration

Marks
150 75 75 3 hours

Continuous Evaluation Pattern

Attendance : 15 marks
Continuous Assessment : 30 marks
Internal Test (Immediately before the second series test) : 30 marks
 ELECTRONICS & COMMUNICATION
ENGINEERING
End Semester Examination Pattern: The following guidelines should be followed regarding
awardof marks
(a) Preliminary work : 15 Marks
(b) Implementing the work/Conducting the experiment : 10 Marks
(c) Performance, result and inference (usage of equipments and trouble shooting): 25 Marks
(d) Viva voce : 20 marks
(e) Record : 5 Marks

General instructions: End-semester practical examination is to be conducted immediately

after the second series test covering entire syllabus given below. Evaluation is to be conducted
under the equal responsibility of both the internal and external examiners. The number of
candidates evaluated per day should not exceed 20. Students shall be allowed for the
examination only on submitting the duly certified record. The external examiner shall endorse
the record.

Course Level Assessment Questions (Examples only)

Course Outcome 1 (CO1): Use data sheets of basic Analog Integrated Circuits and design and
implement application circuits using Analog ICs.
1. Measure important opamp parameters of µA 741 and compare them with the data
provided in the data sheet
2. Design and implement a variable timer circuit using opamp
3. Design and implement a filter circuit to eliminate 50 Hz power line noise.
Course Outcome 2 and 3 (CO2 and CO3): Design and simulate the application circuits with
Analog Integrated Circuits using simulation tools.
1. Design a precission rectifier circuit using opamps and simulste it using SPICE
2. Design and simulate a counter ramp ADC
List of Experiments

I. Fundamentals of operational amplifiers and basic circuits [Minimum seven experiments

are to be done]
1. Familiarization of Operational amplifiers - Inverting and Non inverting amplifiers,
frequency response, Adder, Integrator, Comparators.
2. Measurement of Op-Amp parameters.
3. Difference Amplifier and Instrumentation amplifier.
4. Schmitt trigger circuit using Op–Amps.
5. Astable and Monostable multivibrator using Op-Amps.
6. Waveform generators using Op-Amps - Triangular and saw tooth
7. Wien bridge oscillator using Op-Amp - without & with amplitude stabilization.
 ELECTRONICS & COMMUNICATION
ENGINEERING
8. RC Phase shift Oscillator.
9. Active second order filters using Op-Amp (LPF, HPF, BPF and BSF).
10. Notch filters to eliminate the 50Hz power line frequency.
11. Precision rectifiers using Op-Amp.

II. Application circuits of 555 Timer/565 PLL/ Regulator(IC 723) ICs [ Minimum three
experiments are to be done]
1. Astable and Monostable multivibrator using Timer IC NE555
2. DC power supply using IC 723: Low voltage and high voltage configurations, Short
circuit and Fold-back protection.
3. A/D converters- counter ramp and flash type.
4. D/A Converters - R-2R ladder circuit
5. Study of PLL IC: free running frequency lock range capture range

III. Simulation experiments [The experiments shall be conducted using SPICE]

1. Simulation of any three circuits from Experiments 3, 5, 6, 7, 8, 9, 10 and 11 of section I
2. Simulation of Experiments 3 or 4 from section II

Textbooks
1. D. Roy Choudhary, Shail B Jain, “Linear Integrated Circuits,”
2. M. H. Rashid, “Introduction to Pspice Using Orcad for Circuits and Electronics”, Prentice Hall
 ELECTRONICS & COMMUNICATION
ENGINEERING
INDEX

Exp. Page
Date Name of the Experiment No. Marks Signature
No
Familiarization of Operational amplifiers -
1 Inverting and Non inverting amplifiers,
frequency response, Adder, Integrator,
comparators.
Measurement of Op-Amp parameters.
2

3 Difference Amplifier and Instrumentation

amplifier.

4 Schmitt trigger circuit using Op –Amps.

5 Astable and Monostable multivibrator using Op -
Amps.
6 Timer IC NE555

7 Triangular and square wave generators using Op-

Amps.
Wien bridge oscillator using Op-Amp - without
8
& with amplitude stabilization.
RC Phase shift Oscillator
9

10 Precision rectifiers using Op-Amp.

11 Active second order filters using Op-Amp (LPF,

HPF, BPF and BSF).
12 Notch filters to eliminate the 50Hz power line
frequency
13 IC Voltage Regulators

14 A/D converters- counter ramp and flash type.

15 D/A Converters- ladder circuit.

16 Simulation Experiments:
 ELECTRONICS & COMMUNICATION
ENGINEERING
EXP 1 DATE
Familiarization of operational amplifiers - inverting and non inverting
amplifiers, frequency response, adder, integrator, comparators.

Aim: To familiarize with basic operational amplifier integrated circuits.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory: Operational amplifier, in short, op-amp is a versatile device used to amplify AC and DC
signals. Though it was originally designed for computing mathematical operations such as
addition, multiplication, differentiation, integration etc., it is widely used for variety of
applications like oscillators, filters, regulators, clipping circuits, waveform generators etc.
The symbol of op-amp represents a circuit with two input terminals an output terminal
and two bias supply points.
The 741 IC: It is a frequency compensated and short circuit protected IC.741C is its
commercial version with operating temperature ranges from 00C to +700C. 741 needs positive
and negative dc sources for bias supply connections V + and V-. This is provided by either a dual
power supply or two power supplies. When dual power supply is used its positive terminal is
connected to the V+ pin of the IC and the negative terminal is connected to the V- pin of the IC.
The ground terminal of the dual power supply is connected to the ground point of the circuit.
When two power supplies are used positive terminal of one supply and negative terminal of the
other power supply are connected to the V+ and V- pins of the IC respectively.
Inverting Amplifier: This is one of the most popular op-amp circuits. The polarity of the input
voltage gets inverted at the output. If a sine wave is fed to the input of this amplifier, the output
will be an amplified sine wave with 1800 phase shift. The gain of the inverting amplifier is given
by A= -Rf/Ri. where Rf is the feedback resistance and Ri is the input resistance.
Noninverting Amplifier: This circuit provides a gain to the input signal without any change in
polarity. The gain of noninverting amplifier is given by A=1+R f/Ri. Input impedance is extremely
large.
Adder: This circuit gives the sum of two input voltages. Here an input voltage V i and a dc
voltage Vref are given as inputs to the adder. This is an inverting summing amplifier because the
out is the sum of inputs with a sign change. The minus sign in the expression for the output can
be avoided if necessary, by inverting the output once again using a unity gain inverting amplifier.
The output can be scaled by selecting the ratio R f/Ri. If this ratio is greater than 1 the circuit will
function as a summing amplifier.
Integrator: In an integrator circuit, the output voltage is integral of the input signal. The output
voltage of an integrator is given by

Vo = -1/R1Cf  Vi dt
o
 ELECTRONICS & COMMUNICATION
ENGINEERING
At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like
an open circuit. The gain of an integrator at low frequency can be limited by connecting a
resistor in shunt with capacitor.
Comparator: This circuit compares one analogue voltage level with another analogue voltage
level, or some preset reference voltage, VREF and produces an output signal based on this voltage
comparison. The op-amp voltage comparator compares the magnitudes of two voltage inputs and
determines which is the largest of the two.
The output saturation voltages are about 2V below the magnitudes of the dc power supply
levels. For supply voltages of (+-15V),Vsat will be approximately (+-13V).

Circuit diagram and waveforms:

op-amp symbol op-amp pin out equivalent circuit

Inverting amplifier
 ELECTRONICS & COMMUNICATION
ENGINEERING
Tabular Column & Frequency Response

F(Hz) V0 (volts) log f 20log(V0/Vin)db

Non inverting amplifier

Circuit Diagram & Waveform

Tabular Column & Frequency Response

F(Hz) V0 (volts) log f 20log(V0/Vin)db

 ELECTRONICS & COMMUNICATION
ENGINEERING
Adder

Circuit Diagram & Waveforms

Integrator
Circuit Diagram & Waveforms
 ELECTRONICS & COMMUNICATION
ENGINEERING
Tabular Column & Frequency Response

F(Hz) V0 (volts) log f 20log(V0/Vin)db

Comparator

Circuit Diagram & Waveforms

Design:
Inverting amplifier:

A = -Rf/R1
Take A = 1
Rf = R1
Choose Rf = , R1=
Non inverting amplifier:
A = 1+ Rf/R1
Take A =
Rf = R1
Choose Rf = , R1=

Adder:
 ELECTRONICS & COMMUNICATION
ENGINEERING
Integrator:

Let input frequency be ,f= 1 kHz

f = 1/ (2πRC)
Take C= . Then R= . Use …. std.
Select Rf = 10 R =…. so that break frequency is ….. Hz. Select Rcom =
Procedure:
I. Inverting amplifier and Non inverting amplifier
1. Set up the inverting amplifier on the bread board.

2. Feed a sine wave and observe the input and output simultaneously on CRO.
Verify whether the output is …. sine wave in phase with input.

3. Set up the non inverting amplifier on the bread board.

4. Feed a sine wave and observe the input and output simultaneously on CRO.
Verify whether the output is ….. sine wave with 1800 out of phase with input.
II. Adder
1. Set up the adder circuit.
2. Feed the inputs and verify the output.
III. Integrator
1. Set up the integrator circuit.

2. Feed …., …. square wave at the input and observe the input and output
simultaneously on CRO.

3. Feed a sine wave to the input and note down the output amplitude by varying the
frequency of the sine wave. Enter it in tabular column and plot the frequency
response
IV. Comparator.
1. Set up the comparator circuit.
2. Feed the inputs and verify the output.

Results: Familiarized with basic operational amplifier integrated

circuits. Gain of inverting amplifier :………………….

Gain of non inverting amplifier: :………………….
 ELECTRONICS & COMMUNICATION
ENGINEERING
EXP 2 DATE
Measurement of Op-Amp parameters.

Aim: To measure the following parameters of an Op-amp i.e, input bias current, input offset
voltage, input offset current, CMRR and slew rate.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.
Theory:

Input bias current IB: It is defined as the average of the currents entering into the inverting and
non-inverting terminals of an op-amp. IB=( Ib1+Ib2)/2. Typical value of input bias current is 80nA.

Input offset current IOs: It is defined as the algebraic difference between the currents entering
into the inverting and non-inverting terminals of an op-amp. IO=|Ib1-Ib2|. Typical value of input
offset current is 20nA.

Input offset voltage: It is defined as the small voltage which is applied to overcome circuit
imbalances due to which the output voltage is not zero for zero input voltage, ie voltage applied
between the input terminals of an op-amp to nullify the output voltage. Typical value of input
offset voltage is 2mV.

CMRR: It is the ratio of differential mode gain to common mode gain and is expressed in dB.
CMRR=20 log (Ad/Ac) in dB.

Slew rate: It is the rate of rise of output voltage. It is a measure of fastness of op-amp. It is
expressed in v/μs.

Circuit diagrams

Circuit to measure input offset voltage Circuit to measure IB1

 ELECTRONICS & COMMUNICATION
ENGINEERING

Circuit to measure IB1

Circuit to measure slew rate

Circuit to measure CMRR.

Procedure
1. Set up the circuit to find the input offset voltage.
2. Measure the output voltage using the expression, ViO =VO Ri/(Rf + Ri); where VO is the
output voltage and ViO is the input offset voltage..
3. Set up the circuits for measuring input bias current and input bias voltage
 ELECTRONICS & COMMUNICATION
ENGINEERING
4. Measure the output voltage using the expressions VO= Ib1R and VO= Ib2R.
5. Calculate IB1 and IB2 and measure the bias and offset currents using the expression
IB=( Ib1+Ib2)/2and IOS=|Ib1-Ib2|. Where IB is bias current, IO is offset current.
6. Setup the circuit to calculate the slew rate. Give a square input of …. , … . Vary the
input frequency and observe the output. Note down the frequency at which the output
gets disturbed. Calculate the slew rate using the expression SR=(2πfVm )/106
 ELECTRONICS & COMMUNICATION
ENGINEERING
7. Set up the circuits for finding CMRR and apply a dc signal of …v to input and measure
VO. Calculate the CMRR using the expression CMRR=V i(Rf/Ri)/VO. Express the CMRR
in dB using the expression 20 log(CMRR).

Results:

Measured the Op-amp parameters and obtain the following

results Input offset voltage......= mV

Input bias current =..........A

Input offset current =..........A

Slew rate =..........V/μs.

CMRR = ……..
 ELECTRONICS & COMMUNICATION
ENGINEERING
EXP 3 DATE
Difference Amplifier And Instrumentation
Amplifier.
Aim: To design and setup a difference amplifier and instrumentation amplifier using opamp.
Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator
power supplies.
Theory: The difference amplifier circuit is very useful in detecting very small differences in the
signal. since the gain is RF/R1 can be selected to be very large. The output VO= -RF/R1(V2-V1).If
all the external resistors are of equal value, the gain of the amplifier becomes one. Thus the
output is V2-V1. Hence the name subtractor.
Instrumentation amplifiers are widely used in data acquisition systems, remote sensing
applications and instrumentation systems to measure temperature, humidity, light intensity and
weight etc. Most of the instrumentation systems use a transducer in a bridge circuit.
Instrumentation amplifier facilitates the amplification of potential difference take place due to
the imbalance of the bridge circuit proportional to a change in physical quantity. The main
feature of instrumentation amplifiers are high gain, high input resistance, high CMRR etc.

Circuit diagram and waveforms:

Difference amplifier
 ELECTRONICS & COMMUNICATION
ENGINEERING
Instrumentation amplifier

Design:
Difference amplifier:
Let R=…K
�1 �
 �0 = (1 + �⁄�) − �2
2 � ELECTRONICS & COMMUNICATION
= �1 − �2 ENGINEERING

Instrumentation amplifier
We have, V0=(V1-V2)[1+2R/RAmax]
Given, 1+2R/RAmax=….
Take R and RA max=…. Use … pot in series with ….

Procedure:
1.Verify the condition of op-amps.
2.Setup the circuit..
3. verify the output.

Result: Designed the difference and instrumentation amplifier.

EXP 4 DATE
Schmitt trigger circuit using op amps

Aim: To design and set up a schmitt trigger circuit using op-amps for various LTP and UTP.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory: Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here,
the input voltage triggers the output voltage every time it exceeds certain voltage levels called
the upper threshold voltage VUTP and lower threshold voltage VLTP. The input voltage is
applied to the inverting input. Because the feedback voltage is aiding the input voltage, the
feedback is positive. A comparator using positive feedback is usually called a Schmitt Trigger.
Schmitt Trigger is used as a squaring circuit, in digital circuitry, amplitude comparator, etc.

Circuit diagram
Schmitt trigger LTP=……V and UTP=…..V
 Schmitt trigger LTP = …..V and UTP =…….V

Waveform

Transfer Characteristics

Schmitt trigger LTP= …..V and UTP= …..V

Design:
Schmitt trigger LTP=…V and UTP=…V

Let the required LTP be ..V and UTP be…V

Normally, Vsat=..V when V+= ..V

LTP=….V= -13R2/(R1+R2)

UTP=…..V=13R2/(R1+R2)

Take R2=….K and

R1=….K

Schmitt trigger LTP=…..V and UTP=…..V

Let the required LTP be …..V and UTP be…..V

Normally, Vsat=…..V when V+=….V ,Use a reference voltage.

LTP=…..V=( -13R2/(R1+R2))+(Vref R1/(R1+R2))

UTP=…..V=( 13R2/(R1+R2))+(Vref R1/(R1+R2))

Take R2=…..K and R1=…..K we get reference voltage Vref =…. V

Schmitt trigger LTP= …..V and UTP= ….V

Let the required LTP be ….V and UTP be….V

Normally, Vsat=…..V when V+=….V ,Use a reference voltage.

LTP= ….V=( -13R2/(R1+R2))+(V

ref R1/(R1+R2))

UTP= ….V=( 13R2/(R1+R2))+(Vref R1/(R1+R2))

Take R2=…K and R1=….K we get reference voltage Vref = ….V

Procedure:
1. Verify whether the op-amp was in good condition.
2. Set up the circuit for Schmitt trigger and switch on the supplies and observe the input
and output on the CRO screen.
3. Observe the transfer characteristics.

Result : Designed the Schmitt trigger and obtained the output

EXP 5 DATE
Astable and Monostable multivibrator using Op –Amps

Aim: To design set up a astable and monostable multivibrators using op-amps for a frequency of
1kHz.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory:
Astable multivibrator: Astable multivibrators are capable of producing square wave for given
frequency, amplitude and duty cycle. The output of an op-amp is forced to swing repetitively
between positive saturation +Vsat and negative saturation –Vsat resulting in asquare wave
output. This circuit is also called free running multivibrator or square wave generator. The output
of the op-amp will be in positive saturation if differential input voltage is negative and vice
versa. The differential voltage Vd = Vc -βVsat where β is the feedback factor. βVsat is the
potential at non-inverting terminal of op-amp. Consider the instant at which Vo=+Vsat. Now the
capacitor charges exponentially towards +Vsat through R. Automatically Vd increases and
crosses zero. This happens when Vc changes to –Vsat. Now capacitor starts to discharge to zero
and recharge towards –Vsat. Now Vd decreases and crosses zero. This happens when Vc=-
βVsat. The moment Vd becomes negative again, output changes to +Vsat. This completes one
cycle. The time period T of the square wave is T= 2RCln(1+β)/(1-β).If β is made ½, T= 2.2RC.
Astable multivibrator is particularly useful for the generation of frequency in the audio frequency
range. Higher frequencies are limited by the delay time and slew rate of the op-amp.

Monostable multivibrator: A Monostable Multivibrator, often called a one-shot Multivibrator.

It ha a stable state and and a quasi stable state. The circuit remains in stable state until triggering
signal causes a transition to quasi stable state. After a time interval, it returns to the stable state.
So a single pulse of predetermined duration can be generated using this circuit. Consider the
instant at which the output Vo=+Vsat. Now the diode D1 clamps the capacitor voltage Vc at
0.7V. feedback voltage available at non inverting terminal is +βVsat. When the negative going
trigger is applied such that potential at non inverting terminal becomes less than
0.7 V , the output switches to –Vsat. Now the capacitor charges through R towards –Vsat,
because the diode becomes reverse biased. When the capacitor voltage become more negative
than –Vsat, the comparator switches back to +Vsat, and the capacitor C starts charging to +Vsat
through R until Vc reaches 0.7.
Circuit diagrams and waveforms :

Astable multivibrator

DESIGN

Required period of oscillation T=….ms with duty cycle

……% Time period T =T1+T2 = 2RC ln(1+β)/(1-β)

Where β, the feedback factor=R2/(R1+R2)

Take β=….. and R2=….K. Then

R1=…..K. When β=….., T=….RC

Let C be …µF. Then R= …..K.

Monostable multivibrator

DESIGN

Required period of oscillation T=…..ms with duty cycle

…..% Time period T = RC ln[1/(1-β)]T=…..RC

Where β, the feedback factor=R2/(R1+R2)

Take β=….. and R2=…..K. Then

R1=…..K. Let C be …..µF. Then R=…..K

Use …..K

Design of differentiating circuit: RdCd<0.016Tt.

Take trigger time period Tt=….ms and Cd=…..µF Then Rd=….K

Procedure:
1. Verify the conditions of op-amp.

2. Set up the circuit astable multivibrator and observe the output waveform. Note down
their frequencies and amplitudes.

3. Set up the circuit monostable multivibrator and feed …..Vpp,….Hz square wave at the
trigger input and observe the output waveform. Note down their frequencies and amplitudes.

Results: Designed the astable and monostable multivibrator using opamp.

EXP 6 DATE
Timer IC NE555

Aim: To study NE555 Timer and to design and setup an astable multivibrator and monostable
multivibrator using NE555 timer for a frequency of 1KHz.

Components required: NE555 timer, resistors, capacitors, breadboard, CRO, function generator
and power supplies.

Theory: The 555 timer is a highly stable device for generating accurate time delay or oscillation.
Signetics Corporation introduced this device as SE555/NE555 in 1971. The 555 timer is
available with the supply voltage between +4.5 to +18v, supply current 3 to 6 mA. It is
compatible with both TTL and CMOS logic circuits. The functional block diagram of 555
consist of two comparators, a flip-flop, an output stage, two BJT Q 1 and Q2 and a voltage divider
network. The comparators are devices whose outputs are HIGH when the positive(+) input
voltage is greater than the negative (-) input voltage and LOW when the negative (-) input
voltage is greater than positive (+) input voltage. The voltage divider consisting of three 5KΩ
resistors provide a trigger level of 1/3V CC and a threshold levels of 2/3VCC. The control voltage
input can be used externally adjust the trigger and threshold levels to other values, if necessary.

When the normally HIGH trigger input momentarily goes below 1/3V CC, the output of
comparator 2 switches from LOW to HIGH and set the S-R flip flop, causing the output to go
HIGH and turning the discharge transistors Q1 OFF. The output will remain HIGH until the
normally LOW threshold input goes above 2/3V CC and causes the output of comparator 1 to
switch from LOW to HIGH. This resets the flip flop, causing the output to go back LOW and
turning the discharge transistor ON. The external reset input can be used to reset the flip flop
independent of threshold circuit. The trigger and threshold inputs are controlled by external
components connected to produce either monostable or astable action.

So the output of timer becomes HIGH when the trigger input voltage is less than 1/3V CC
and the output becomes LOW when the threshold voltage is greater than 2/3V CC. Also in stable
state, the output of timer is LOW.

Astable multivibrator: When the power supply VCC is connected, the external timing capacitor
‘C” charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high (≈VCC)
as Reset R=0, Set S=1 and this combination makes Q =0 which has unclamped the timing
capacitor ‘C’.

When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the control flip
flop on that Q =1. It makes Q1 ON and capacitor ‘C’ starts discharging towards ground through
RB and transistor Q1 with a time constant RBC. Current also flows into Q1 through RA.
Resistors RA and RB must be large enough to limit this current and prevent damage to the
discharge transistor Q1. The minimum value of RA is approximately equal to VCC/0.2.
 During the discharge of the timing capacitor C, as it reaches V CC/3, the lower comparator
is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0 unclamps the external
timing capacitor C. The capacitor C is thus periodically charged and discharged between 2/3
VCC and 1/3 VCC respectively. The length of time that the output remains HIGH is the time for
the capacitor to charge from 1/3 VCC to 2/3 VCC.

The charging period of capacitor = 0.69 (RA + RB) C.

The discharging period of capacitor = 0.69 RB C.

Monostable multivibrator: A Monostable Multivibrator, often called a one-shot

Multivibrator, is a pulse-generating circuit in which the duration of the pulse is determined by the
RC network connected externally to the 555 timer. In a stable or stand by mode Q is high and in
turn, Q1 is turned ON and output is low. When the negative going trigger passes through VCC/3,
the FF is set i.e. Q =0. This makes transistor Q1 off. The capacitor starts charging towards V CC,
which was earlier clamped to zero. After a time period, the capacitor voltage becomes greater
than 2/3 VCC and upper comparator resets the FF, i.e. R=1, S=0. This makes Q =1. In turn
the transistor Q1 turns ON and thereby discharging the capacitor C rapidly to ground potential.
Mononostable circuit has only one stable state (output low), hence the name monostable.
Normally the output of the Monostable Multivibrator is low.

Circuit diagram:

Pin out of 555 timer IC Functional block diagram of 555 timer

Astable multivibrator using 555 timer

Monostable multivibrator using 555 timer

Design:

1.Astable multivibrator

Take VCC=…..V and tc=….ms and

td=….ms We have, tc=0.69(RA+RB)C and

td=….RB

The RA and RB should be in the range of 1K to 10K to limit the collector current of the internal
transistor. Take RA=RB=….KΩ.

Let C=…..µF. Choose C1=….µF.

2.Monostable multivibrator

Take VCC=……V and T=…ms.

We have, T=…..RC

Take R=…..K to limit current through the internal transistor to

….Ma. Then C=…..µF.

Design of triggering circuit we have RiCi ≤ 0.0016Tt where Tt is the time period of the trigger.

Take Tt=…..ms. Take Ri=…..KΩ to avoid loading. Then Ci=…..µF. Choose C1=…..µF.

Procedure:
1.Set up the astable multivibrator circuit after verifying the condition of the IC

2.Observe the output waveform at pin no.3 and 6 of the IC.

3. Set up the monostable multivibrator circuit.

4. Use positive pulses of amplitude Vcc and frequency ….. Hz as the trigger.

5. Observe the output waveform at pin no.3 and 6 of the IC

Result: Familiarized the NE555 Timer and designed an astable multivibrator and
monostable multivibrator using NE555 timer for a frequency of 1KHz
EXP 7 DATE
Triangular, square wave and sawtooth generators using Op- Amps

Aim: To set up and study a saw-tooth and triangular wave form generator using Op-Amp for
1KHz frequency.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory:

Triangular wave generator:

This circuit uses two op-amps. One functions as a comparator and other as an integrator.
Comparator compares the voltage at point P continuously with respect to the point voltage at the
inverting input which is at zero volt. When voltage at P goes slightly above zero, the output of A
will switches to negative saturation. Suppose the output of A is at positive saturation +Vsat,
since this voltage is at the input of integrator, the output of A2 will be a negative going ramp.
Thus one end of voltage divider R1 and R2 is at +Vsat and other end is at negative going ramp.
At the time t=t1, when the negative going ramp attains the value of -Vramp, the effective voltage
at P becomes slightly less than zero volt. This switches output of A1from +Vsat to –Vsat level.
The output of A2 increases in the positive direction. At the instant t=t2 , voltage at P becomes
just above zero volt thereby switching the output of A from –Vsat to + Vsat . The cycle repeats
and generates a triangular waveform. Frequency of triangular waveform f = (R1/4R2R3C) .Peak
to peak amplitude of ramp voltage is 2(R2/R1) Vsat.

Saw tooth waveform generator:

In sawtooth waveform generator the rise time is much higher than its fall time or vice -
versa. The triangular waveform generator can be converted into a Sawtooth waveform generator
by including a variable dc voltage into non inverting terminal of the integrator.This can be done
by using a port. When the wiper of the port is at the centre ,the output will be a triangular wave
since the duty cycle is 50%.If the wiper moves towards negative ,the rise time of Sawtooth
becomes larger than fall time. If the wiper moves towards positive ,the fall time becomes
larger than rise time. The Sawtooth waveform generators have wide applications in time base
generators and pulse width modulation circuits.
Circuit diagram and waveforms:

Triangular wave generator

Design:

Triangular wave generator:

Frequency,f =R1/(4*R2*R3*C)

Peak-peak output of ramp Vpp = 2R2/R1

Let the required Vpp = …..V and Vsat =

….. V Assume R1 = …..KΩ then R2 =

…..Ω Take C = …. µF, so R3 = …... KΩ

Sawtooth wave generator

Design:

Sawtooth wave generator

Frequency,f =R1/(4*R2*R3*C)

Peak-peak output of ramp Vpp = 2R2/R1

Let the required Vpp = ...V and Vsat = … V

Assume R1 = …KΩ then R2 = …. Ω Use …. Ω standard

Take C = …. µF, so R3 = …. KΩ Use …..KΩ pot

Select R4 = ….. KΩ

Procedure:

1. Set up the waveform generator circuit.

2. Obtain the output and note down the amplitude and frequency.

3. Set up the circuit of saw tooth wave generator.

4. Observe the output of both op-amps and note down the rise time and fall time.

5. Obtain the output by moving the wiper of port in both directions and observe the
changes taking place in waveforms.

Results: Designed and studied the saw tooth and triangular wave generator.
EXP 8 DATE
WIENBRIDGE OSCILLATOR USING OP-AMP WITH AND WITHOUT
AMPLITUDE STAILIZATION
Aim
: 1. To design set up a wien bridge oscillator incorporating amplitude stabilization.

2. Design and set up a Wien bridge oscillator using an op-amp for a frequency of 1kHz.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies

Theory: An FET circuit in association with the wien bridge oscillator, helps the stabilization of
the amplitude of oscillation. The N-channel JFET acts as a voltage controlled resistor and the
diode circuit function as a negative peak detector. The dc voltage at the gate of FET becomes
more negative when amplitude of oscillation increases. Then gate of FET gets reverse biased and
effective resistance from drain to source increases. This causes to decrease the gain according to
the relation A=1+( Rf /Ri ) and amplitude is brought back to a stable level. When output peak
starts to decrease, opposite patter occurs. This is an audio frequency oscillator of high stability
and simplicity.The feedback signal in the circuit is connected to the non-inverting input terminal
so that the op-amp is working as a non-inverting amplifier. Therefore, a feedback network need
not provide any phase shift.The circuit can be viewed as a Wien bridge with a series RC network
in one arm parallel RC network in the adjoining arm.Resisrors Ri and Rf are connected in the
remaining two arms.The conditionof zero phase shift around the circuit is achieved by balancing
the bridge.The frequency of oscillation is the resonant frequency of the balanced bridge and is
given by the expression fo=1/(2πRC).From the analysis of the circuit,it can be seen that the
feedback factor β=1/3 at the frequency of oscillation. Therefore, for the sustained oscillation,the
amplifier must have a gain of 3.

Circuit diagram:

With amplitude stabilization Without amplitude stabilization

Design:

Without amplitude stabilization

Required frequency,fo= …

kHz. Given fo=1/(2πRC)

Let C=…..μF. R1=R2=R=….kΩ

Use …..kΩ std.

Gain 1+Rf/Ri=3, Then Ri=…k.

Then R3= Rf=….k,use …k potentiometer.

Select R4= ….K, andC1 and C2=….µF.

With amplitude stabilization

Required frequency, fo= ….

kHz. Given fo=1/(2πRC)

Let C=….μF. R1=R2=R=….k Use …..k std.

Gain 1+Rf/Ri=3, Then Ri=….k.

Then R3= Rf=…..k,use ….k

potentiometer. Select Rs= ….M,

andCS=….µF

Procedure:

1. Verify the conditions of op-amp and JFET.

2. Set up the circuit and observe the output waveform. Note down the frequency and
amplitude of oscillation.

Result:

Designed the wienbridge oscillator using op-amp with and without amplitude stabilization
EXP 9 DATE
RC PHASE SHIFT OSCILLATOR
Aim: To design and set up an RC phase shift oscillator using op-amp for a frequency of

1 kHz.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies

Theory: RC phase shift oscillator consists of an op-amp as the amplifying stage and three RC
cascaded networks as the feedback network. The feedback network provides a fraction of the
output voltage back to the input of the amplifier.The op-amp is functioning in the inverting
mode.Therefore any signal which appears at the inverting terminal is shifted by 180⁰ at the
output.An additional 180⁰ phase shift required for oscillationas per Barkhausen criteria,is
provided by the cascaded RC network.Thus the total phase shift around the loop becomes 0⁰.

The frequency of oscillation is given by,fo=1/(2π√6RC).The gain of the

inverting op-amp should be atleast 29 at this frequency because the attenuation provided by the
feedback network is 1/29.The gain is kept slightly greater than 29 to ensure that the variations in
circuit parameters will not make the loop gain less than unity,and thus oscillations died out.For
lower frequencies(<1 MHz),op-amp 741 may be used,however for higher frequencies,LM318 or
LF351 should be used.

Circuit diagram:
Design:

Let the required frequency fo be,1/(2π√RC)=…..kHz.

Take C=….Μf.Then R=….Ω. Use ……Ω.

Gain Rf/R1=…..Take R1=….k and Rf=…..k pot.

Procedure:

1.Verify whether the op-amp is in good condition and set up the circuit as shown in the circuit
diagram.

2.Note down the amplitude and frequency of output waveform.

Result:
Designed the RC phase shift oscillator using op-amp.
EXP 10 DATE
Precision rectifiers using Op-Amp.

Aim: To design and setup a precision rectifier using op amp

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory: The precision rectifier, also known as a super diode, is a configuration obtained with an
operational amplifier in order to have a circuit behave like an ideal diode and rectifier. It is
useful for high-precision signal processing.
In a precision half wave rectifier a diode is placed in the negative feedback path of the op amp.
If Vin becomes positive, the output of the op amp will become positive. Hence the diode
conducts and a closed feedback path is established between the op amp’s output terminal and the
negative input terminal. This negative feedback path will cause a virtual short circuit to appear
between two input terminal. Thus V0=Vin. For the circuit to start working Vin has to exceed the
voltage equal to diode drop/op amp open loop gain. Since the op amp open loop voltage is very
high,starting voltage is negligiably small. Hence the circuit behaves like an ideal diode.
If Vin becomes negative, the output Vo of the op amp will be negative. This will reverse bias the
diode and no current will flow through the load resistance RL, causing the output VO to remain at
0V. Since the diode is off, the op amp will be operating as open loop circuit and its output will b
at -Vsat.
In a practical half wave precision rectifier an inverting amplifier is converted to a rectifier by
adding two diodes. The resistors are designed such that gain of the amplifier is one. Duing the
positive half cycle of the input, the output becomes negative. At this moment D 2 becomes
forward biased and D1 becomes reverse biased. Hence V01 is zero and V02 is negative. During
the negative half cycle, the output of the inverting amplifier becomes positive and D1 becomes
forward biased and D2 becomes reverse biased. Hence the V01 is positive and V02 is zero.
A full wave precision rectifier consists of a half wave rectifier and an inverting adder. We can
vary the output gain by changing the values of resistors as required . Input signal is directly
given to the adder at X. T he output V 02 which gives the negative ripples only of the half wave
rectifier is also given to the adder at Y. The mathematical addition of these two signals will gives
the output of a full wave rectifier. The resistance value of the adder is adjusted such that the
output is –(2Y+X).
Circuit diagram and expected waveforms:

Half wave precision rectifier Practical half wave precision rectifier

Full wave precision rectifier

Design:

For unity gain select R=…..K

Procedure:
1. Set up the circuit.
2. Apply a sine wave of milli-volt range and frequency less than …..KHz.
3. Observe the output in the CRO.
4. Repeat the procedure for the full wave circuit.

Results: Designed the circuit for precision rectifier and obtained the result.
EXP 11 DATE
Active second order filters using Op-Amp (LPF, HPF, BPF and BSF).

Aim: To design and set up the active second order filters using op amp.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory : A stop band having a 40 db/decade roll off is obtained with the second order filters.
They are important because higher order filters can be realized using them. The gain of the
second order filters can be fixed by R1 & RF, while the cutoff frequency can be obtained from R2,
R3, C2, and C3 as f=1/(2π√(R2 R3 C2C3)) and voltage gain AV= 20 log(V0/Vin).
For a second order low pass filter, the voltage gain magnitude is│V 0/Vi│=AF/√(1+(f/fH)4)
For a second order high pass filter, the voltage gain magnitude is│V0/Vi│=AF/√(1+(fL/f)4)
For a second order band pass filter, the voltage gain magnitude is
│V0/Vi│=AF (f/fL)/√{[1+(f/fL)2][1+(f/fH)2]}
A band pass filter of -40 dB/decade fall off rate can be formed by cascading a second order HPF
and LPF.
A band reject filter is obtained by cascading a LPF, HPF and a summer circuit.

Circuit diagram:

Low pass filter High pass filter

 Band pass filter Band reject filter

Design:

Low pass filter design

Required cutoff frequency fH = …

KHz We have fH = 1/2π√(R1R2C2C3)

Let C2=C3= ……µF. Then R2=R3=…..K

For R2=R3and C2=C3,

The pass band gain AF=(1+RF/R1) must be …..

That is RF= ……R1

Let R1=……K. Then RF=…..K.(use ….k)

Tabular Column Vin = …. volt

f(Hz) V0(V) Log(f) Av in dB

Graph

High pass filter design

Given cutoff frequency fL=

….KHz We have,

fL=1/2π√(R2R3C2C3)

Take C2=C3=C and R2=R3=R

Then fL=1/2ΠRC

Assume C=….µF. Then R=…..K.Use ….k std.

The pass band gain AF=(1+RF/R1) must be ……. for butterworth filter.

ie R=…..R1

Take R1=…..K .Then RF=….. K . Use ….K pot

Tabular Column Vin = ……volt

f(Hz) V0(V) Log(f) Av in dB

Graph

Band pass filter

Tabular Column Vin = …..volt

f(Hz) V0(V) Log(f) Av in dB

Graph
 Band reject filter

Tabular Column Vin = …..volt

f(Hz) V0(V) Log(f) Av in dB

Graph
Procedure:
1. Set up the circuits and feed a ….Vpp sine wave from the signal generator.
2. Vary the frequency in steps and note the output voltage.
3. Plot the frequency response.
4. Mark the lower cut-off frequency and calculate the roll-off in dB/decade

Results:
Designed the second order filters using op amp and obtained the results as
Cutoff frequency of low pass filter =....................KHz
Roll off of low pass filter =……………..
Cutoff frequency of high pass filter =.....................KHz
Roll off of high pass filter =…………….
Cutoff frequency of band pass filter =.....................KHz
Roll off of band pass filter =……………..
Cutoff frequency of band reject filter =.....................KHz
Roll off of band reject filter =……………..
EXP 12 DATE
Notch filters to eliminate the 50Hz power line frequency

Aim: Design and setup a notch filters to eliminate the 50Hz power line frequency.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory: Band elimination filter is also known as band rejection filter or band stop filter.
Wideband rejection can be setup by connecting a low pass filter and a high pass filter in parallel.
If an LPF with fL is connected in parallel with HPF with fH such that fH>fL, it forms BEF with
bandwidth fH-fL.

Narrow band rejection filter is also known as notch filter. It provides maximum attenuation at f0.
This is achieved by a twin-T RC network. Passive twin T network has relatively low figure of
merit Q. Q can be increased by associating with a voltage follower using op amp. Notch filter
has wide applications in communication field. It is used to eliminate undesired frequencies. The
very common application is to remove power supply that access at 50 Hz.

Circuit diagram:

Design:

Required notch frequency fN =1/2ΠRC =….KHz

Take C=…..µF. Then R=…..K

Take 2C=……1µF and R/2=…..K

Tabular Column Vin = …… volt

f(Hz) V0(V) Log(f) Av in dB

Graph

Procedure:
1. Set the signal generator output as …..V sine wave
2. Vary the frequency of sine wave and note down the output voltage.
3. Plot the frequency response on graph sheet.
Result:
Designed a notch filters to eliminate the 50Hz power line frequency.
EXP 13 DATE
IC voltage regulators.

Aim: To design and set up a low voltage and a high voltage regulator using IC RC723.

Components required: Op-amp, resistors, capacitors, breadboard, CRO, function generator and
power supplies.

Theory: 723 is a general purpose regulator that can be adjusted over a wide range of both
positive and negative regulated voltage. It has two sectios 1- a zener diode, a constant current
source and a reference amplifier that produces a fixed voltage of 7.15 at the terminal V ref.. The
constant current source forces the zener to operate at a fixed point so that the zener outputs a
fixed voltage. 2- it consist of an error amplifier, a series pass transistor Q 1 and a current limiting
transistor Q2 .T he error amplifier compares a sample of the output voltage applied at the INV
input terminal. The error signal controls the conduction of Q 1. These two sections are not
internally connected but various points are brought out on the IC package.723 regulator IC are
available in a 14 pin dual in line package or 10 pin metal can. It is inherently a low current
device, but it can be boosted to provide 5A or more current by connecting external components.
But it has no built in thermal protection .It also has no short circuit current limits. It can operate
with an input voltage from 9.5V to 40V and provide output voltage from 2V to 37V.
Low voltage regulator: A positive low voltage regulator using 723 is as shown. The
voltage at NI terminal of the error amplifier due to R 1R2 divider is VIN= Vref(R2/R1+R). T he
difference between VIN and the output voltage V0 is directly fed back to the INV terminal is
amplified by the error amplifier. The output of the error amplifier drives the pass transistor Q 1 so
as to minimize the difference the NI and INV input of error amplifier. Since Q 1 is operating as an
emitter follower V0=Vref(R2/R1+R2). If the output voltage becomes low, the voltage at the INV
terminal of the error amplifier also goes down. This makes the output of the error amplifier to
become more positive, thereby driving transistor Q1 more into conduction .This reduces the
voltage across Q1 and drive more current into the load causing the voltage across the load to
increase. So the initial drop in the load voltage has been compensated. Similarly any increase in
load voltage, or changes in the input voltage get regulated. The reference voltage typically
7.15volt, so the output voltage V0=7.15(R2/R1+R2). This will be always being less than 7.15V.

High voltage regulator :

If it is desired to produce regulated output voltage greater than 7V, a small change should
be made in the circuit for low voltage regulator. The non-inverting terminal is connected directly
to Vref through R3. So the voltage at the non-inverting terminal is V ref. The error amplifier
operates as a non-inverting amplifier with a voltage gain of Av=1+R1/R2. Notice that Av is
always greater than 1. So the output voltage of the circuit is Vo=7.15(1+ R1/R2).
Circuit diagram

Functional block diagram of 723 regulator

Pin diagram of IC 723

 Low voltage regulator

High voltage regulator

Design

 Low voltage regulator

V0 =
R2/(R1+R2) = …..V Vref = ….. V

R1=( Vref – V0)/ID = (7.15-6)/1mA =…..kΩ V0=…V

R2=V0/ID =6V/1mA = ….kΩ ≈….kΩ ID = ..mA
Take C = …..pF R3 = ……. kΩ

 High voltage Regulator

V0 = 7.15( 1 +( R1/ R2))

Take R1 = ….kΩ

1+(R1/R2)= 12/7.15 R2 =…. kΩ

Use R2= ….kΩ std

C= …..pF Take RL= …..Ω rheostat

Low voltage regulator

Observations:

For line regulation

Vs(V) Vo(V)
10
11
12
13
14
15

For load regulation

IL(mA) Vo(V)
0
5
10
20
40
70
80
100
 Typical graph

Line regulation Load Regulation

Low voltage regulator

Observations:

For line regulation

Vs(V) Vo(V)
18
20
22
24
28
30

For load regulation

IL(mA) Vo(V)
0
5
10
20
40
70
80
100
Typical graph

Line regulation Load Regulation

Procedure:
Low voltage regulator:

1. Set up the circuit. Switch on the power supply and input voltage sources.
2. Vary the input voltage from ….V to ….V and observe the output voltage. Note down it
in tabular column.
3. Vary the rheostat and note the change in output current.
4. Draw the regulation characteristics with input on X-axis and output on Y-axis.
5. Calculate the % line regulation using the expression:
SV = change in output voltage / change in input voltage

6. Calculate the % load regulation using the

expression: SL = (VNL – VF )/ VNL

High voltage regulator:

1. Set up the circuit. Switch on the power supply and input voltage sources.
2. Vary the input voltage from ….V to …..V and observe the output voltage. Note down
it in tabular column.
3. Vary the rheostat and note the change in output current.
4. Draw the regulation characteristics with input on X-axis and output on Y-axis.

Result:

Designed the voltage regulator circuits using IC 723 Load

regulation for
Low voltage regulator =……………
High voltage regulator=……………
EXP 14 DATE
A/D converters- counter ramp and flash type.

Aim: To design and setup a counter ramp and flash type ADC.

Components required: Op-amp, diode, resistors, capacitors, comparator LM311,IC’s

7408,7493,741, breadboard, CRO, function generator and power supplies.
Theory:
Counter ramp ADC: It displays the digital equivalent of input analog signal. Basically, a
comparator opens a gate for a period of time and a counter counts the number of pulses flowing
through the gate. Comparator keeps the gate open until the analog equivalent of the digital output
of the counter equals the input voltage that to be digitized.
A four bit binary counter 7493 is used to count the pulses. An op amp with R-2R ladder
network is used as a digital to analog converter. Comparator output provides high output as long
as Vin > Va. Vin is the input to be digitized and V a. analog equivalent of the instantaneous digital
output. When Vin < Va , gate closes and pulses stop to flow to binary counter. Digital output
remains standstill at its value.
2-bit flash ADC: If the analog signal exceeds the reference signal to any comparator, that
comparator turns on. If all comparators are off, analog input will be between 0 and +V/4.If C1 is
high and C2 and C3 are low, input will be between +V/4 and +V/2.If C1 andC2 are high and C3
is low input will be between +V/2 and +3V/4. If all comparators are high , analog input will be
between +3V/4 and +V. the outputs of three comparators are then fed to a coding network to
provide 2 bits which are equivalent to the input analog voltage.

Circuit diagram:

Counter ramp ADC

 2 bit FLASH ADC

Procedure:
1. Set up the circuit for counter ramp ADC and …..bit flash ADC

2. Vary the analog input from …..V to …….V and observe the output bits.

Result:

Designed and setup the ADC circuits

.
EXP 15 DATE
D/A Converters- ladder circuit.
Aim:
To design and set up a R-2R ladder type DAC.
Components required:
Op-amp, resistors, capacitors, breadboard, CRO, function generator and power supplies.
Theory: An R-2R ladder DAC uses fewer unique resistor values. Only two resistance values are
used anywhere in the entire circuit. This means that only two values of resistance in the ratio
2:1.Current flowing through any input resistor (2R) encounters two possible paths at the far end.
The effective resistances of both paths are the same, so the incoming current splits equally along
both paths. The half current that flows back towards lower orders of magnitude does not reach
the op amp, and therefore has no effect on the output voltage. The half that takes the path
towards the op amp along the ladder can affect the output.

Circuit diagram:

Design:

Let R=……KΩ & 2R=…..KΩ

Observations and typical response curve

Q3Q2Q1Q0 V0(Volts)
0000
0001
0010
……
……
1101
1110
1111

Procedure:

1. Verify the conditions of op-amp.

2. Set up the DAC circuit and manually enter binary inputs ….. to ….

3. Measure the output voltage using a multimeter and tabulate the readings.

4. Draw the response with analog output on Y-axis and binary output on X-axis.

Results:
Designed the ladder circuit DAC Error in
the output....................................%
EXP 16 DATE
Study of PLL IC: free running frequency lock range capture range

Aim: To design set up a PLL circuit and study its functional characteristics.

Components required:565 PLL IC, Power Supply, Function generator, CRO, Resistors,
Capacitors, Bread board

Theory: PLL is a control system that generates an output signal whose phase is related to the
phase of input reference signal. It mainly consists of a phase detector, an LPF and a VCO. Phase
comparator or phase detector compare the frequency of input signal fs with frequency of VCO
output fo and it generates a signal which is function of difference between the phase of input
signal and phase of feedback signal which is basically a d.c voltage mixed with high frequency
noise. LPF remove high frequency noise voltage. Output is error voltage. If control voltage of
VCO is 0, then frequency is center frequency (fo) and mode is free running mode. Application of
control voltage shifts the output frequency of VCO from f o to f. On application of error voltage,
difference between fs & f tends to decrease and VCO is said to be locked. While in locked
condition, the PLL tracks the changes of frequency of input signal.

Center frequency (free running frequency) fo= 1.2/4R1C1 Hz

Lock range fL = ± 8 fo/V Hz

V = (+V) – (-V)
 fL
Capture range f =±
c
 3
1/ 2
 2(3.6)x10 xC2

Circuit diagram

Block diagram of 565 PLL

Pin out of 565

Circuit diagram of PLL

Graph
Design:

Take V+=…..V and V-=…..V

Let the free running frequency f0 be 2.5KHz=1.2/4R1C1

Take C1=…..µF. Then R1=…..K.

The value of R1 satisfies the required condition 2k < R2

Take C3 =….µF C2=…µF Then the theoretical values of fL and fC

fL=±8*2.5*103/10-(-10) =….KHz

fc=√(103)/√(2π*3.6*103*10*10-6) = …… Hz

Procedure:

1. Verify the condition of components.

2. Set up the circuit and observe the output waveform and note down the VCO frequency.

3. Feed a square wave to the pin no.2 of 565 PLL IC and vary its frequency from …..Hz to ……
MHz and note down fC1 and fL2. Then decrease the frequency from …..MHz to …..Hz note down
fC2 and fL1

4. Calculate capture range and lock range.

Results: Designed the PLL IC and obtain the results.

Free running frequency:……………

Capture range :……………………..

Lock range :……………………….