Nanyang Technological University
School of Electrical and Electronic Engineering
EE2002 Analog Electronics
TUTORIAL 3
(With answers at the end)
l.a) The op-amp in Fig. T 3.1 has a unity-gain frequency of l.2MHz.
i) What is the closed loop BW?
ii) What is the closed-loop gain at 600kHz ?
95kΩ
5kΩ
-
V0
Vin
+
Fig. T3-1
1.b)The op-amp shown in Fig. T3-2 has a SR of 4 V/μS and a unity-gain frequency of
2MHz. Determine whether the amplifier will distort the input signal shown.
20 kΩ
20 kΩ
Vin
Vo
5V
-2V
5μs
Fig. T3-2
2. The op-amp in Fig T3-3 has a slew rate of 0.50V/μS. The amplifier must be
capable of amplifying the following input signals:
v1 = 0.01sin(106t)
v2 = 0.05sin(350x103t)
v3 = 0.10sin(200x103t)
v4 = 0.20sin(50x103t)
a) Determine whether the output will be distorted due to slew-rate limitations on
any input.
b) If so, find a remedy (other than changing the input signals).
1
330 kΩ
10 kΩ
Vi
-
Vo
+
Fig. T3-3
3.a) What minimum SR is necessary for a unity-gain amplifier that must pass, without
distortion, the input waveform shown in Fig T3-4.
volts
t (μs)
Fig. T3-4
3.b)Repeat (a), if the amplifier is in a noninverting configuration with Rl=50kΩ and
Rf=100kΩ.
4. In a certain application, a signal source having 60kΩ of source resistance produces
a 1-V-rms signal. The signal must be amplified to 2.5V rms and drive a 1kΩ load.
Assuming that the phase of the load voltage is of no concern, design an op-amp
circuit for the application.
2
Answers to Tutorial 3
1. (a)
(i) BWCL = 60 kHz
vo
(ii) (600kHz ) = 2.0 V V
v in
(b) No distortion will occur
2. (a) The output due to v2 and v3 will be distorted.
(b) There are only two remedies:
(i) find an amp with greater SR, a SR of at least 0.66 V/μs
(ii) reduce the ACL of the present amplifier to 25 V/V.
3. (a) The minimum SR is 3.0 V/μs
(b) The (SR)min = 9 V/μs
4. Many right answers.
