DEMP QB ANS

UNIT 2

2. Mul plexer Designs

A Mul plexer (MUX) is a combina onal circuit that selects one of many inputs and forwards the
selected input to a single output line based on control or select lines. The number of select lines
determines how many inputs the MUX can handle.

a) 2:1 Mul plexer:

 Theory: A 2:1 MUX has two input lines (I0, I1), one output (Y), and one select line (S). The
select line determines which input is passed to the output. If the select line (S) is 0, the first
input (I0) is selected. If the select line is 1, the second input (I1) is selected.

 Truth Table:

 Logic Diagram:

Boolean Equa on:

Y=S‾⋅I0+S⋅I1

b) 4:1 Mul plexer:

 Theory: A 4:1 MUX has four input lines (I0, I1, I2, I3), one output (Y), and two select lines (S1,
S0). The select lines choose one of the four inputs based on their binary combina on.

 Truth Table:
  Logic Diagram:

 Boolean Equa on:

Y=S1‾⋅S0‾⋅I0+S1‾⋅S0⋅I1+S1⋅S0‾⋅I2+S1⋅S0⋅I3

c) 8:1 Mul plexer:

 Theory: A 8:1 MUX has eight input lines (I0 to I7), one output (Y), and three select lines (S2,
S1, S0). The three select lines allow selec ng one of the eight inputs based on their binary
values

 Truth table

Logical circuit :
3. Demul plexer Designs

A Demul plexer (DEMUX) is the reverse of a mul plexer. It takes a single input and routes it to one
of several outputs based on select lines.

a) 1:2 Demul plexer:

 Theory: A 1:2 Demul plexer takes a single input and routes it to one of two outputs. It has
one select line (S). When S = 0, the input is routed to output O0, and when S = 1, the input is
routed to output O1.

 Truth Table:

 Logic Diagram:

b) 1:4 Demul plexer:

 Theory: A 1:4 Demul plexer takes a single input and routes it to one of four outputs. It has
two select lines (S1, S0). Each combina on of select lines directs the input to one of the four
outputs.
  Truth Table:

 Logic Diagram:

c) 1:8 Demul plexer:

A 1 to 8 demul plexer consists of one input line, 8 output lines and 3 select lines. Let the input be D,
S1 and S2 are two select lines and eight outputs from YO to Y7. It is also called as 3 to 8 demux
because of the 3 selec on lines.

Truth Table

Logical Circuit
4. Subtractors Designs

A Subtractor is a combina onal circuit that subtracts one binary number (minuend) from another
(subtrahend). It produces a difference and, in some cases, a borrow.

a) Half Subtractor:

 Theory: A Half Subtractor subtracts two single-bit binary numbers. It produces a difference
(D) and a borrow output (B_out). The borrow is produced when the minuend bit is smaller
than the subtrahend bit.

 Truth Table:

 Boolean Equa ons:

b) Full Subtractor:

 Theory: A Full Subtractor subtracts two bits along with a borrow input. It gives a difference
and a borrow output. It’s used for mul -bit binary subtrac on where a borrow input might
be present from the previous lower significant bit.
  Truth Table:

 Boolean Equa ons:

5. Adders Designs

a) Half Adder:

 Theory: A Half Adder adds two single-bit binary numbers. It produces a sum and a carry
output.

 Truth Table:

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

 Boolean Equa ons:

b) Full Adder:

 Theory: A Full Adder adds three bits: two operand bits and a carry-in from a lower-order bit.
It produces a sum and a carry-out for higher-order addi on.

 Truth Table:
  Boolean Equa ons:

UNIT 3

Difference between Latch and Flip-Flop (Table Form)

A Latch and a Flip-Flop are both bistable devices used to store a single bit of data. The key difference
lies in how they operate with respect to ming (clocking).

Feature Latch Flip-Flop

Control Level-sensi ve (operates as long as input Edge-sensi ve (operates only on clock

Signal is ac ve) edge)

Can change output any me when Changes state only at clock transi ons
Timing
control signal is ac ve (posi ve or nega ve edge)

Clocking No clock signal required Requires a clock signal to change state

Can con nuously change state as long as State change occurs only on the clock
Opera on
the enable is ac ve edge

SR flip-flop, JK flip-flop, D flip-flop, T flip-

Types SR latch, D latch
flop

Used for simple memory elements in Used for more reliable state changes in
Applica ons
combina onal circuits sequen al circuits

2. 1-Bit Memory Cell Using Gates and Clocked SR Flip-Flop

a) 1-Bit Memory Cell Using Gates:

A 1-bit memory cell can be constructed using logic gates, such as an SR latch. The SR latch can store a
single bit of data, where:

 Set (S) input sets the output to 1.

 Reset (R) input resets the output to 0.

 Basic SR Latch Using NOR Gates:

o The circuit consists of two NOR gates cross-coupled, with inputs for Set (S) and Reset
(R), and outputs Q and Q‾\overline{Q}Q.

o When S = 1, Q is set to 1, and when R = 1, Q is reset to 0.

Diagram:

b) Clocked SR Flip-Flop:

A Clocked SR Flip-Flop is similar to an SR latch, but with an added clock signal that enables the latch
to change its state only when the clock signal is ac ve.

 The output changes based on the S and R inputs, but only when the clock (CLK) is high.

 This prevents the flip-flop from changing its state at arbitrary mes, providing more
predictable behavior.

Truth Table for Clocked SR Flip-Flop:

3. JK, SR, T, D Flip-Flops

a) JK Flip-Flop:

 Theory: The JK flip-flop is a refinement of the SR flip-flop. It overcomes the invalid state
when both inputs are 1 by toggling the output.
  Logic Circuit: It uses a combina on of AND gates, OR gates, and a clock input to control the
toggling ac on.

 Working: When both inputs J and K are 1, the output toggles. Otherwise, the output is set or
reset based on the values of J and K.

Truth Table for JK Flip-Flop:

b) SR Flip-Flop:

 Theory: The SR flip-flop has two inputs: Set (S) and Reset (R). It stores a binary value, and its
output changes based on the input signals.

 Working: When the S input is high, the output is set to 1, and when R is high, the output is
reset to 0.

Truth Table for SR Flip-Flop:

c) T Flip-Flop:

 Theory: The T flip-flop is a modifica on of the JK flip-flop where both inputs are ed
together. It toggles its state on every clock cycle when the T input is 1.

 Working: If T = 1, the output toggles on every clock pulse. If T = 0, the output remains
unchanged.

Truth Table for T Flip-Flop:

d) D Flip-Flop:

 Theory: The D flip-flop has a single data input (D) and is designed to store the input on the
rising edge of the clock signal. It eliminates the race condi on present in the SR flip-flop.

 Working: The output Q follows the D input at the clock's edge.

Truth Table for D Flip-Flop:

4. Conver ng Flip-Flops

You can convert between different types of flip-flops using logic gates. For example:

 SR to JK Flip-Flop: To convert an SR flip-flop to a JK flip-flop, add feedback connec ons and

change the input logic so that the flip-flop toggles when both inputs (S and R) are high.

 JK to D Flip-Flop: A JK flip-flop can be converted to a D flip-flop by tying both the J and K

inputs together and using the D input as the shared signal.

5. Difference Between Asynchronous and Synchronous Counters

Feature Asynchronous Counter Synchronous Counter

Clocking All flip-flops do not receive the clock at the same All flip-flops are triggered by
me; flip-flops change states at different mes. the same clock signal.

Speed Slower due to propaga on delay through flip- Faster as all flip-flops change
flops. states simultaneously.

Design Simpler design, but slower opera on. More complex design, but
Complexity faster.
 Example Ripple Counter Parallel Counter

6. Ring Counters

 Theory: A Ring Counter is a type of counter where only one flip-flop is high at any given me.
The output of the last flip-flop is fed back to the input of the first flip-flop, crea ng a ring-like
structure.

 Working: The flip-flops in the ring shi their states in a circular fashion. A 4-bit ring counter
will cycle through 4 states.

Diagram:

7. Asynchronous UP/Down/UP-Down (Ripple) Counters

Asynchronous Up Counter (Ripple Counter)

Theory:
An Asynchronous Up Counter, also known as a Ripple Counter, is a type of counter where each flip-
flop is triggered by the previous flip-flop’s output rather than by a common clock signal. This results
in a delay, or ripple effect, as each flip-flop is triggered one a er the other. The counter "counts up"
as it progresses through binary states in increasing order.

Characteris cs:

 Each flip-flop toggles on the falling edge (or rising edge, depending on design) of the
previous flip-flop’s output.

 In a 3-bit asynchronous up counter, the output of the first flip-flop serves as the clock for the
second flip-flop, and so on.

 It is called asynchronous because the flip-flops do not all change states at exactly the same
me.

3-bit Asynchronous Up Counter:

To illustrate, let's consider a 3-bit asynchronous up counter, which can count from 0 (000 in binary) to
7 (111 in binary).

Logic Diagram:

 CLK is the main clock signal.

 Q0, Q1, and Q2 are the outputs of the flip-flops, represen ng the count in binary.

Opera on:

 The first flip-flop (FF1) toggles with each clock pulse.

 The second flip-flop (FF2) toggles when Q0 transi ons from high to low (i.e., on the falling
edge).

 The third flip-flop (FF3) toggles when Q1 transi ons from high to low.

Each flip-flop in this counter is in toggle mode, meaning that it changes its state on every falling edge
of the input.

Truth Table for a 3-Bit Asynchronous Up Counter:

Clock Pulse Q2 (MSB) Q1 Q0 (LSB)

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
 Clock Pulse column represents each clock cycle, where the counter increments by 1.

 Q2, Q1, and Q0 show the binary count values from 000 to 111.

This asynchronous counter resets a er reaching the binary count of 111 (or 7 in decimal) and starts
from 000 again.

Advantages and Disadvantages:

  Advantages: Simple design, minimal wiring.

 Disadvantages: Propaga on delay due to the ripple effect, making it less suitable for high-
frequency applica ons.

Asynchronous Down Counter (Ripple Down Counter)

Theory:
An Asynchronous Down Counter is a sequen al counter circuit where each flip-flop is triggered by
the previous flip-flop’s output. However, in a down counter, the flip-flops are designed to count
downwards, meaning they progress in descending binary order from a maximum value to zero. Like
other asynchronous counters, the output of each flip-flop serves as the clock signal for the next flip-
flop, crea ng a ripple effect.

Characteris cs:

 It "counts down" in binary sequence, such as from 111 (7 in decimal) down to 000 (0 in
decimal).

 Each flip-flop toggles on the falling edge of the output from the previous flip-flop.

 This type of counter has cumula ve propaga on delay because each flip-flop waits for the
previous one to change state.

3-bit Asynchronous Down Counter

In a 3-bit asynchronous down counter, the counter will decrement from 111 (7 in decimal) down to
000 (0 in decimal) on each clock pulse.

Logic Diagram:

 CLK: Main clock signal that triggers the first flip-flop.

 Q0, Q1, and Q2: Output from each flip-flop represen ng the count in binary.

Each flip-flop is configured in toggle mode, meaning that it changes its state on every falling edge of
the signal from the previous flip-flop.

Truth Table for a 3-Bit Asynchronous Down Counter

 Clock Pulse Q2 (MSB) Q1 Q0 (LSB)

0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
 The Clock Pulse column shows the pulse number, with each pulse decremen ng the counter
by 1.

 Q2, Q1, and Q0 show the binary count values, which decrement with each clock pulse from
111 down to 000.

Opera on of Each Flip-Flop:

1. Q0 toggles with every clock pulse.

2. Q1 toggles on the falling edge of Q0.

3. Q2 toggles on the falling edge of Q1.

When the counter reaches 000, the next clock pulse will reset it back to the maximum count of 111,
allowing the down count to start again.

Asynchronous Up-Down Counter (Ripple Up-Down Counter)

Theory: An Asynchronous Up-Down Counter is a sequen al circuit that can count both upwards and
downwards. This counter combines the func onality of an asynchronous up counter and a down
counter, with the direc on of coun ng controlled by an UP/DOWN control input. In asynchronous
counters, each flip-flop’s clock input is driven by the output of the previous flip-flop, crea ng a ripple
effect. Depending on the control signal, the counter either increments (counts up) or decrements
(counts down) its binary value.

Characteris cs:

 UP/DOWN Control Input: Determines the coun ng direc on:

o If UP/DOWN = 1, the counter counts up (increasing order).

o If UP/DOWN = 0, the counter counts down (decreasing order).

 Each flip-flop’s clock is triggered by the output of the previous flip-flop, resul ng in
asynchronous behavior.

 Suitable for applica ons where coun ng direc on needs to switch dynamically.

3-bit Asynchronous Up-Down Counter

For demonstra on, consider a 3-bit asynchronous up-down counter, which counts from 0 (000) to 7
(111) in up mode and from 7 (111) down to 0 (000) in down mode.
Logic Diagram: The logic diagram below shows the general structure of a 3-bit asynchronous up-
down counter with JK flip-flops and an UP/DOWN control input. Each flip-flop is connected to toggle
based on the direc on specified by the control signal.

In this circuit:

 UP/DOWN signal switches the counter between up and down modes.

 Q0, Q1, and Q2 are the flip-flop outputs, represen ng the counter value.

Each flip-flop is in toggle mode, meaning that it changes state based on the output of the previous
flip-flop and the mode set by the UP/DOWN input.

Truth Table for a 3-Bit Asynchronous Up-Down Counter

When UP/DOWN = 1 (Coun ng Up):

Clock Pulse Q2 (MSB) Q1 Q0 (LSB)

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
This mode counts in ascending order (000 to 111), similar to a regular asynchronous up counter.

When UP/DOWN = 0 (Coun ng Down):

Clock Pulse Q2 (MSB) Q1 Q0 (LSB)

0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
This mode counts in descending order (111 to 000), just like a standard asynchronous down counter.

Opera on of Each Flip-Flop:

 1. Q0 toggles on every clock pulse regardless of the coun ng mode.

2. Q1 toggles on the falling edge of Q0 in up mode or on the rising edge of Q0 in down mode,
depending on the UP/DOWN control.

3. Q2 toggles based on the combined state of Q1 and Q0 and the UP/DOWN input.

8. MOD-4/2-bit and MOD-8/3-bit Synchronous Up-Counter Using JK Flip-Flops

MOD-4 (2-bit) Synchronous Up-Counter Using JK Flip-Flops

Theory: A MOD-4 synchronous up-counter is a digital circuit that counts from 0 to 3 (in binary) and
then resets back to 0. "MOD-4" indicates that the counter has four unique states (00, 01, 10, 11)
before it wraps around. Since it’s a synchronous counter, all flip-flops are triggered by the same clock
signal simultaneously, which ensures no cumula ve delay (unlike asynchronous counters).

Design Requirements:

1. We will use 2 JK flip-flops (labeled as Q1 and Q0) to store the count since 2 bits can
represent four states.

2. Since we need a MOD-4 counter, the counter should reset a er reaching 3 (11 in binary).

3. The JK flip-flops will be connected such that they toggle based on the counter’s current state.

Working of JK Flip-Flops in the Counter:

 Q0 will toggle on each clock pulse, represen ng the least significant bit (LSB).

 Q1 will toggle whenever Q0 transi ons from 1 to 0 (which occurs every second clock pulse),
represen ng the most significant bit (MSB).

State Table for MOD-4 Counter

We can create a truth table to determine the input condi ons required for the JK flip-flops at each
state.

Present State (Q1 Q0) Next State (Q1' Q0') J1 K1 J0 K0

00 01 0 X 1 X
01 10 1 X X 1
10 11 X 1 1 X
11 00 X 1 X 1
 J0 and K0 control flip-flop Q0, which should toggle on every clock pulse, so J0 = K0 = 1.

 J1 and K1 control flip-flop Q1, which should toggle only when Q0 transi ons from 1 to 0.

Logic Equa ons for Flip-Flop Inputs

From the state table:

 J0 = 1, K0 = 1 (Q0 toggles with each clock pulse).

 J1 = Q0 and K1 = Q0 (Q1 toggles only when Q0 is high).

Logic Diagram for MOD-4 Synchronous Counter Using JK Flip-Flops

The logic diagram is shown below:

+----------+ +----------+

CLK ---> | JK | ----> | JK |

| FF (Q0) | | FF (Q1) |

| J0=1 K0=1| | J1=Q0 K1=Q0|

+----------+ +----------+

Truth Table

Clock Pulse Q1 (MSB) Q0 (LSB)

0 0 0
1 0 1
2 1 0
3 1 1
4 0 0
A er reaching the state 11 (decimal 3), the counter resets to 00, sa sfying the MOD-4 condi on.

Explana on of Opera on

1. Q0 toggles with each clock pulse due to its input J0 = 1 and K0 = 1.

2. Q1 toggles only when Q0 is high (i.e., every second clock pulse).

3. This produces a binary count sequence of 00, 01, 10, 11 on each clock pulse.

MOD-8 (3-bit) Synchronous Up-Counter Using JK Flip-Flops

Theory: A MOD-8 synchronous up-counter is a digital circuit that counts from 0 to 7 (in binary) and
then resets back to 0, making a total of 8 unique states (hence, MOD-8). In a synchronous counter, all
flip-flops are triggered simultaneously by the same clock pulse, which prevents cumula ve delay
across flip-flops as seen in asynchronous counters.

To achieve this:

1. We will use 3 JK flip-flops labeled as Q2, Q1, and Q0, where:

o Q0 is the least significant bit (LSB),

o Q2 is the most significant bit (MSB).

2. Each flip-flop toggles based on the current count and its respec ve toggle condi ons.

Opera on of JK Flip-Flops in the MOD-8 Counter

For a MOD-8 counter:

 Q0 toggles on every clock pulse.

  Q1 toggles when Q0 changes from 1 to 0, which occurs every two clock pulses.

 Q2 toggles when both Q0 and Q1 are 1, which happens every four clock pulses.

State Table and Input Requirements

The following table shows the current state and next state of the flip-flops for each clock pulse, as
well as the necessary inputs to the JK flip-flops to achieve the desired transi ons.

Present State (Q2 Q1 Q0) Next State (Q2' Q1' Q0') J2 K2 J1 K1 J0 K0

000 001 0 X 0 X 1 X
001 010 0 X 1 X X 1
010 011 0 X X 1 1 X
011 100 1 X 0 X X 1
100 101 X 1 0 X 1 X
101 110 X 1 1 X X 1
110 111 X 1 X 1 1 X
111 000 X 1 X 1 X 1
From the table:

 J0 = 1, K0 = 1: Q0 toggles with each clock pulse.

 J1 = Q0, K1 = Q0: Q1 toggles when Q0 is high.

 J2 = Q0 AND Q1, K2 = Q0 AND Q1: Q2 toggles only when both Q0 and Q1 are high.

Logic Equa ons for JK Flip-Flop Inputs

 J0 = 1, K0 = 1: Q0 toggles on each clock pulse.

 J1 = Q0, K1 = Q0: Q1 toggles when Q0 is high.

 J2 = Q0 * Q1, K2 = Q0 * Q1: Q2 toggles when both Q0 and Q1 are high.

Logic Diagram for MOD-8 Synchronous Counter Using JK Flip-Flops

Here’s the logic diagram structure:

+----------+ +----------+ +----------+

CLK ------>| JK | ------>| JK | ------>| JK |

| FF (Q0) | | FF (Q1) | | FF (Q2) |

| J0=1 K0=1| | J1=Q0 K1=Q0 | | J2=Q0*Q1 K2=Q0*Q1|

+----------+ +----------+ +----------+

Truth Table for MOD-8 Counter

Clock Pulse Q2 (MSB) Q1 Q0 (LSB)

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
 5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
The counter cycles back to 000 a er reaching 111, comple ng the MOD-8 count sequence.

Explana on of Opera on

1. Q0 toggles with every clock pulse, represen ng the LSB of the count.

2. Q1 toggles when Q0 is high, crea ng the next higher binary place.

3. Q2 toggles when both Q0 and Q1 are high, represen ng the MSB and comple ng the MOD-8
cycle.

9. Shi Registers

Shi Registers

A Shi Register is a sequen al logic circuit used to store and move (shi ) data. They use flip-flops
(o en D flip-flops) and can shi data either le or right. The four main types are:

1. Serial-In, Serial-Out (SISO): Data is input and output serially.

2. Serial-In, Parallel-Out (SIPO): Data enters serially and is output in parallel.

3. Parallel-In, Serial-Out (PISO): Data is loaded in parallel and shi ed out serially.

4. Parallel-In, Parallel-Out (PIPO): Data is input and output in parallel.

Example: 4-bit Serial-In, Serial-Out (SISO) Shi Register

In a 4-bit SISO Shi Register, four D flip-flops are connected in sequence. Data enters at the input of
the first flip-flop (Q0) and shi s right with each clock pulse un l it reaches the output of the last flip-
flop (Q3).

Logic Diagram:

Serial Input -----> D0 -> D1 -> D2 -> D3 -----> Serial Output

| | | |

Q0 Q1 Q2 Q3

Truth Table for Shi ing Data 1011

Clock Pulse Serial Input Q3 (Output) Q2 Q1 Q0

0 1 0 0 0 0
1 0 0 0 0 1
2 1 0 0 1 0
3 1 0 1 0 1
 4 0 1 1 1 0
Applica ons

 Data Storage

 Data Transfer (serial to parallel or vice versa)

 Counters and Delay Lines

Shi registers are fundamental in digital electronics for data handling and transfer.

10. Sequence Generator with Example

A Sequence Generator is a digital circuit that produces a specific, repea ng binary sequence with
each clock pulse. It uses flip-flops (such as D or JK) and logic gates to transi on between predefined
states, making it useful for counters, digital clocks, and pa ern genera on.

Example: 4-bit Sequence Generator for 0001 → 0011 → 0111 → 1111

This sequence generator outputs the sequence 0001, 0011, 0111, 1111 and then repeats. Each bit in
the sequence is represented by a flip-flop (Q3, Q2, Q1, Q0).

State Table:

Clock Pulse Q3 Q2 Q1 Q0 Next State

0 0 0 0 1 0001
1 0 0 1 1 0011
2 0 1 1 1 0111
3 1 1 1 1 1111
4 0 0 0 1 (Repeat)

Applica ons

 Pa ern Generators for tes ng

 Counters with specific sequences

 Control Circuits in automa on

Sequence generators are essen al in digital electronics for crea ng controlled, repea ng pa erns.
 UNIT 4

1. Internal Architecture of 8086 Microprocessor

The 8086 microprocessor is a 16-bit processor developed by Intel, which features a bipar te
architecture divided into two func onal units:

1. Bus Interface Unit (BIU):

o Responsible for handling all data, address, and control buses.

o It fetches instruc ons from memory and provides the addresses for instruc on
fetching and data transfer.

o It contains the Segment Registers, Instruc on Pointer, and Physical Address

Calcula on logic.

2. Execu on Unit (EU):

o Executes instruc ons fetched by the BIU.

o It contains General Purpose Registers, Flags Register, ALU, and control circuits for
decoding and execu ng instruc ons.

The internal registers of the 8086 include:

 Segment Registers: CS (Code Segment), DS (Data Segment), SS (Stack Segment), ES (Extra

Segment)

 General-purpose Registers: AX, BX, CX, DX (each 16-bit)

 Pointer and Index Registers: SP (Stack Pointer), BP (Base Pointer), SI (Source Index), DI
(Des na on Index)

 Instruc on Pointer (IP): Points to the next instruc on.

 Flags Register: Contains the status flags (Zero, Carry, Sign, etc.).

2. Flag Register of 8086

The Flag Register of the 8086 microprocessor is a 16-bit register used to store various status flags
that are set or cleared based on the result of opera ons.

Flag Register Format:

Flag Name Bit Posi on Descrip on

CF 0 Carry Flag
PF 2 Parity Flag
AF 4 Auxiliary Carry Flag
ZF 6 Zero Flag
SF 7 Sign Flag
TF 8 Trap Flag
IF 9 Interrupt Enable Flag
DF 10 Direc on Flag
 OF 11 Overflow Flag

3. Register Organiza on of 8086

The registers in the 8086 microprocessor can be categorized into the following groups:

1. General-Purpose Registers:

o AX, BX, CX, DX (16-bit): Used for arithme c, data manipula on, and indexing.

o These can be further divided into 8-bit registers: AH, AL, BH, BL, etc.

2. Pointer and Index Registers:

o SP (Stack Pointer): Points to the top of the stack.

o BP (Base Pointer): Used in stack opera ons.

o SI (Source Index): Used for string opera ons.

o DI (Des na on Index): Used for string opera ons.

3. Segment Registers:

o CS (Code Segment): Points to the code segment.

o DS (Data Segment): Points to the data segment.

o SS (Stack Segment): Points to the stack segment.

o ES (Extra Segment): Used for extra data or string opera ons.

4. Instruc on Pointer:

o IP: Points to the next instruc on to be executed in the code.

5. Flags Register: Contains status flags (e.g., carry, zero, sign).

4. Numerical on Physical Address Calcula on

In the 8086 microprocessor, the physical address is calculated using the segment address and offset
address.

Formula:
Physical Address=(Segment×16)+Offset\text{Physical Address} = ( \text{Segment} \ mes 16 ) +
\text{Offset}Physical Address=(Segment×16)+Offset

Example:

 Segment address = 0x2000

 Offset address = 0x1234

Calcula on:
Physical Address=(0x2000×16)+0x1234=0x32000+0x1234=0x33234\text{Physical Address} = (0x2000
\ mes 16) + 0x1234 = 0x32000 + 0x1234 =
0x33234Physical Address=(0x2000×16)+0x1234=0x32000+0x1234=0x33234

So, the physical address is 0x33234.

5. Addressing Modes of Instruc ons

1. ADC AL, [SI]

 Addressing Mode: Indirect Addressing

 Explana on: The operand [SI] refers to the memory loca on whose address is stored in the SI
(Source Index) register. The value at this memory loca on is added to AL.

2. MOV AL, BL

 Addressing Mode: Register Addressing

 Explana on: The contents of the BL register are moved to the AL register directly.

6. Procedure and Macro

Procedure

A Procedure in assembly language is a block of code that can be called from different parts of the
program. It is used to perform a specific task, and once the task is completed, control returns to the
calling instruc on. Procedures are a fundamental part of structured programming, helping to break
down a complex program into smaller, more manageable blocks of code.

 Key Points:

o A procedure can accept parameters (inputs) and may return a value (output).

o Local variables are defined within the procedure, which are not accessible outside of
it.

o Procedures help to avoid code repe on and improve modularity and

maintainability of the program.

o Procedures typically involve stack opera ons to store return addresses and
parameters.

 Example (In Assembly Language):

; Example of a simple procedure to add two numbers

ADD_NUMBERS PROC

MOV AX, [NUM1] ; Load the first number into AX

ADD AX, [NUM2] ; Add the second number to AX

RET ; Return from the procedure

ADD_NUMBERS ENDP
In this example:

o ADD_NUMBERS is the name of the procedure.

o It performs the addi on of two numbers and then returns control to the calling code
using the RET instruc on.

Macro

A Macro is similar to a procedure, but it works differently. It is essen ally a template of code that
gets expanded inline by the assembler during the assembly process. Macros do not have a separate
execu on stack or parameters (in the tradi onal sense), and they do not cause a jump in execu on,
unlike procedures.

 Key Points:

o Macros are expanded at the point of their invoca on, so they are not reusable in the
way procedures are. Every me a macro is called, the assembler replaces the macro
with the actual code.

o Macros can accept parameters, but unlike procedures, they do not involve
pushing/popping parameters to/from the stack.

o Since macros are expanded inline, they can make the code more efficient by
elimina ng the overhead of calling procedures, but they can also increase the code
size if used excessively.

 Example (In Assembly Language):

; Define a macro to add two numbers

ADD_MACRO MACRO NUM1, NUM2

MOV AX, NUM1 ; Move NUM1 into AX

ADD AX, NUM2 ; Add NUM2 to AX

ENDM

; Calling the macro

ADD_MACRO 5, 10 ; The assembler replaces this with MOV AX, 5 and ADD AX, 10

In this example:

o ADD_MACRO is a macro that adds two numbers, NUM1 and NUM2.

o When invoked, the macro is expanded by the assembler into the actual code (MOV
and ADD instruc ons), as if the code had been wri en directly.
7. Assembler Direc ve

An assembler direc ve is a command in assembly language that provides instruc ons to the
assembler but does not generate machine code.

1. DB: Define Byte

o Syntax: DB 10h

o Defines a byte in memory.

2. DW: Define Word

o Syntax: DW 1234h

o Defines a word (2 bytes).

3. EQU: Define Constant

o Syntax: MAX_SIZE EQU 100h

o Defines a constant value.

4. ORG: Set Origin

o Syntax: ORG 100h

o Specifies the star ng memory address.

8. Segmenta on Concept of 8086

The segmenta on concept in the 8086 microprocessor allows it to address more memory than a 16-
bit address bus would typically allow (16-bit addresses can only access 64KB). The 8086 uses
segmented memory to address up to 1MB of memory by combining a segment address and an offset
address. The 8086 uses a 16-bit segment register and a 16-bit offset to form a 20-bit physical
address.

Key Points:

1. Segment Registers: The 8086 has four segment registers:

o CS (Code Segment): Points to the segment where the program's code resides.

o DS (Data Segment): Points to the segment where data is stored.

o SS (Stack Segment): Points to the segment that holds the stack.

o ES (Extra Segment): Used for extra data storage, typically during string opera ons.

Each segment is 64KB in size, and the combina on of a segment base and offset provides a 20-bit
physical address, giving access to 1MB of memory.

2. Segment and Offset:

o The segment address is mul plied by 16 (or shi ed le by 4 bits), and the offset
address is added to it to form the physical address.

o Formula: Physical Address=(Segment×16)+Offset\text{Physical Address} =

(\text{Segment} \ mes 16) + \text{Offset}Physical Address=(Segment×16)+Offset
 o This allows the processor to access up to 1MB of memory, as the 20-bit physical
address (from combining segment and offset) can uniquely iden fy a loca on in 1MB
of memory.

Example:

If the CS = 0x2000 and the IP = 0x1234, the physical address is calculated as:

Physical Address=(0x2000×16)+0x1234=0x32000+0x1234=0x33234\text{Physical Address} = (0x2000

\ mes 16) + 0x1234 = 0x32000 + 0x1234 =
0x33234Physical Address=(0x2000×16)+0x1234=0x32000+0x1234=0x33234

So, the physical address becomes 0x33234.

3. Advantages of Segmenta on:

o Modular Programming: Allows different types of data (code, stack, and data) to
reside in separate areas of memory.

o Efficient Memory Use: Segmenta on allows for easier memory management, as

different segments can grow or shrink independently.

o Memory Protec on: Different segments can be protected by the opera ng system to
prevent data from being overwri en.

UNIT 5

1. Difference between Microprocessor and Microcontroller

Feature Microprocessor Microcontroller

Defini on A microprocessor is a CPU on a A microcontroller is a small computer on a
single chip that performs general- single chip, designed for specific tasks in
purpose processing tasks. embedded systems.
Components Only the processor (CPU) is Contains CPU, memory (RAM/ROM), I/O
present, and external memory and ports, and peripherals on the same chip.
peripherals are required.
Memory External memory (RAM/ROM) is Includes on-chip memory
required for opera on. (RAM/ROM/EEPROM).
I/O Ports I/O ports are not present, external I/O ports are integrated on the chip for
interfacing required. interfacing.
Power Higher power consump on due to Lower power consump on as it integrates
Consump on addi onal external components. all components on a single chip.
Applica on Suitable for general-purpose Designed for embedded systems like home
compu ng and complex appliances, robo cs, etc.
processing.
Cost More expensive due to the need Cost-effec ve due to integrated
for external components. peripherals.
Example Intel 8086, Intel i7 8051, PIC, AVR, ARM Cortex-M
2. Internal Block Diagram of 8051 Microcontroller Architecture

The 8051 microcontroller architecture consists of several key components:

1. CPU: The central processing unit that controls the en re opera on of the microcontroller.

2. ROM (Read-Only Memory): Stores the program code. In the 8051, it is typically 4KB.

3. RAM (Random Access Memory): Used to store data and variables during program execu on.
It is 128 bytes in the 8051.

4. I/O Ports: 8051 has four parallel I/O ports (P0, P1, P2, P3), each of 8 bits.

5. Timers/Counters: There are two 16-bit mers/counters in the 8051 to generate delays or
count events.

6. Interrupt Control: Allows handling of external events via interrupts.

7. Serial Communica on Control: 8051 supports serial data communica on through the UART.

8. Oscillator/Clock Circuit: Provides the necessary clock signal for the opera on of the
microcontroller.

Block Diagram of 8051:

3. Flag Register of 8051 (PSW)

The Flag Register (Program Status Word or PSW) in 8051 is an 8-bit register that holds the status
flags, which indicate the results of arithme c and logical opera ons.

Bit Structure of PSW:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CY AC F0 RS1 RS0 OV UD P

 CY (Carry Flag): Set if a carry is generated from the most significant bit (used in addi on and
subtrac on).

 AC (Auxiliary Carry Flag): Used in BCD arithme c opera ons.

 F0 (User Flag): A user-defined flag for any purpose.

  RS1, RS0 (Register Bank Select): Select the register bank (0 to 3) in the 8051.

 OV (Overflow Flag): Set if the result of an opera on overflows the register.

 UD (Unused Flag): Reserved for future use.

 P (Parity Flag): Set if the number of 1’s in the accumulator is odd.

4. 8051 Ports

The 8051 microcontroller has four parallel I/O ports (P0, P1, P2, P3), each of 8 bits, which are used
for interfacing with external devices.

1. Port 0 (P0):

o 8-bit bi-direc onal port used for input or output.

o It is also used for mul plexed address and data bus in some 8051 variants.

2. Port 1 (P1):

o 8-bit bi-direc onal I/O port.

o It is fully sta c, meaning it can drive a pin high or low.

3. Port 2 (P2):

o 8-bit bi-direc onal I/O port.

o It can also be used for high-order address bus during external memory interfacing.

4. Port 3 (P3):

o 8-bit I/O port with addi onal func ons like serial communica on, interrupts, etc.

o P3.0 (RXD): Serial input (used in UART for receiving data).

o P3.1 (TXD): Serial output (used in UART for transmi ng data).

o P3.2 (INT0) and P3.3 (INT1): External interrupt pins.

5. Different Types of Microcontrollers

Microcontrollers are classified based on factors like architecture, size, processing capability, and
applica on. Common types include:

1. 8-bit Microcontrollers:

o Typically use 8-bit data buses.

o Example: 8051, PIC 16, AVR.

2. 16-bit Microcontrollers:

o Have 16-bit data buses and are more powerful than 8-bit controllers.

o Example: PIC 18, MSP430.

 3. 32-bit Microcontrollers:

o Use 32-bit data buses and provide higher processing power.

o Example: ARM Cortex-M, PIC32, STM32.

4. RISC Microcontrollers:

o Use a Reduced Instruc on Set Compu ng (RISC) architecture, focusing on faster

execu on.

o Example: ARM, AVR.

5. CISC Microcontrollers:

o Use Complex Instruc on Set Compu ng (CISC) architecture with a rich set of
instruc ons.

o Example: Intel 8051.

6. Special Purpose Microcontrollers:

o Designed for specific applica ons, such as motor control, automo ve, or embedded
systems.

o Example: TMS320 (Texas Instruments).

6. 8051 Internal RAM Organiza on

The internal RAM of the 8051 microcontroller is organized into several sec ons:

1. General-purpose RAM (128 bytes):

o Memory loca ons 0x00 to 0x7F are used as general-purpose RAM for storing
variables, data, etc.

2. Special Func on Registers (SFR):

o Memory loca ons 0x80 to 0xFF are used for Special Func on Registers (SFR), which
control I/O ports, mers, serial communica on, etc.

3. Bit-addressable RAM:

o The first 32 bytes of the RAM (from 0x20 to 0x2F) are bit-addressable. This means
each bit can be accessed and manipulated individually.

4. Stack Area:

o The stack is maintained star ng from 0x08 to 0x1F. The stack is used for storing
return addresses during func on calls and temporary data.
 5. Internal RAM Organiza on Diagram:

+-----------------+-------------------------+

| 128 Bytes RAM | Special Func on |

| (0x00 to 0x7F) | Registers (0x80 to |

+-----------------+ 0xFF) |

| Bit-addressable| |

| RAM (0x20-0x2F) |

+-----------------+-------------------------+

This structure allows for flexible data storage and efficient handling of different memory
requirements within the microcontroller.