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▪ Here, we introduce additional features of Verilog, present more elaborate examples, and compare alternative
descriptions of combinational circuits in Verilog.
▪ Sequential circuits are presented in Chapter 5.
▪ The module is the basic building block for modeling hardware with the Verilog HDL.
▪ The logic of a module can be described in any one (or a combination) of the following modeling styles:
• Gate-level modeling using instantiations of predefined and user-defined primitive gates.
• Dataflow modeling using continuous assignment statements with the keyword assign.
• Behavioral modeling using procedural assignment statements with the keyword always.
Note: There is one other modeling style, called switch-level modeling. It is sometimes used in the simulation of MOS
transistor circuit models, but not in logic synthesis. We will not consider switch-level modeling. 2
▪ Gate-level modeling was introduced in Section 3.10 with a simple example.
▪ In this type of representation, a circuit is specified by its logic gates and their interconnections.
▪ Gatelevel modeling provides a textual description of a schematic diagram.
▪ The Verilog HDL includes 12 basic gates as predefined primitives. Four of these primitive gates are of the three-state
type.
▪ The other eight are all declared with the lowercase keywords and, nand, or, nor, xor, xnor, not, and buf .
▪ Primitives such as and are n -input primitives. They can have any number of scalar inputs (e.g., a three-input and
primitive).
▪ The buf and not primitives are n -output primitives. A single input can drive multiple output lines distinguished by
their identifiers.
▪ When a primitive gate is listed in a module, we say that it is instantiated in the module.
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Note: identifiers having multiple bit widths are called vectors.
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The first (leftmost) number (array index) listed is always the MSB of the vector.)
▪ Two or more modules can be combined to build a hierarchical description of a design.
▪ There are two basic types of design methodologies: top down and bottom up.
▪ In a top-down design, the top-level block is defined and then the subblocks necessary to build the top-level block are
identified.
▪ In a bottom-up design, the building blocks are first identified and then combined to build the top-level block.
▪ For example, the binary adder of Fig. 4.9 .
▪ It can be considered as a top-block component built
with four full-adder blocks, while each full adder is
built with two half-adder blocks.
▪ In a top-down design, the four-bit adder is defined first,
and then the sub-blocks needed to make top-level
blocks are described.
▪ In a bottom-up design, the half adder is defined, then
each full adder is constructed, and then the four-bit adder is built from the full adders.
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A bottom-up hierarchical description of a four-bit adder
▪ The half adder is defined by instantiating primitive gates.
▪ The next module describes the full adder by instantiating and
connecting two half adders.
▪ The third module describes the four-bit adder by instantiating and
connecting four full adders.
S1
C1
C2
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▪ A three-state gate has a control input that can place the gate into a high-impedance state.
▪ The high-impedance state is symbolized by z in Verilog.
▪ There are four types of three-state gates, as shown in Fig. 4.32 .
▪ The bufif1 gate behaves like a normal buffer if control = 1. The output goes to a high-impedance state z when
control = 0.
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Note:
▪ An unknown value is denoted by x and a high impedance by z .
▪ An unknown value is assigned during simulation when the logic
value of a signal is ambiguous.
▪ A high-impedance condition occurs at the output of three-state
gates that are not enabled or if a wire is inadvertently left
unconnected.
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The outputs of three-state gates can be connected together to form a common output line.
To identify such a connection, Verilog HDL uses the keyword tri (for tristate) to indicate that the output has multiple
drivers.
As an example, consider the two-to-one line multiplexer with three-state gates shown in Fig. 4.33 .
Note: The 2 three-state buffers have the same output. In order to show that they have a common connection, it is necessary
to declare m_out with the keyword tri.
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▪ Dataflow modeling of combinational logic uses a number of operators that act on binary operands to produce a binary
result.
▪ Verilog HDL provides about 30 different operators.
▪ Dataflow modeling uses continuous assignments and the keyword assign.
▪ A continuous assignment is a statement that assigns a value to a net. The data type family net is used in Verilog HDL to
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represent a physical connection between circuit elements.
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Thank You
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Dataflow HDL models describe combinational circuits by their function rather than by their gate structure 13
▪ A Verilog HDL synthesis compiler can accept this module description as input, execute synthesis algorithms, and provide
an output netlist and a schematic of a circuit equivalent to the one in Fig. 4.17, all without manual intervention!
▪ The designer need not draw the schematic.
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The next example uses the conditional operator ( ? : ). This operator takes three operands:
condition ? true-expression : false-expression;
The condition is evaluated. If the result is logic 1, the true expression is evaluated and used to assign a value to the left-
hand side of an assignment statement. If the result is logic 0, the false expression is evaluated. - -
- The two conditions together are equivalent to an if–else condition.
The continuous assignment
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▪ Behavioral modeling represents digital circuits at a functional and algorithmic level.
▪ It is used mostly to describe sequential circuits, but can also be used to describe combinational circuits.
▪ Behavioral descriptions use the keyword always , followed by an optional event control expression and a list of
procedural assignment statements.
▪ The event control expression specifies when the statements will execute. The target output of a procedural assignment
statement must be of the reg data type.
▪ Contrary to the wire data type, whereby the target output of an assignment may be continuously updated, a reg data
type retains its value until a new value is assigned
o Since variable m_out is a target output, it must be
declared as reg data (in addition to the output
declaration).
o The procedural assignment statements inside the
always block are executed every time there is a change
in any of the variables listed after the @ symbol.
(Note that there is no semicolon (;) at the end of the
always statement.) 16
▪ The select input is defined as a two-bit vector,
and output y is declared to have type reg .
▪ The always Statement has a sequential block
between the keywords case and endcase .
▪ The block is executed whenever any of the
inputs listed after the @ symbol changes in value.
▪ The case statement is a multiway conditional
branch construct.
▪ Whenever in_0, in_1, in_2, in_3 or select
change, the case expression ( select ) is
evaluated and its value compared, from
top to bottom, with the values in the list of
statements that follow, the so-called case items.
▪ The statement associated with the first case item that matches the case expression is executed. In the absence of a match, no
statement is executed.
▪ Since select is a two-bit number, it can be equal to 00, 01, 10, or 11. The case items have an implied priority because the list is
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evaluated from top to bottom.
▪ Binary numbers in Verilog are specified and interpreted with the letter b preceded by a prime.
▪ The size of the number is written first and then its value. Thus, 2’b01 specifies a two-bit binary number whose value is 01.
▪ Numbers are stored as a bit pattern in memory, but they can be referenced in decimal, octal, or hexadecimal formats with
the letters ‘d, ‘o, and ‘h, respectively.
▪ For example, 4’ HA = 4’ d10 = 4’ b1010 and have the same internal representation in a simulator.
▪ If the base of the number is not specified, its interpretation defaults to decimal.
▪ If the size of the number is not specified, the system assumes that the size of the number is at least 32 bits;
- if a host simulator has a larger word length—say, 64 bits—the language will use that value to store unsized
numbers.
▪ The integer data type (keyword integer) is stored in a 32-bit representation.
▪ The underscore (_) may be inserted in a number to improve readability of the code
(e.g., 16’b0101_1110_0101_0011 ). It has no other effect.
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▪ A test bench is an HDL program used for describing and applying a stimulus to an HDL model of a circuit in order to
test it and observe its response during simulation.
▪ Test benches can be quite complex and lengthy and may take longer to develop than the design that is tested.
▪ The results of a test are only as good as the test bench that is used to test a circuit.
▪ Care must be taken to write stimuli that will test a circuit thoroughly, exercising all of the operating features that are
specified.
▪ In addition to employing the always statement, test benches use the initial statement to provide a stimulus to the circuit
being tested.
▪ The always statement executes repeatedly in a loop.
▪ The initial statement executes only once, starting from simulation time 0, and may continue with any operations that
are delayed by a given number of time units, as specified by the symbol #.
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▪ For example, consider the initial block
▪ The block is enclosed between the keywords begin and end .
▪ At time 0, A and B are set to 0. Ten time units later, A is changed to 1.
▪ Twenty time units after that (at t = 30 ), A is changed to 0 and B to 1.
Inputs specified by a three-bit truth table can be generated with the initial block:
▪ When the simulator runs, the three-bit vector D is initialized to 000 at time
= 0.
▪ The keyword repeat specifies a looping statement: D is incremented by 1
seven times, once every 10 time units.
▪ The result is a sequence of binary numbers from 000 to 111.
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A stimulus module has the following form:
▪ A test module is written like any other module, but it typically has no inputs or outputs.
▪ The signals that are applied as inputs to the design module for simulation are declared in the stimulus module as local reg
data type.
▪ The outputs of the design module that are displayed for testing are declared in the stimulus module as local wire data type.
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▪ The module under test is then instantiated, using the local
identifiers in its port list.
▪ Figure 4.34 clarifies this relationship. The stimulus
module generates inputs for the design module by
declaring local identifiers t_A and t_B as reg type and
checks the output of the design unit with the wire
identifier t_C .
▪ The local identifiers are then used to instantiate the design
module being tested.
▪ The simulator associates the (actual) local
identifiers within the test bench, t_A, t_B , and t_C, with
the formal identifiers of the module ( A, B, C ).
▪ The association shown here is based on position in the port list, which is adequate for the examples that we will consider.
▪ Note: Verilog, however, provides a more flexible name association mechanism for connecting ports in larger circuits.
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▪ The response to the stimulus generated by the initial and always blocks will appear in text format as standard output
and as waveforms (timing diagrams) in simulators having graphical output capability.
▪ Numerical outputs are displayed by using Verilog system tasks .
▪ These are built-in system functions that are recognized by keywords that begin with the symbol $ .
▪ Some of the system tasks that are useful for display are
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▪ The format specification uses the symbol % to specify the radix of the numbers that are displayed and may have a
string enclosed in quotes (“ ”).
▪ The base may be binary, decimal, hexadecimal, or octal, identified with the symbols %b, %d, %h, and %o,
respectively (%B, %D, %H, and %O are valid too).
▪ E.g., the statement $display ("%d %b %b", C, A, B); specifies the display of C in decimal and of A and B in binary.
▪ Note that there are no commas in the format specification.
▪ An example that specifies a string enclosed in quotes may look like the statement
$display ("time = %0d A = %b B = %b ", $time, A, B); and will produce the display
time = 3 A = 10 B = 1
where (time = ), (A = ), and (B = ) are part of the string to be displayed
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▪ The initial block specifies a sequence of binary values to be applied during the simulation.
▪ The output response is checked with the $monitor system task. Every time a variable in its argument
changes value, the simulator displays the inputs, output, and time. 25
▪ A $monitor system task displays the output caused by the given stimulus.
▪ A commented alternative statement having a $display task would create a header that could be used with a $monitor
statement to eliminate the repetition of names on each line of output
▪ We next show an HDL example that produces the truth table of a combinational circuit.
▪ Logic simulation is a fast and accurate method of verifying that a model of a combinational circuit is
correct.
▪ There are two types of verification: functional and timing.
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▪ In functional verification, we study the circuit logical operation independently of timing considerations.
- This can be done by deriving the truth table of the combinational circuit.
▪ In timing verification, we study the circuit’s operation by including the effect of delays through the gates.
- This can be done by observing the waveforms at the outputs of the gates for given inputs.
An example of a circuit with gate delays was presented in Section 3.10 in HDL Example 3.3.
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Thank You
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