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3 Ch03 MOSFET

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0% found this document useful (0 votes)
52 views29 pages

3 Ch03 MOSFET

Uploaded by

ayeshabulehyeh44
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 3

MOS Transistor
Introduction
▪ The general outline of the MOSFET operation
▪ Current-voltage characteristics of MOSFET
▪ Physical limitation of small device geometries
▪ Various second-order effects observed in MOSFETs
▪ MOS capacitances
MOSFETs can be used to implement the switches
Transistors as Switches
◆ We can view MOS transistors as electrically controlled
switches
◆ Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
Structure and Operation of MOSFET

5
CMOS Inverter

VDD
A Y
0 1
1 0 OFF
ON
0
1
A Y
OFF
ON

A Y

GND
CMOS NAND Gate

A B Y
0 0 1 OFF
ON
OFF
ON OFF
ON
0 1 1
1
Y
1 0 1 0 ON
A OFF
1 1 0 0
1
1
0 OFF
ON
B OFF
ON
CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate
◆ Y pulls low if ALL inputs are 1
◆ Y pulls high if ANY input is 0

Y
A
B
C
10
P-substrate n-substrate

11
12 © CMOS Digital Integrated Circuits – 4th Edition
Structure and Operation of MOSFET

NFET Structure Diagram

◆ MOSFET is a four-terminal device.


▪ Gate, Source, Drain, Substrate (or Body).
▪ The two n+ region will be the current-conducting terminal of
this device. (Source and Drain)
▪ Conducting channel will be formed by Gate Voltage.
Structure and Operation of MOSFET
◆ Channel current is
controlled by external bias
of four terminals.

◆ Conducting channel has to be formed in order to start current flow


between the source and drain region.
◆ As gate-to-source voltage is increased, the majority carriers (holes) are
repelled back into the substrate, and the p-type substrate is depleted.
◆ As surface potential in the channel region reaches a threshold voltage,
a conducting n-type layer is formed between the source and the
drain.
14
◆ The conducting channel provides an electrical connection between the two n+ regions:
allowing current flows.
◆ VT0 ,Threshold voltage, denotes the value of the gate-to-source voltage required to
create conducting channel.
ni: the intrinsic carrier concentration of silicon

( )
NA: the acceptor concentration
VT = VT 0 +  − 2F + VSB − 2F ND: the donator concentration
Nox: oxide-interface fixed change density
 the substrate bias coefficient
ni:= 1.45 x 1010 cm-3 at room temperature
2q  N A   Si NA = 4 x 1018 cm-3
= ND = 2 x 1020 cm-3
Cox
tox = 26.3 Å
Nox = 4 x 1010 cm-2
the Fermi potential
kT  ni   1.45 1010 
F ( substrate) = ln   = 0.026V  ln  18 
= −0.51V
q  NA   4  10 
16
Example
◆ Example- how a nonzero VSB affects VTH.
▪ the MOS transistor - long channel device 0.80

NA = 4 x 1018 cm-3 0.75

Threshold Voltage VT (V)


ND = 2 x 1020 cm-3 0.70

0.65
tox = 26.3 Å
0.60
Nox = 4 x 1010 cm-2
◆ Sol. 0.55

0.50

▪ Calculate the  0.45

0.40
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

Substrate Bias VSB (V)


2  q  N A   si 2 1.6 10 −19
 4 10 11.7  8.85 10
18 −14 1
= = = 0.52V 2
Cox 2.20 10−6

▪ Compute and plot the threshold voltage


VT = VT 0 +  ( − 2F + VSB − 2F )
= 0.48 + 0.52  ( 1.01 + VSB − 1.01 )
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19
20
MOSFET Operation : A Qualitative view
◆ For VGS>VT0 , VDS=0
▪ Drain current ID equal to zero.
◆ For VGS>VT0 , 0 < VDS < VDSAT
▪ Drain current ID proportional to VDS
▪ Called the linear mode (or linear region).
◆ For VGS>VT0 , VDS = VDSAT
▪ Inversion charge at the drain is reduced to
zero : pinch-off point.
◆ For VGS>VT0 , VDSAT < VDS
▪ A depleted surface region forms adjacent to
the drain and grows toward source.
▪ Called Saturation mode (or saturation region)
MOSFET Operation : A Qualitative view
◆ MOSFET operating in the saturation region
▪ As the inversion layer near the drain, effective channel length
is decreased.
▪ Voltage of channel-end remains constant and equal to VDSAT
▪ Pinched-off area of the channel absorbs most of the excess
voltage drop (VDS–VDSAT).
▪ A high-field is generated between the channel-end and the
drain boundary.

22
Gradual Channel Approximation (1)

◆ Analysis of the actual three-dimension MOS system is


very complex.
◆ We will use the gradual channel approximation(GCA)
for establishing the MOSFET current-flow problem.
23
Gradual Channel Approximation
The boundary conditions for the channel voltage Vc are
Vc ( y = 0 ) = VS = 0
(3.25)
Vc ( y = L ) = VDS

◆ It is assumed that the entire channel region between the source and the drain is
inverted
VGS  VT 0
(3.26)
VGD = VGS − VDS  VT 0

◆ Let QI(y) be the total mobile charge in the surface inversion layer, which can be
expressed as
QI ( y) = −Cox  [VGS − VC ( y) − VT 0 ] (3.27)
Gradual Channel Approximation (3)

◆ Assume that all the mobile electron in the inversion layer


have a constant surface mobility μn. Then we can express
the incremental resistance as
dy
dR = −
25 W  n  QI ( y ) (3.28)
Gradual Channel Approximation (4)
◆ Assume that the channel current density is uniform across this
segment.
◆ Applying the Ohm’s law for this segment, we can write the voltage
drop along segment dy in the y-direction as follows,
ID
dVC = I D  dR = −  dy
W  n  QI ( y )
Integrate this equation along the channel.

VDS
I D  L = W  n  C ox  (VGS − VC − VT 0 )  dVC
0

n  C ox W
ID =   [2  (VGS − VT 0 )VDS − VDS
2
]
2 L

k W
I D =   [2  (VGS − VT 0 )VDS − VDS 2
] k  =  n  Cox
2 L
k
I D =  [2  (VGS − VT 0 )VDS − VDS
2
] k = k  W / L
2

26
Example 3.4
◆ Examine the relationship between ID and VDS.
▪ n = 76.3cm2/V∙s
▪ Cox=2.2∙10-2 F/m2
▪ W = 20m
▪ L = 2m
▪ VT0=0.48V

◆ Sol.
▪ Calculate the k
W 20 m
k = n  Cox  = 76.3cm 2 / V  s  2.2 10−6 F/cm 2  = 1.68mA/V 2
L 2 m
▪ ID equation
I D = 0.84mA / V 2  2  (VGS − 0.48)  VDS − VDS 2 

27
◆ The above drain current equation is not valid beyond the
boundary between the linear region and the saturation
region. i.e., for,
VDS  VDSAT = VGS − VT 0 (3.37)

◆ The drain current remains approximately constant around


the peak value reached for beyond the saturation
boundary. This saturation current equals,

n  C ox W
I D ( sat ) =   [2  (VGS − VT 0 )  (VGS − VT 0 ) − (VGS − VT 0 ) 2 ]
2 L
n  C ox W (3.38)
=   (VGS − VT 0 ) 2

2 L

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