THE INTEL 8086 MICROPROCESSOR

LECTURE - 4

Abdullah Al Noman
Lecturer
Computer Science and Engineering Department
Shahjalal University of Science and Technology
 PIN Diagram of 8086
(External Architecture)
PIN DIAGRAM OF 8086 MICROPROCESSOR

Introduction
Unlike the 8085 microprocessor, an 8086 to have better
performance, operates in 2 modes that are minimum and
maximum mode.

The minimum mode is a single processor configuration

while the maximum mode is a multiple processor
configuration.

Due to this reason, in the 40 pin IC of 8086

microprocessor, 8 pins i.e., pin numbered from 24 to 32
are assigned different configurations separately
according to the two modes.
PIN DIAGRAM OF 8086 MICROPROCESSOR

VCC (Pin #40) – At this pin, the external power supply

of + 5V is provided to the processor.

VSS (Pin #1 and 20) – These two pins acts as the

ground. This pin directs the extra current of the
microprocessor to ground.

AD0 – AD15 (Pin #2 to 16 and 39) – These are the

multiplexed address and data bus.

We know that the 8086 microprocessor has 20-bit

address bus and 16-bit data bus. So, the 16 lines of the
address and data bus are multiplexed together so as to
reduce the number of lines inside the IC.
PIN DIAGRAM OF 8086 MICROPROCESSOR

A16/S3, A17/S4, A18/S5 and A19S6 (Pin #35 to 38) –

Out of 20 address bits, 4 are present in the multiplexed
form with the status signals. In the case of memory
operations, these pins act as an address bus and contain
the memory address of any particular instruction or data.

However, from I/O operations these pins are low that

shows the status of the processor.

Basically, the signal at S3 and S4 show that which

segment is currently accessed by the microprocessor
among the four segments present in it.
PIN DIAGRAM OF 8086 MICROPROCESSOR

The table below will show the encoding of S3 and S4:

S5, when enabled, shows the presence of an interrupts in

the microprocessor. So, basically, it serves as an interrupt
flag.
PIN DIAGRAM OF 8086 MICROPROCESSOR

The signal at S6 shows the status of the bus master for

the current operation. More simply we can say, whether
the 8086 is the bus master or any other proficient device
is acting as the bus master.

When 0 is present as the signal at this pin then it

indicates the 8086 is holding the access of the bus
otherwise it is high i.e., 1.
PIN DIAGRAM OF 8086 MICROPROCESSOR

BHE’ / S7 (Pin #34) – BHE’/S7 is used as BHE’ (Bus

High Enable) during the first clock cycle of an
instruction execution. The 8086 outputs a low on this pin
during read, write, and interrupt acknowledge cycles in
which data are to be transferred in a high-order byte
(AD15-AD8) of the data bus.

BHE can be used in conjunction with AD0 to select

memory banks. During all other cycles BHE’/S7 is used
as S7 and the 8086 maintains the output level (BHE’) of
the first clock cycle on this pin.
PIN DIAGRAM OF 8086 MICROPROCESSOR

MN/MX’ (Pin #33) – The input at this particular pin sets

the 8086 whether the processor will operate in the
minimum mode or maximum mode.

A signal 0 at this pin sets the 8086 in maximum mode

i.e., multiple processors. While signal 1 sets it in
minimum mode i.e., single processor.

RD’ (Pin #32) – An active low signal at this pin shows

that the microprocessor is performing read operation
with either memory or I/O devices.
PIN DIAGRAM OF 8086 MICROPROCESSOR

CLK (Pin #19) – A signal at this pin provides the timing

to the internal operations that are being executed inside
the microprocessor.

NMI (Pin #17) – NMI is the non-maskable interrupt

input activated by a leading edge. When an NMI occurs,
then an interrupt service routine is generated by the
interrupt vector table.

TEST’ (Pin #23) – This pin basically shows the wait

instruction. Whenever a low signal at this pin occurs then
the processing inside the processor continues. As against,
in case of the high signal, the processor has to wait for
the disabling of this pin.
PIN DIAGRAM OF 8086 MICROPROCESSOR

INTR (Pin #18) – The processor after each clock cycle

samples the INTR and if the signal at this pin is found to
be high then the processor controls that interrupt
internally.

READY (Pin #22) – This signal is used by the

peripherals and memory devices in order to show if the
peripherals are ready or not.

RESET (Pin #21) – Whenever this pin is enabled then it

resets the processor and other devices connected to the
system by immediately terminating the recent task.
PIN DIAGRAM OF 8086 MICROPROCESSOR

Pins in Minimum mode

INTA’ (Pin #24) – Whenever an INTR signal is
generated, then the microprocessor generates INTA
signal, as a response to that interrupt.

ALE (Pin #25) – Whenever an address is present in the

multiplexed address and data bus, then the
microprocessor enables this pin.

This is done to inform the peripherals and memory

devices about fetching of the data or instruction at that
memory location.
PIN DIAGRAM OF 8086 MICROPROCESSOR

Pins in Minimum mode

DEN’ (Pin #26) – Whenever a 0 is present at this pin
then the transceiver gets enabled and it separates the data
from the multiplexed address and data bus.

DT/R’ (Pin #27) – This pin is used to show whether the

data is getting transmitted or is received. A high signal at
this pin provides the information regarding the
transmission of data. While a low indicates reception of
data.

M/IO’ (Pin #28) – This pin indicates whether the

processor is performing an operation with memory or
I/O devices.
PIN DIAGRAM OF 8086 MICROPROCESSOR

Pins in Minimum mode

WR’ (Pin #29) – An active low signal at this pin
indicates that the processor is performing write operation
from either memory or I/O devices.

HOLD (Pin #31) – When an external device enables this

pin then the processor stops accessing the buses
immediately after the recent task gets over.

HLDA (Pin #30) – This pin is used as a response pin for

the hold request. Once request for accessing the buses is
produced by an external entity. Then the microprocessor
acknowledges the device that its request will be
considered once it gets over by the current operation.
PIN DIAGRAM OF 8086 MICROPROCESSOR

Pins in Maximum mode

S0‘, S1‘ and S2‘ (Pin #26 to 28) – These are basically 3
status pins and are active low. This means that if the
status at all the 3 pins is 0 then it shows that multiple
interrupts are to be handled in maximum mode.

The table below is representing the status of the

processor in different combinations:
PIN DIAGRAM OF 8086 MICROPROCESSOR

Pins in Maximum mode

QS0 and QS1 (Pin #24 and 25) – These two pins indicate
the status of the 6-byte pre-fetch queue present in the
architecture of 8086.
PIN DIAGRAM OF 8086 MICROPROCESSOR

Pins in Maximum mode

LOCK’ (Pin #29) – This pin is involved in maximum
mode operation. So, basically, when a single processor is
accessing the buses and peripherals then it locks the
resources being used by it. So, that no other entity can
access it until the recent processor frees it.

RQ’/ GT0‘ and RQ’/ GT1‘ (Pin #30 and 31) – Due to
the involvement of multiple processors, these pins
indicate the request and grant permission for accessing
the buses, memory and peripherals.
Internal Architecture of 8086
Microprocessor
INTERNAL ARCHITECTURE OF 8086 (OVERVIEW)

The 8086 microprocessor is internally

divided into two separate functional
units. These are the Bus Interface Unit
(BIU) and the Execution Unit (EU).

The BIU fetches instructions, reads

data from memory and ports, and
writes data to memory and I/O ports.
The EU executes instructions that
have already been fetched by the BIU.

The BIU and EU function

independently.

Internal architecture of the 8086

INSTRUCTION QUEUE

Instruction queue is a First-In-First-

Out (FIFO) group of registers in
which up to six bytes of instruction
code are prefetched from memory
ahead of time.

This is done in order to speed up

program execution by overlapping
instruction fetch with execution.

This mechanism is known as

pipelining.

Internal architecture of the 8086

BUS CONTROL LOGIC

The bus control logic of the BIU

generates all the bus control signals
such as read and write signals for
memory and I/O.

Internal architecture of the 8086

 PHYSICAL ADDRESS MAPPING HARDWARE

The 8086 contains the on-chip logical

address to physical address mapping
hardware.

The programmer works with the

logical address which includes the 16-
bit contents of a segment register and
a 16-bit displacement or offset value.

The 8086 on-chip mapping hardware

translates this logical address to 20-bit
physical address which it then
generates on its twenty addressing
pins.

Internal architecture of the 8086

SEGMENT REGISTERS

The BIU has four 16-bit segment

registers. These are the
• Code Segment (CS),
• Data Segment (DS),
• Stack Segment (SS),
• Extra Segment (ES).

The 8086's one megabyte memory is

divided into segments of up to 64K
bytes each. The 8086 can directly
address four segments (256K byte
within the 1 Mbyte memory) at a
particular time.

Internal architecture of the 8086

SEGMENT REGISTERS

Programs obtain access to code and

data in the segments by changing the
segment register contents to point to
the desired segments.

All program instructions must be

located in main memory pointed to by
the 16-bit CS register with a 16-bit
offset in the segment contained in the
16-bit instruction pointer (IP).

Internal architecture of the 8086

 LOGICAL ADDRESS TO PHYSICAL ADDRESS CALCULATION

The BIU computes the 20-bit physical address internally using the
programmer-provided logical address (16-bit contents of CS and IP)
by logically shifting the contents of CS four bits to left and then
adding the 16-bit contents of IP.

For example, if [CS] = 456A16 and [IP] = 162016, then the 20-bit
physical address is generated by the BIU as follows:

Four times logically shifted [CS] to left = 456A016

+ [IP] as offset = 162016
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

20-bit physical address = 46CC016

BIU
SEGMENT REGISTERS

The SS register points to the current

stack. The 20-bit physical stack
address is calculated from SS and SP
for stack instructions such as PUSH
and POP.

The programmer can use the BP

register instead of for accessing the
stack using the based addressing
mode. In this case, the 20-bit physical
stack address is calculated from BP
and SS.

Internal architecture of the 8086

SEGMENT REGISTERS

The DS register points to the current

data segment; operands for most
instructions are fetched from this
segment.

A 16-bit offset (Effective Address,

EA) along with the 16-bit contents of
DS are used for computing the 20-bit
physical address.

Internal architecture of the 8086

SEGMENT REGISTERS

The ES register points to the extra

segment in which data (in excess of
64K pointed to by DS) is stored.

String instructions use ES and DI to

determine the 20-bit physical address
for the destination, and DS and SI for
the source address.

Internal architecture of the 8086

SEGMENT REGISTERS

The segments can be contiguous, partially

overlapped, fully overlapped, or disjoint. An
example of how five segments (segment 0
through segment 4) may be stored in physical
memory are shown aside.

Every segment must start on 16-byte memory

boundaries. Typical examples of values of
segments should then be selected based on
addresses starting at 0000016, 0001016, 0002016,
0003016, …...., FFFF016.

Many applications can be written to simply

initialize the segment registers and then forget
them. One can then work with a 64K memory
as with the 8085.
GENERAL REGISTERS

The EU has eight 16-bit general

registers. These are AX, BX, CX, DX,
SP, BP, SI, and DI.

The 16-bit registers AX, BX, CX, and

DX can each be used as two 8-bit
registers (AH, AL, BH, BL, CH, CL,
DH, DL).

For example, the 16-bit register DX

can be considered as two 8-bit
registers DH (high byte of DX) and
DL (low byte of DX).

Internal architecture of the 8086

GENERAL REGISTERS

The AX is called the 16-bit accumulator while the AL is the 8-

bit accumulator. The use of accumulator registers is assumed
by some instructions.

The Input/Output (IN or OUT) instructions always use AX or

AL for inputting/outputting 16- or 8-bit data to or from an I/O
port.

Multiplication and division instructions also use AX or AL.

The AL register is the same as the 8085 A register.

8086 Registers
GENERAL REGISTERS

The BX register is called the base register. This is the only

general-purpose register, the contents of which can be used for
addressing 8086 memory.

All memory references utilizing these register contents for

addressing use DS as the default segment register.

The BX register is similar to 8085 HL register.

In other words, 8086 BH and BL are equivalent to 8085 H and

L registers, respectively.
8086 Registers
GENERAL REGISTERS

The CX register is known as the counter register.

This is because some instructions such as shift, rotate, and loop

instructions use the contents of CX as a counter.

For example, the instruction “LOOP START” will

automatically decrement CX by 1 without affecting flags and
will check if [CX] = 0. If it is zero, the 8086 executes the next
instruction; otherwise the 8086 branches to the label START.

8086 Registers
GENERAL REGISTERS

The data register DX is used to hold high 16-bit result (data) in

16-bit * 16-bit multiplication or high 16-bit dividend (data)
before a 32-bit / 16-bit division and the 16-bit remainder after
the division.

8086 Registers
SPECIAL PURPOSE REGISTERS

SP – Stack Pointer
BP – Base Pointer
SI – Source Index
DI – Destination Index
MISCELLANEOUS

Arithmetic Logic Unit (16-bit):

Performs 8 and 16-bit arithmetic and
logic operations.

Instruction Register and Instruction

Decoder:
The EU fetches an opcode from the
queue into the instruction register. The
instruction decoder decodes it and
sends the information to the control
circuit for execution.

Temporary Registers: It is an 16-bit

register that holds data values during
arithmetic and logical operations.
Internal architecture of the 8086
FLAG REGISTER
FLAG REGISTER (STATUS FLAGS)

Carry Flag (CY) – Carry is generated when performing n bit operations and the result
is more than n bits, then this flag becomes set i.e. 1, otherwise, it becomes reset i.e. 0.

if a 16-bit addition gives a 17-bit result then the extra 1-bit goes to the carry flag. Also
for subtracting a large number from a small number, The value of the carry flag can be 1
(for borrowing 1). (This is one kind of overflow which we will see in the upcoming
slides.)

ADD AX, BX

ADD BH, CL
FLAG REGISTER (STATUS FLAGS)

Parity Flag (P) – After any arithmetic or logical operation if the lower 8-bit of the result
has even parity, an even number of 1, then the parity register becomes set i.e. 1,
otherwise it becomes reset i.e. 0.

Let's say the result of an operation is as follows:

10111010 01101000
What will be the state of PF?

00000000
What will be the state of PF?

01000000
What will be the state of PF?
FLAG REGISTER (STATUS FLAGS)

Auxiliary Carry Flag (AC) – After any arithmetic or logical operation, for the lower 8-
bit of the result, if carry-in occurs from the lower nibble to the higher nibble then this
flag becomes set i.e. 1, otherwise, it becomes reset i.e. 0.

00101011 2BH
addition 00111001 39H
01100100 64H
FLAG REGISTER (STATUS FLAGS)

Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H, the
zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

00110000 30H
subtraction 00110000 30H
00000000 00H
FLAG REGISTER (STATUS FLAGS)

Sign Flag (S) - After any operation, if the MSB of the result is 1, it indicates the number
is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number
is positive and the sign flag becomes reset i.e. 0.

00110000 30H
subtraction 01000000 40H
1 11110000 -AH
FLAG REGISTER (STATUS FLAGS)

Overflow Flag (OF) - This flag will be set (1) if the result of a signed operation is too
large to fit in the number of bits available to represent it, otherwise reset (0).

Additionally, there are four types of overflow.

1. Signed overflow, (It occurs when a signed representation of a number is taken.)

2. Unsigned overflow,
3. Both overflow,
4. No overflow
FLAG REGISTER (STATUS FLAGS)

Basics

What is the range of 8-bit signed numbers? (-128 to 127)

What is the range of 8-bit unsigned numbers? (0 to 255)

For the following binary number, what are the signed and unsigned value?
1000 0001
Signed value = ?
Unsigned value = ?
FLAG REGISTER (STATUS FLAGS)

Overflow

See the following example,

Unsigned Representation Signed Representation
255 1 111 1111 2’s comp -1
1 0 000 0001 2’s comp 1
------------------------------------------------------------------ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------

256 1 0 000 0000 0

Carry Flag = 1

Unsigned Result = 0 Signed Result = 0

Doesn't Match! So, an Matched! So, not a

unsigned overflow. signed overflow.
Why did this error occur? (Because of less storage capacity!)
So, we must mention it as overflow. Carry Flag = 1 means an unsigned overflow occurred.
FLAG REGISTER (STATUS FLAGS)

Overflow

See another example,

Unsigned Representation Signed Representation
127 0 111 1111 2’s comp +127
127 0 111 1111 2’s comp +127
------------------------------------------------------------------ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------

254 1 111 1110 254

Carry Flag = 0

Unsigned Result = 254 Signed Result = -2

Matched! So, not an Doesn't Match! So, a

unsigned overflow. signed overflow.
Why did this error occur? (Because of less storage capacity!)
So, we must mention it as overflow. Carry Flag = 0 means an no unsigned overflow.
FLAG REGISTER (STATUS FLAGS)

Overflow

In short….. OF CF
CF = 1 Unsigned overflow 0 0 No overflow
CF = 0 No unsigned overflow 0 1 Unsigned overflow
OF = 1 Signed overflow 1 0 Signed overflow
OF = 0 No signed overflow 1 1 Both overflow
FLAG REGISTER (STATUS FLAGS)

Overflow

Example of both overflow,

Unsigned Representation Signed Representation
128 1 000 0000 2’s comp -128
128 1 000 0000 2’s comp -128
------------------------------------------------------------------ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------

256 1 0 000 0000 -256

Carry Flag = 1

Unsigned Result = 0 Signed Result = 0

Doesn't Match! So, an Doesn't Match! So, a

unsigned overflow. signed overflow.
So, both overflow!
FLAG REGISTER (STATUS FLAGS)

Overflow
The overflow flag traces this bit-line (MSB)
OF for whether there is a carry-in or carry-out.

Unsigned Representation Signed Representation

128 1 000 0000 2’s comp -128
128 1 000 0000 2’s comp -128
------------------------------------------------------------------ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------

256 1 0 000 0000 -256

Carry Flag = 1

Unsigned Result = 0 Signed Result = 0

Doesn't Match! So, an Doesn't Match! So, a

unsigned overflow. signed overflow.
So, both overflow!
FLAG REGISTER (STATUS FLAGS)

Overflow

Carry in Carry out Overflow

No No No
No Yes Yes
Yes No Yes
Yes Yes No
FLAG REGISTER (CONTROL FLAGS)

Trace Flag (TF) - This flag is used for on-chip debugging.

• Setting trace flag puts the microprocessor into single step mode for debugging.

• In single stepping, the microprocessor executes a instruction and enters into single
step ISR.

• If trap flag is set (1), the CPU automatically generates an internal interrupt after each
instruction, allowing a program to be inspected as it executes instruction by
instruction.
FLAG REGISTER (CONTROL FLAGS)

Interrupt Flag (IF) – This flag is for interrupts. If interrupt flag is set (1), the
microprocessor will recognize interrupt requests from the peripherals. If interrupt flag is
reset (0), the microprocessor will not recognize any interrupt requests and will ignore
them.

Directional Flag (DF) – This flag is specifically used in string instructions. If

directional flag is set (1), then access the string data from higher memory location
towards lower memory location. If directional flag is reset (0), then access the string
data from lower memory location towards higher memory location.
THANK YOU