Mathematical Models and Simulations of Phase Noise in Phase-Locked Loops
Mathematical Models and Simulations of Phase Noise in Phase-Locked Loops
Abstract
Limkumnerd, S. and Eungdamrong, D.
Mathematical models and simulations of phase noise in phase-locked loops
Songklanakarin J. Sci. Technol., 2007, 29(4) : 1017-1028
Phase noises in Phase-Locked Loops (PLLs) are a key parameter for communication systems that
contribute the bit-rate-error of communication systems and cause synchronization problems. Accurate
predictions of phase noises through mathematical models are consequently desirable for practical designs
of PLLs. Despite many phase noise models derived from noise sources from electronic devices such as an
oscillator and a multiplier have been proposed, no phase noise models that include noises from loop filters
have specifically been investigated. This paper therefore investigates the roles of loop filters in phase noise
contribution. The major scopes of this paper is a detailed analysis and simulations of phase noise models
resulting from all components. i.e. a voltage-controlled oscillator, a multiplier and a filter. Two particular
second-order passive and active low-pass filters are compared. The results show that simulations of phase
noises without an inclusion of filter noises may not be accurate because the filter noises, particularly the
active filter, significantly contribute the total phase noise. Moreover, the passive filter does not significantly
dominate the phase noise at low offset frequency while the active filters entirely dominate. Therefore, the
passive filter is a more efficient filter for PLL circuit at low offset frequency. The phase noise models
presented in this paper are relatively simple and can be used for accurate phase noise prediction for PLL
designs.
Key words : phase-locked-loop, phase noise, voltage control oscillator, phase detector,
loop filter, main divider
1
M.Sc. student in Telecommunication, 2Ph.D.(Electrical and Computer Engineerging), Asst. Prof., School
of Communications Instrumentations and Control Sirindhorn International Institute of Technology,
Thammasat University, 131 Moo 5, Tiwanont Road, Bangkadi, Muang, Pathum Thani, 12000 Thailand.
Corresponding e-mail: thanyee@yahoo.com
Received, 28 November 2006 Accepted, 28 February 2007
Songklanakarin J. Sci. Technol. Simulations of phase noise in phase-locked loops
Vol. 29 No. 4 Jul. - Aug. 2007 1018 Limkumnerd, S. and Eungdamrong, D.
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Phase Locked Loops (PLLs) are extensively important before practical implementations.
used for a variety of radio applications such as in Despite Leeson's Equation (1966) being first
frequency synthesizers or in carrier recovery and recognized as a classical phase noise prediction in
clock recovery circuits (Lathi, 1998). Such PLLs PLLs, such equation predicts only the single-
are closed-loop systems that utilize a negative sideband phase noise measured from the power
feedback to sustain a constant ratio of an output spectral density of the carrier and an amplitude
frequency to an input frequency (Rohde, 1997). variation may also be included. Moreover,
Generally, desirable performances of PLLs are not calculating phase noise using Leeson's equation
only high frequency but also low phase noise requires not only operation of all linear device but
(Rohde et al., 2005). The high frequency opera- also an oscillator that contains only a single
tions can be achieved through the use of high resonator (Razavi, 2001). Recently, Ducker (2000)
transition frequency (fT) technologies such as has proposed mathematical models of double-
Bipolar or BiCMOS devices. However, the phase sideband phase noise through two major noise
noises have significantly degraded the perform- sources, i.e. voltage-controlled oscillator and
ances of PLLs by reducing the signal-to-noise multiplier. Although Eric Ducker's equations are
ratio (SNR), increasing adjacent channel power relatively simple for phase noise prediction, noise
and reducing adjacent channel rejection (Kroupa, models of loop filter have not yet been studied.
2003). As a result, the degraded performances of As loop filters can be of various types and
the PLLs contribute the bit-rate-error of commu- orders, they may significantly generate noises
nication systems and cause synchronization leading to the total phase noise of PLLs and this
problems in clocked and sampled data digital paper therefore investigates the roles of loop filters
systems (Misra, 2001). in phase noise contribution through mathematical
Consequently, predicting phase noise models and simulations. The major scope of this
through mathematical models and simulations are paper is a detailed analysis and simulations of
Songklanakarin J. Sci. Technol. Simulations of phase noise in phase-locked loops
Vol. 29 No. 4 Jul. - Aug. 2007 1019 Limkumnerd, S. and Eungdamrong, D.
phase noise models resulting from all components. are devices that convert a high output frequency
i.e. a voltage-controlled oscillator, a multiplier and a reference frequency, respectively, to a low
and using MATHEMATICA and MATLAB. Two frequency for a multiplication process at the PD.
particular second-order passive and active low With reference to Figure 1, the loop gain
pass filters are compared. The paper is organized L(s) (Thamsirianunt and Kwasniewski, 1997) in
as follows; Section 1 commences by literature s-domain can be expressed by a multiplication
reviews on basic PLLs. Sections 2 and 3 then between a forward loop gain G(s) = KpKvF(s)/s and
describe practical effects of phase noise in the a reverse loop gain H(s) = 1/N as
frequency domain and mathematical noise models
1 K × Kv × F(s)
of all components, respectively. Finally, total phase L(s) = G(s) × H(s) = p
noises of PLLs are summarized and simulated in s N
sections 4 and 5. (1)
gain is large enough, the error e(s) becomes a very the carrier (PSSB) to the carrier power (PC). In other
small value in steady state or is almost constant. words,
Equation (3) is consequently equal to Single − Sideband Phase Noise =
d[Constant] F F
= 0 = REF − OUT (4) P
dt R N 10 log(L( f m )) = 10 log C (6)
PSSB
Thus,
On the other hand, the SΦ(fm) can be
FOUT = FREF
N
R (5) measured through the PSD of the modulation of
signal with the ideal phase modulator using the
spectrum analyzer at RF with a 1-Hz resolution-
When the PLL is locked, it produces an
bandwidth. Note that the SΦ(fm) is twice (3-dB more
output that has a small and constant phase error
than) the L(fm). Figure 3 shows plots of the SΦ(fm)
with respect to the input phase but the output
versus the log scale of the offset frequency fm
frequency is the same or linearly proportional to
consequently demonstrating the nonlinear decay
the reference frequency as shown in Equation (5).
and demon-strates various regions of the phase
noise depend-ing on the regions of slopes. Table 1
2. Phase Noise Analysis
summarizes types and slopes of noises in each
Phase noise is widely used to describe the
region. The SΦ(fm) can be described in dBc/Hz
characteristic randomness of frequency stability.
as a general phase noise equation that includes
Generally, two types are single- sideband L(fm) or
the noises in all regions of slopes as summarized in
double sideband SΦ(fm) phase noises. On the other
Table 1. In other words,
hand, the L(fm) can directly be measured through
the power spectral density (PSD) of the signal using
the spectral analyzer at RF with a 1-Hz resolution-
bandwidth filter. Figure 2 shows the measured
PSD of the carrier power and the single-sideband
phase noise power. As shown in Figure 2, the L(fm)
(Manassewitsch, 1987) can be described in decibels
relative to the carrier level as dBc/Hz as the ratio
of the noise power at an offset frequency fm from
sτ (1 + sτ )
for a resistor Pr(R) is assumed to be white noise (14)
and is equal to 4kTBR where k is the Boltzmann's F2_3 F2_2
θVCO (s) =
1 1 Kv
1 + L(s)
(17) θ R (s) = × F2 (s) (23)
s 1 + L(s)
Substituting Equations (16) with Equations (8) Meanwhile the closed loop transfer function for
and (17) yields the phase noise model of the VCO the Op-Amp is expressed as
SΦ_VCO(f) as
1 Kv
SΦ_VCO ( f ) = NVCO ( f ) × θVCO (s)
2
(18) θOA (s) = (24)
s 1 + L(s)
In addition, the closed loop transfer function for By substituting Equations (16) with Equations (15)
the multiplier is given by and (23), the phase noise model of the resistor
L(s) (SΦ_R(f)) is given by
θ MUL (s) = (19)
1 + L(s) 2
SΦ_ R ( f ) = NR ( f ) × θ R (s) (25)
modeled through the summation of phase noise filter F2 shown in Figures 5 and 6, respectively. In
models described in Equations (18), (20) and (27), addition, Table 3 also summarizes values of noise
i.e. SΦ2(f) = SΦ_VCO(f) + SΦ_MUL(f) + SΦ_FIL2(f), and is coefficients used in simulations by Ducker (2000).
described in dBc/Hz as For purposes of comparison, both filters F1 and F2
have been designed to operate at the same corner
SΦ2 ( f m ) = 10 log(SΦ_VCO ( f ) + SΦ_ MUL ( f ) + SΦ_FIL2 ( f ))
frequencies. Figure 7 shows the simulated bode
(29) plots of such two filters. Comparisons of calculated
and simulated values DC gains and corner
5. Simulation Results frequencies are summarized in Table 4. It can be
Phase noises of the PLL have been simulated considered from Table 4 that the corner frequencies
using MATHEMATICA and MATLAB. Based on of both filters F1 and F2 are equal, i.e. f F1_1 = fF2_1 and
Drucker (2000), Table 2 summarizes values of f F1_2 = f F2_2. However, the DC gain of the filter F1 is
components of the passive filter F1 and the active has been constantly fixed while the DC gain of the
filter F2 can be tuned through the corner frequency
Table 2. Summary of values of components of the fF2_3 that behaves as an integrator and yields a -20
passive filter F1 and the active filter F2. dB/decade for the DC gain.
Figure 8 shows the simulated total phase
Components Values Units noise SΦ1(f) in [dBc/Hz] versus offset frequency
Resistors R1 5.62 kΩ in [Hz], running from 1 Hz to 1 GHz. Such total
R2 2.94 kΩ phase noise SΦ1(f) is the sum of SΦ_VCO(f), SΦ_MUL(f)
and SΦ_FIL1(f) as described in Equation (28). As
Capacitors C1 47 nF
C2 6.8 nF
shown in Figure 8, the total phase noises can be
considered in three regions of offset frequency.
First, at the offset frequency lower than approxi-
Table 3. Summary of noise coefficients used in mately 700 kHz, only the multiplier noise
simulations. dominates the total phase noise while both VCO
and filter noises are relatively low at low offset
Components Constants Values
frequency and do not significantly contribute to the
VCO k0_VCO 10-15.5 total noise. Secondly, between 700-kHz to 100-
k2_VCO 10-3 MHz offset frequency, the filter noise dominates
k3_VCO 100.7
Kv 107
Main Divider k0_md 10-15.5
k1_md 10-12.5
N 1000
Reference Divider R 10
Reference Oscillator k0_ref 10-15.8
k1_ref 10-12.7
k2_ref 10-9.86
k3_ref 10-7.82
Resistor k0_R1 10-12.64
k0_R2 10-12.92
Op-Amp k0_OA 10-17.045
k1_OA 10-16.02
Figure7. Simulated magnitude of filters F1 and F2
Phase Detector Kp 0.5
Songklanakarin J. Sci. Technol. Simulations of phase noise in phase-locked loops
Vol. 29 No. 4 Jul. - Aug. 2007 1025 Limkumnerd, S. and Eungdamrong, D.
Values
Filters Parameters
Calculated Simulated
F1 DC Gain kF1 dB 145.38 145.62
Corner Frequency f F1_1 = ω F1_1/2π = 1/τ F1_1 Hz 7.24 × 10 3
7.21 × 103
f F1_2 = ω F1_2/2π = 1/τ F1_2 Hz 5.73 × 104 5.74 × 104
F2 DC Gain kF2 dB 76.02 76.11
Corner Frequency f F2_1 = ω F2_1/2π = 1/τ F2_1 Hz 3.31 × 103 3.35 × 103
f F2_2 = ω F2_2/2π = 1/τ F2_2 Hz 7.24 × 103 7.21 × 103
f F2_3 = ω F2_3/2π = 1/τ F2_3 Hz 5.73 × 104 5.74 × 104
the total noise. Finally, at the offset frequency noise. Secondly, between 10-Hz to 800-kHz offset
higher than approximately 100 MHz, only the frequency, both the filter noises dominate the total
VCO noise dominates. noise. Finally, at the offset frequency higher than
Figure 9 shows the simulated total phase approximately 800 kHz, only the VCO noise
noise SΦ2(f) in [dBc/Hz] versus offset frequency dominates.
in [Hz], running from 1 Hz to 1 GHz. Such total Figure 10 shows the simulated total phase
phase noise SΦ2(f) is the sum of SΦ_VCO(f), SΦ_MUL(f) noises of the PLL in dBc/Hz versus offset fre-
and SΦ_FIL2(f) as described in Equation (29). As quency in [Hz]. As shown in Figure 10, the total
shown in Figure 9, the total phase noises can be phase noise SΦ1(f) decreases by -30 dBc/dec in the
considered in three regions of offset frequency. range of 1 to 35 Hz and gradually decreases until
First, at the offset frequency lower than approxi- 300 kHz offset frequency before decreasing with
mately 10 Hz, only the multiplier noise dominates the slope to -20 dBc/dec before it reaches the noise
the total phase noise while both VCO and filter floor of -155 dBc at approximately 400 MHz. On
noises are relatively low at low offset frequency the other hand, the total phase noise SΦ2(f) starts
and do not significantly contribute to the total at -20 dBc/dec at the low offset frequency range
Figure 8. The simulated total phase noise SΦ1(f) Figure 9. The simulated total phase noise SΦ2(f)
in [dBc/Hz] versus offset frequency in in [dBc/Hz] versus offset frequency in
[Hz]. [Hz].
Songklanakarin J. Sci. Technol. Simulations of phase noise in phase-locked loops
Vol. 29 No. 4 Jul. - Aug. 2007 1026 Limkumnerd, S. and Eungdamrong, D.
Conclusions
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Circuits, McGraw-Hill, London., pp. 100-101. Circuits, Vol. 39; 452-462
Rohde, U.L. 1997. Microwave and Wireless Synthe- Thamsirianunt, M. and Kwasniewski, T.A. 1997. CMOS
sizers, John Wiley & Sons, Inc., New York., pp. VCO’s for PLL Frequency Synthesis in GHz
44-45, Digital Mobile Radio Communications, IEEE
Rohde, U.L., Poddar, A.K. and Bock, G. 2005. The Journal of Solid-State Circuits, Vol. 32; 1511-
Design of Modern Microwave Oscillators for 1524
Wireless Applications, John Wiley & Sons, Inc., Zhang, B. Allen, P.E. and Huard, J.M. 2003. A Fast
New York., pp. 323-324. Switching PLL Frequency Synthesizer with an
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Songklanakarin J. Sci. Technol. Simulations of phase noise in phase-locked loops
Vol. 29 No. 4 Jul. - Aug. 2007 1028 Limkumnerd, S. and Eungdamrong, D.
Appendix
Appendix A.1: Analytical treatments for Equa- Appendix A.2: Analytical treatments for Equa-
tions (10) and (11) tions (13) and (14)
Vout1 (s) 1 1 1 1
F1 (s) = = R1 + sC1 R1 +
sC2 V (s) sC2 sC1
Iin (s) Fs (s) = out2 =
Iin (s) R2
1 1 + sR1C1
=
sC2 sC1
1 1 + sR1C1
1 + sR1C1 sC sC1
=
2
s 2C1C2
= R2
1 1 + sR1C1
+
sC2 sC1
1 + sR1C1 1 + sR1C1
= s 2
C C
sC1 + sC2 + s 2 R1C1C2 =
1 1 2
R2 1 1 + sR1C1
1 1 + sR1C1 sC + sC
= 2 1
s C1 + C2 + sR1C1C2
1 1 + sR1C1
1 + sR1C1 =
sC1 + sC2 + s R1C1C2
2
= R2
sR C C
s(C1 + C2 )(1 + 1 1 2 )
C1 + C2 1 1 + sR1C1
=
kF1 (1 + sτ F1_1 ) sR2 C1 + C2 + sR1C1C2
=
s(1 + sτ F1_2 ) 1 + sR1C1
=
sR C C
sR2 (C1 + C2 )(1 + 1 1 2 )
where kF1 = 1/(C1+C2) is a constant. τF1_1 = R1C1 and C1 + C2
τF1_2 = (R1C1C2)/(C1+C2) are time constants
(1 + sτ F2_1 )
=
sτ F2_3 (1 + sτ F2_2 )