INTRODUCTION:

Flip flops have two stable states and hence they are
bistable multivibrators. The two stable states are High
(logic 1) and Low (logic 0).
They can switch between the states under the influence of
a control signal (clock or enable) i.e. they can flip' to one
state and flop' back to other state.

They are binary storage devices because they can store

binary data (0 or 1).

INTRODUCTION:

They are also known as signal change sensitive

devices which mean that the change in the level of
clock signal will bring change in output of the flip
flop.
"A Flip- flop works dependingon clock pulses.
" Flip flops are also used to control the digital
circuite's functionality. They can an change the
operation of a digital circuit depending on the state
 FLIP-FLOPS

3 classes of flip-flops

latches: outputs respond immediately while

enabled (no timing control)

pulse-triggered flip-flops: outputs response

the triggering pulse

edge-triggered flip-flops: outputs responses to

the control input edge
 S-R FLIP FLOP

" The S-R flip-flop is basic flip-flop among all the flip
flops. All the other flip flops are developed after SR-flip
flop.
" SR flip flop is represented as shown below

SET Output

R
RESET Ioverted
Output

Clock G

S-R FLIP FLOP

Any flip flop can be build using logic gates. NAND and NOR
gates were used as they are universal gates.

Inputs Outputs Action

S R

0 0
No change
1 1 Reset

1 0 1 Set

1 1 0 Undefined
 The Basic SR Flip-flop with clock
Clock S
X X Qn
1 0 0 Qn ’Hold
1 0 Hold
CLK - 1 1 0 1 ’ Hold
1 1 Invalid

-a

-
The Basic SR Flip-flop R

Working
From the diagram it is evident that the flip flop has
mainly four states. They are
S=1, R=0Q=1, Q'=0
This state is also called the SET state.

S=0, R=1Q=0, Q'1

This state is k nown as the RESET state.
In both the states ,the outputs are just compliments
of each other and that the value of Q follows the
value of S.
 S=0, R=0-Q& Q'=Remember
If both the values of S and R are switched to 0,
then the circuit remembers the value of S and R in
their previous state.
S=1, R=1-Q=0, Q'=0 [Invalid]
This is an invalid state because the values of
both Q and Q'are 0.
They are supposed to be compliments of each
other. Normally, this state must be avoided.

JK-FLIP FLOP

The J-K flip-flop is operationally similar to the S

R flip-flop.

The J-K flip-flop is clock driven like the clocked

S-R flip-flop.
The difference is that the J-K flip-flop will retain
its output status when two lows are present at
its inputs. Also, when both inputs are high, the
outputs will toggle on and off
 WORKING

Q and Q' are feedback to the pulse-steering

NAND gates.
No invalid state.
Include a toggle (switch) state.
J=HIGH (and K=LOW) - a SET state
K=HIGH (and J=LOW)- a RESET state
both inputs LOW -a no change
both inputs HIGH - a toggle

Toggling means Changing the next state output to

complement of the present state output'
Toggling will cause the output to complement
again and again.
This complement operation continues until the
Clock pulse goes back to 0. Since this condition is
undesirable, we have to find a way to eliminate this
condition.

This undesirable behavior can be eliminated by

Edge triggering of JK flip-flop or by using master
slave JK Flip-flops.
 JK-FLIP FLOP
X
Toggles on leading edge SR flip-fop
df clock signal

JO J-K
Flip-lop CIko
Clk o
Ko

Symbol Circuit
 D-FLIP FLOP

The D flip-flop is widely used. It is also known as a

"data" or "delay" flip-flop and negative edge
triggered flip flop.
By comparing R-S, J-K, and D flip-flops
see that the D flip-flop never has an unknown
state, unlike the R-S and J-K.
single input D (data)
D=HIGH - aSET state
D=LOW - a RESET state
 D-FLIP FLOP

Q(t)

CIk

Q()

D -Q

CLK CLK

D-FLIP FLOP TRUTH TABLE

CLK D K
1 1
1 0 1

J=Q
 T-FLIP FLOP

" AT flip flop is like JK flip-flop.

These are basically a single input version of JK
flip flop.

This modified form of JK flip-flop is obtained by

connecting both inputs Jand Ktogether.
This flip-flop has only one input along with the
clock input.

T Q(t)
JK
Flip-Flop
K
Q(t)'
T Flip-Flop

clk

clk Llol T J K Q nlololoH R

1 lo 0 1 1 previous
values
1 1
1 1 1 1 1 1 1 compliment
0 1 1 0 1 0 of previous
values
 For Register Devices:
Flip flops can store a single bit of data i.e. 1 or 0.
Registers are used to store multiple bits of data. So
flip flops are used to design Registers. According to
digital electronics, a Register is a device which is
used to store the information.

Data Transfer
The process of transferring the data from one
register to another register
 Introduction
" Counters are a specific type of
sequential circuit.

" Like registers, the state, or the

flip-flop values themselves, serves
as the "output."
1
00 01
" The output value increases by one
on each clock cycle. 1 1

" After the largest value, the output 11 10

"wraps around" back to 0.

Benefits of counters
Counters can act as simple clocks to keep track of "time."

"You may need to record how many times something has

happened.
- How many bits have been sent or received?
" How many steps have been performed in some computation?

" All processors contain a program counter, or PC.

" The PC increments once on each clock cycle, and the next
program instruction is then executed.

Synchronous
Counters

Asynchronous
Asynchronous Counters
The flip-flops do not change states at exactly the same time as
they do not havea common clock pulse.
Output of one flip-flop is connected to the clock input of the
next more-significant flip-flop.
Its simple and requires less hardware.
Has speed limitation.
HIGH

Q,

FFO FF1

Timing diagram
00 ’ 01 ’ 10 ’ 11 ’00 ...

Binary ripple counter

"The counter is called ripple counter because the output of one
flip-flop feed to the clock input of another

The flip flops respond to negative going clock edge.

a
" Each flip flop divides the incoming clock pulse frequency by
factor of 2.

" Cumulative delay is a drawback.

4-Bit Asynchronous Counter
HIGH
FRO FI FF2 FF3

J,

CLK

al

CLK

(b)

Synchronous Counter
Synchronous Counters are so called because the clock input of
all the individual flip-flops within the counter are all clocked
together at the same time by the same clock signal.

The clock signal is directly applied to all Flip flops in a parallel

sequence.

Rising Edge Falling Edge

Logic "1

Logic 0
Count changes
state here