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Scheme of Valuation/Answer Key
(Scheme of evaluation (marks in brackets) and answers of problems/key)
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FOURTH SEMESTER B.TECH (R &S) DEGREE EXAMINATION, MAY 2024 (2019 SCHEME)
Course Code: ECT206
Course Name: COMPUTER ARCHITECTURE AND MICROCONTROLLERS
Max. Marks: 100 Duration: 3 Hours
PART A
(Answer all questions; each question carries 3 marks) Marks
1 Any three points (3 marks) 3
2 Explanation of stack pointer, program counter and accumulator (3 marks) 3
3 Bits of Program Status Word (1 mark) Register bank selection using bits RB1 and 3
RB0 (2 marks)
4 Operations of 3 instructions (3 marks) 3
5 1.5 mark for initialisation of counter, source and destination addresses & 1.5 marks 3
for data transfer
6 # include < reg51.h> 3
void main (void)
{unsigned char z;
For (z=0; z<=255; z++)
P1=z;
}
C program (3 marks)
7 TMOD register format (1 mark) Bit functions (2 marks) 3
8 List of any three SFRs and functions (1 mark each) 3
9 Concept of paging (3 marks) 3
10 Diagram (1 mark) Working (2 marks) 3
PART B
(Answer one full question from each module, each question carries 14 marks)
Module -1
11 a) Converting to binary (1 mark) 5
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Normalised form (1 mark)
32-bit result (3 marks) Ans :1 1000 0010 1001 0100 0000 0000 0000 000
b) General processor block diagram (4 marks) Explanation (5 marks) 9
12 a) Steps (8 marks) 8
b) Explanation address bus, data bus and control bus (2 marks each) 6
Module -2
13 a) Functions of four pins (4*1.5marks) 6
EA= External Access. Active low input, when grounded external program memory
is accessed.
RST= Reset pin. Microcontroller will reset and terminate all activities
XTAL= interfacing external crystal to generate system clock
ALE= Address Latch Enable. For demultiplexing the multiplexed address lines of
port 0
b) Immediate, Register, Direct, Register Indirect and Indexed addressing mode 8
Any four addressing modes with one example each (2 marks each)
14 a) Interrupt execution procedure (6 marks) 6
b) 8 Functions (1 mark each) 8
Module -3
15 a) Any five data types (1 mark each) 5
b) Interfacing diagram (4 marks) Program (5 marks) 9
16 a) Program (7 marks) 7
MOVX A,@DPTR ; To read data from external memory
(Consider the sum and carry )
b) SSD interfacing diagram (3marks) Program (4 marks) 7
Module -4
17 a) 4 modes (2 marks each) 8
b) Explanation (2 marks each) 6
18 a) Explanation of serial data transfer in 8051 (3 marks) 10
TMOD register is loaded with the value 20H
1. TH1 is loaded with value to set the baud rate
2. SCON register is loaded with the value 50H
3. TR1 is set to 1 to start Timer1
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4. TI is cleared by the "CLR TI" instruction
5. transmit character byte is written into the SBUF register
6. TI flag bit is monitored to see if the character has been transferred
completely
7. to transfer the next character, go to Step 5.
+ Program (5 marks) + comments (2 marks)
Program to transfer data serially
Correction in line 03 :MOV SCON, # 50H
b) Structure (2 marks) Explanation (2 marks) 4
Module -5
19 a) Explanation (3 marks) Diagram and example (3 marks) 6
b) Address Translation block diagram (4 marks) + Explanation (4 marks) 8
20 a) Any five differences (1 mark each) Any two advantages (2 marks each) 9
b) Block diagram (2 marks) explanation (3 marks) 5
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