A 0.

5-V 85-nW Rail-to-Rail Operational Amplifier

with a Cross-Coupled Output Stage

Akihiro Tanaka, Zhigang Qin, and Hirokazu Yoshizawa

Graduate school of Electronic Engineering
Saitama Institute of Technology, Fukaya, Saitama 369-0293, Japan

Abstract— A 0.5-V rail-to-rail operational amplifier (op- circuit uses depletion-type NMOS transistors, which are
amp) with a large common-mode input range is proposed. It usually not available in standard CMOS processes.
has a two-stage structure which consists of a complementary Lee used native NMOS transistors for the input pair of
input stage and a novel cross-coupled output stage. The the first stage and realized a sub-0.5V rail-to-rail op-amp
cross-coupled output stage increases the transconductances
[4]. Native transistors can be realized without using extra
of MOSFETs of the output stage without increasing the chip
area. And hence, it increases the drivability for a capacitive masks, but minor process modifications are required.
load. Using HSPICE simulations, it is verified that the Takahashi proposed a 0.5-V rail-to-rail op-amp with a
proposed circuit has a DC gain of more than 80 dB for standard CMOS technology [5]. The first stage (i.e. the
common-mode input voltages from 40 mV to 400 mV with a input stage) of this op-amp, shown in Fig.1, are built using
supply voltage of 0.5 V. Unity-gain frequency is 8.2 kHz with complementary (PMOS and NMOS) input pairs in parallel.
a capacitive load of 40 pF and the power consumption is The second stage consists of a common-source amplifier.
85nW including all bias circuits. The drawback of this circuit is that the input common-
mode range is limited because of M3 and M7 in diode
I. INTRODUCTION configurations, that is, their gate and drain are connected.
The quantity of portable electronic devices such as mobile Hence, it is hard to have a low drain-to-source voltage
phones and portable tablets is drastically increasing, and such as 100 mV unless the gate-to-source voltage is
the demand for low-power circuits is getting higher due to designed to be 100 mV.
their battery operations. In this paper, we propose a 0.5-V rail-to-rail CMOS op-
These devices usually require analog and mixed-mode amp with a large common-mode input range, which can be
circuits. And one of the most important building blocks in realized in a standard CMOS process. In addition, a
analog and mixed-mode circuits is the operational proposed output stage increases the drivability for a
amplifier (op-amp). When the supply voltage is reduced, capacitive load. The performance of the op-amp has been
the signal swing is also reduced. And the signal-to-noise verified by HSPICE simulations.
ratio (SNR) lowers if the noise power is constant.
Therefore, the common-mode input and output ranges
should be as wide as possible in order to have a large SNR. II. PROPOSED 0.5-V RAIL-TO-RAIL OP-AMP
Then the rail-to-rail input/output feature has become very
important especially in low-voltage op-amps. A. Input stage
For more than a decade, low-voltage op-amps which Fig. 2 shows the proposed rail-to-rail op-amp. Unlike
operate with a supply voltage of 1V or below have been the circuit of [5], the gates of M3 and M7 are not
investigated [1-5]. Blalock proposed a body-driven input connected to their drains. Therefore, VDS3 and VSD7 can be
stage for a 1-V rail-to-rail op-amp [1], and Chatterjee as small as 100 mV while keeping these MOS transistors
realized a 0.5-V op-amp by using the body-driven in their weak-inversion saturation regions.
technique [2]. However, the input impedance of these op- In the circuit of Fig. 1, the minimum common-mode
amps drop significantly when the pn junction of an input input voltage, Vcmin (min), is
PMOS transistor, which consists of the source (p-type) Vcmin (min) = VGS3 + VSD1 – VSG1 > 0 V. (1)
and the body (n-type), is forward-biased. The circuit of [2] Assuming VGS3 = VSG1, Vcmin (min) is higher than 0 V. It
may get into the latch-up state when the supply voltage means that the common-mode input range does not cover
exceeds 0.7 V. the ground (0 V) in this structure. In the circuit of Fig. 2,
Stockstad proposed a buffered body-driven technique on the other hand, the minimum common-mode input
and realized a 0.9-V rail-to-rail op-amp [3], which voltage is
operates up to 5.5 V. The input impedance is as high as Vcmin (min) = VDS3 + VSD1 – VSG1 < 0 V. (2)
that of a typical gate-driven CMOS op-amp. However, this

978-1-4799-2452-3/13/$31.00 ©2013 IEEE 137

Assuming VDS3 = VSD1, Vcmin (min) can be lower than 0 V. follower configuration has been investigated. The result is
Therefore, the common-mode input range covers the shown in Fig. 6. The voltage difference between the input
ground (0 V) in the proposed circuit. and output is within +/– 1 mV for the entire range from 0
The maximum common-mode input voltage, Vcmin (max), V to 0.5V. (In this work, device mismatches and process
in the circuit of Fig.1 is corners have not been investigated yet.)
Vcmin (max) = VDD – VSG7 – VDS5 + VGS5 < VDD. (3) Fig. 7 shows the DC gain with the common-mode input
In the circuit of Fig. 2, on the other hand, it is voltage. The proposed circuit has a DC gain of more than
Vcmin (max) = VDD – VSD7 – VDS5 + VGS5 > VDD. (4) 80 dB for common-mode input voltages from 40 mV to
Additionally the proposed circuit has a cascode structure 400 mV, and more than 60 dB from 32 mV to 467 mV.
in the first stage and a high voltage gain is expected. For comparison, the DC gain of an op-amp without the
Each MOSFET has been designed to have a gate-to- cross-coupled output stage (with a common-source output
source voltage (Vgs) of 0.2 V. It is obvious that these stage instead) is also shown in Fig. 7.
MOSFETs operate in their subthreshold regions. Their The transconductance of the input stage is shown in
drain-to-source voltages are kept more than 100 mV so Fig.8. Since the input stage consists of a PMOS pair and
that they stay in their saturation regions. an NMOS pair, the total transconductance of the input
stage depends on the common-mode input voltage. This is
a subject for future.
B. Cross-coupled output stage
Common-mode rejection ratio (CMRR) is shown in
Fig. 3a shows a conventional common-source output Fig.9. CMRR of 90 dB is obtained for low frequencies.
stage. Assume that a PMOS transistor MP3 consists of 10 Figure of merit (FoM) is calculated using the equation
unit transistors in parallel. Fig. 3b is the proposed cross- described below,
coupled output stage. Both MP3a and MP3b consist of 5 UGF ⋅ C L ,
unit transistors in parallel. An NMOS transistor MN3 in FoM = (5)
I total
Fig. 3a is also divided into half and shown in Fig. 3b as
MN3a and MN3b. Therefore the silicon area is unchanged. where UGF is the unity-gain frequency, CL is the load
The gate terminal of MP3b is connected to the gate of capacitance, and Itotal is the current consumed in the whole
MN3a, and the gate terminal of MN3b is connected to the circuit. FoM of the proposed circuit (including all bias
gate of MP3a. For example, VGS of MN3b is 0.3 V while circuits) is 1.93 with a load capacitance of 40 pF.
VGS of MN3a is 0.2 V. Also the source-to-gate voltage Maximum sink current and source current at a supply
(VSG) of MP3b is 0.3 V while VSG of MP3a is 0.2 V. Hence, voltage of 0.5 V are 52 μA and 23 μA, respectively.
it is expected that the cross-coupled output stage increases For comparison, a rail-to-rail op-amp with a common-
the transconductance of MOSFETs of the output stage, source output stage shown in Fig. 10 was simulated. With
and it increases the drivability for a capacitive load. a load capacitance of 5 pF, the unity-gain frequency is 8.3
kHz and the phase margin is 49 degree (which is almost
equal to the phase margin of the circuit shown in Fig. 2
C. Reference-current generation circuit with a load capacitance of 40 pF). With a load capacitance
Fig. 4 shows a current reference circuit. We have of 10 pF, the unity-gain frequency is 7.6 kHz and the
adopted the Oguey bias circuit [6] to generate a reference phase margin is only 40 degree. The phase margin reduces
current of 2 nA. Without using a resistor, a supply- because the second pole moves toward a lower frequency
voltage-independent current-reference circuit is realized. by increasing the load capacitance. On the other hand, in
MIREF in Fig. 4 works as a current source (IREF) in Fig. 2. the proposed circuit (Fig. 2), the second pole locates at a
MR2, MR3, MR4, MR5 and MR6 form the supply- higher frequency because the transconductance of the
independent bias circuit. Unlike a conventional bias circuit output stage is larger than that of Fig. 10. Therefore even
in which a resistor is used, an NMOS transistor MR6 is with a capacitive load of 40 pF, a phase margin of 50
used for the resistor-free circuit [6]. degree is obtained. Table I summarizes simulation results
of the proposed circuit with those of related circuits.
III. SIMULATIONS
IV. CONCLUSIONS
We have run HSPICE simulations for the proposed
circuit shown in Fig. 2 using SPICE parameters for a A 0.5-V rail-to-rail op-amp with a large common-mode
standard 0.18-μm CMOS process with a supply voltage of input range is proposed. It also has a novel output stage.
0.5 V. Bias circuits for VBIAS1 and VBIAS2 (not shown in Using HSPICE simulations, it has been verified that the
Fig.2) are also included in simulations. The threshold proposed circuit operates with a supply voltage of 0.5 V
voltages for PMOS and NMOS are about –0.4 V and and has a DC gain of more than 80 dB for common-mode
0.45V, respectively. input voltages from 40 mV to 400 mV. Unity-gain
Fig. 5 shows the gain and phase margin at the common- frequency is 8.2 kHz with a capacitive load of 40 pF and
mode input voltage of 0.25 V. The DC gain of the the power consumption is 85 nW including all bias circuits.
proposed op-amp is 101 dB, the unity-gain frequency is
8.2 kHz, and the phase margin is 50 degree with a load ACKNOWLEDGMENT
capacitance of 40 pF. The power consumption is 85 nW
This work is supported by VLSI Design and Education
for the whole circuit including bias circuits.
Center (VDEC), the University of Tokyo in collaboration
To verify the common-mode input range, the difference
with Synopsys, Inc. and Rohm Corporation.
between the input and output voltages in a voltage-

138
 REFERENCES VDD = 0.5 V VDD = 0.5 V

[1] B.J. Blalock, P.E. Allen, and G.A. Rincon-Mora,

+ + + MP3b
0.2V MP3 0.2V 0.3V
“Designing 1-V Op Amps Using Standard Digital CMOS VY - VY - 18u/2u
- 18u/2u
18u/2u
Technology,” IEEE Trans. Circuits Syst. II, vol.45, pp. 769- M=5 M=5
M=10
780, Jul. 1998. MP3a
[2] S. Chatterjee, Y. Tsividis, and P. Kinget, "0.5-V Analog Vout
Circuit Techniques and Their Application in OTA and Filter Vout
Design," IEEE Journal of Solid-State Circuits, vol. 40, no. MN3a
12, pp. 2373–2387, Dec. 2005. MN3 MN3b
VX 11u/2u VX 11u/2u
[3] T. Stockstad and H. Yoshizawa, “A 0.9-V 0.5-μA Rail-to- 11u/2u
+ + M=5 +
Rail CMOS Operational Amplifier,” IEEE Journal of Solid- M=10 0.2V 0.3V
State Circuits, vol.37, pp. 286-292, Mar. 2002.
0.2V - - - M=5
[4] E.K.F. Lee, “A Sub-0.5V, 1.5 μW Rail-to-Rail Constant gm
Opamp and Its Filter Application,” Proc. IEEE Int. Symp. (a) (b)
on Circuits and Systems, pp. 197-200, 2012.
[5] R. Takahashi, T. Harada, S. Okuyama, and K. Matsushita, Fig. 3 (a) Conventional common-source output stage; (b) proposed
“Ultra-Low Voltage 2-stage Amplifier Circuit with Wide cross-coupled output stage.
VDD
Input/Output Range,” IEICE Technical Report, ICD2009-85,
pp.49-53, 2009. MR1
[6] H. Oguey and D. Aebischer, “CMOS current reference MR2 MR3
without resistance,” IEEE Journal of Solid-State Circuits,
vol. 32, no. 7, pp. 1132–1135, 1997.
MR4
VDD
MR5 IREF
M7 M8
IS2
MR6 MIREF

inn M5 M6 inp Fig. 4 Reference-current generation circuit [6].

C1
M9
0.8p

VDD Vout

inn M1 M2 inp C2

0.8p

IS1
M3 M4

Fig. 1 Rail-to-rail op-amp [5].

VDD
MR1 MP3a MP3b

VY
VBIAS1
Vinn Vinp
M1 M2
1.1 pF
Fig. 5 Gain (above) and phase margin (below).

IREF
M3 M4 Vout
VDD
M7 M8

1.1 pF

Vinn Vinp
M5 M6
VBIAS2 VX

MN3a MN3b

Fig. 2 Proposed rail-to-rail op-amp with a cross-coupled output stage.

Fig. 6 Voltage difference between the input and output in a voltage-
follower configuration.

139
 Fig. 9 Common-mode rejection ratio (CMRR).

VDD
MR1 MP3
Fig. 7 DC gain and common-mode input voltage.

VBIAS1 VY 1.1 pF
Vinn Vinp
M1 M2

IREF
M3 M4 Vout
VDD
M7 M8

Vinn Vinp
M5 M6
1.1 pF
VBIAS2 VX

Fig. 8 Transconductance and the common-mode input voltage.

MN3

Fig.10 Rail-to-rail op-amp with a common-source output stage.

TABLE I. SUMMARY OF SIMULATION/EXPERIMENTAL RESULTS

[1]* [2]* [3]* [4]* [5]** This work with a This work with a
cross-coupled common-source
output stage** output stage**
Supply voltage [V] 1.0 0.5 0.9 0.5 0.4 0.5 0.5
DC gain [dB] 49 62 79 62 63 101 92
Unity-gain frequency [kHz] 1,300 10,000 5.6 102 5.0 8.2/8.6 8.3
Load capacitance CL [pF] 22 20 12 20 N/A 40/20 5
Phase margin [degree] 57 N/A 62 52 N/A 50/59 49
Supply current [μA] 300 150 0.5 3.0 0.02 0.17 0.057
Power [μW] 300 75 0.45 1.5 0.008 0.085 0.029
CMRR (at DC) [dB] 56** N/A 59 N/A N/A 90 90
Figure of Merit [1/V] 0.10 1.33 0.13 0.68 N/A 1.93/1.01 0.73
*experimental results, **simulation results.

140