Pattern to remove excess metal, leaving wires Meta! Thick field < P substrate Formation of n-well regions Define n MOS and p MOS active areas Field and gate oxidations (thinox) Form and pattern polysilicon p+ diffusion n+ diffusion ee Contact cuts Deposit and pattern metallization Over glass with cuts for bonding pads Figure 5.8 Typical n-well CMOS process steps with corresponding masks required Rigen te hoeVLSI and Chip Design 5-2 ASIC Design and Testing ESI introduction to Wafer to Chip Fabrication Process © Integrated Chip fabrication is a sequential and lengthy process. Various steps involved in IC fabrication process is listed below. 1, Wafer preparation. 2. Oxidation. 3. Diffusion. 4, Ton implantation. seP ° 5. Chemical vapor deposition. yet 6, Metallization. 0¥8 7. Photolithograph' Ee jotolithography stich 8, Packaging. vit EESEE nos Fabrication * nMOS fabrication process involves 9 steps as follows : Step - 1 : Processing is done on a thin film (wafer) of pure silicon crystal. p-impurities stp are introduced as crystal is grown. sind Typically wafer diameter is 75 to 150mm and thickness is 0.4 mm. Impurity is boron having concentrations of 10”/cm? to 10'5/cm? giving resistivity of 25 Q - cm to Bo wens Fig. 5.1.1 Step - 2: A layer of silicon dioxide (SiO,) is grown over the surface of wafer for protection of surface. The thickness of silicon dioxide layer is typically 1 pm This layer acts as barrier to dopants during processing. ap A ie 44am + Py ‘Silicon dioxide tin Pow YY Uj} ee hi Fig. 5.1.2 : Dp Nhsting eps for yer sop 4 ¢ The photoresist yet is exposed to UV light jough a mask. The mask enesponds to regions into stich diffusion is to take place vith transistor channels: Mask Fig. 5.1.4 itp 5 : These regions are then etched together so that the wafer surface is exposed in ‘dow defined by mask Oxide in window <6: The photoresist layer Polysiicon Suins on substrate is removed and a WW %m over the chip surface and then ‘Ysllicon is deposited on it to form “structure. The polysilicon layer ited “by — Chemical oP Fig. 5.4.6 Stim (CVD). Precise control of Js, impurity concentration 4m Shyer of SiO, (0.1 um typical) is A U . h ped polysilicon 2 A) “ted by heavily doped pol Mity is important during fabrication Proe go =.VEo! and wnip Vesign Step-7:The thin oxide is removed to expose areas into which n-type impurities are to be diffused form the source and drain. Diffusion is achieved by heating the wafer to high temperature and passing gas containing the desired n-type impurity (Phosphorus) over the surface. Step - 8 : Thick silicon dioxide (SiO) is grown and then masked with photoresist and then etched to expose specific areas of polysilicon gate, drain and source areas where connections are made (contact holes). Mia nt diffusion (1 um deep) Ee F214 Fig. 5.1.8 Step - 9 : The wafer is then metal deposited over its surface to a thickness of typically 1 um. The metal is usually aluminium. The metal layer is masked and etched to form the required interconnection pattern. Aluminium patterned metallization (1 ym) Fig. 5.1.9 nMOS fabrication process * The fabrication process involves formation or deposition and patterning of three layers isolated by silicon dioxide. The layers are diffused in substrate, polysilicon on oxide (on substrate ) and metal insulated by oxide. In depletion mode devices it is important to introduce a masked ion implementation step between step 5 and step 6. The thick oxide is a mask and is self-aligning.