ELE 2254 MICROCONTROLLERS (E&E)
8051 Microcontroller
8051- pin diagram
Structure of Internal RAM of 8051:
103
Special Function Registers (SFRs) of 8051:
PSW - PROGRAM STATUS WORD Register:
104
TCON - Timer Control (SFR) [Bit-Addressable As TCON.7 to TCON.0]
TMOD - Timer Mode Control (SFR) [NOT Bit-Addressable]
105
ISR - Interrupt Service Routine address
106
DAC 0800 Pin Diagram:
107
ADC 0808/0809 Pin diagram:
LCD Pin Diagram
Commands for LCD:
Code (Hex) Command to LCD
38 2 lines and 5X7 matrix
01 Clear display screen
02 Return home
04 Shift cursor left
06 Shift cursor right
05 Shift display right
07 Shift display left
08 Display off, cursor off
108
0A Display off, cursor on
0C Display on, cursor off
0E Display on, cursor no blinking
80-8F Force cursor to 1st line first position - 16th position
C0-CF Force cursor to 2nd line first position - 16th position
8051 Assembly Instruction Set
Arithmetic Instructions:
Code Description MC
ADD A, #n A A+n 1
ADD A, Rr A A + Rr 1
ADD A, addr A A + [addr] 1
ADD A, @Rp A A + [Rp] 1
ADDC A, #n A A+n+C 1
ADDC A, Rr A A + Rr + C 1
ADDC A, addr A A + [addr] + C 1
ADDC A, @Rp A A + [Rp] + C 1
SUBB A, #n A A-n-C 1
SUBB A, Rr A A - Rr - C 1
SUBB A, addr A A - [addr] - C 1
SUBB A, @Rp A A - [Rp] - C 1
INC A A A+1 1
INC Rr Rr Rr + 1 1
INC addr [addr] [addr] + 1 1
INC @Rp [Rp] [Rp] + 1 1
INC DPTR DPTR DPTR + 1 2
DEC A A A-1 1
DEC Rr Rr Rr -1 1
DEC addr [addr] [addr] - 1 1
DEC @Rp [Rp] [Rp] - 1 1
MUL AB BA A X B (B Higher) 4
DIV AB BA A / B (B Remainder) 4
DA A ADEC ABIN 1
109
Logical Instructions:
Code Description MC
ANL A, #n A A AND n 1
ANL A, Rr A A AND Rr 1
ANL A, addr A A AND [addr] 1
ANL A, @Rp A A AND [Rp] 1
ANL addr, A [addr] [addr] AND A 1
ANL addr, #n [addr] [addr] AND n 2
ORL A, #n A A OR n 1
ORL A, Rr A A OR Rr 1
ORL A, addr A A OR [addr] 1
ORL A, @Rp A A OR [Rp] 1
ORL addr, A [addr] [addr] OR A 1
ORL addr, #n [addr] [addr] OR n 2
XRL A, #n A A X-OR n 1
XRL A, Rr A A X-OR Rr 1
XRL A, addr A A X-OR [addr] 1
XRL A, @Rp A A X-OR [Rp] 1
XRL addr, A [addr] [addr] X-OR A 1
XRL addr, #n [addr] [addr] X-OR n 2
CLR A A 00 1
CPL A A 1
RL A A0 A7 A6 A0 1
RLC A C A7 A6 A0 C 1
RR A A0 A7 A6 A0 1
RRC A C A7 A6 A0 C 1
SWAP A ALN AHN 1
NOP PC PC + 1 1
Data Transfer Instructions:
Code Description MC
MOV A, #n A n 1
MOV A, Rr A Rr 1
MOV A, addr A [addr] 1
110
MOV A, @Rp A [Rp] 1
MOV Rr, A Rr A 1
MOV Rr, #n Rr n 1
MOV Rr, addr Rr [addr] 2
MOV addr, A [addr] A 2
MOV addr, #n [addr] n 2
MOV addr, Rr [addr] Rr 2
MOV addr1, addr2 [addr1] [addr2] 2
MOV addr, @Rp [addr] [Rp] 1
MOV @Rp, A [Rp] A 1
MOV @Rp, #n [Rp] n 1
MOV @Rp, addr [Rp] [addr] 2
MOV DPTR, #nn DPTR nn 2
MOVX A, @Rp A [Rp]^ 2
MOVX A, @DPTR A [DPTR]^ 2
MOVX @Rp, A [Rp]^ A 2
MOVX @DPTR, A [DPTR]^ A 2
MOVC A, @A+DPTR A [A+DPTR] 2
MOVC A, @A+PC A [A+PC] 2
PUSH addr SP SP + 1; [SP] [addr] 2
POP addr [addr] [SP]; SP SP - 1 2
XCH A, Rr A Rr 1
XCH A, addr A [addr] 1
XCH A, @Rp A [Rp] 1
XCHD A, @Rp ALN [Rp]LN 1
Branch Instructions:
Code Description MC
ACALL sadd [SP] PC + 2; PC sadd 2
LCALL ladd [SP] PC + 3; PC ladd 2
CJNE A, add, radd PC + 3 + radd 2
CJNE A, #n, radd PC + 3 + radd 2
CJNE Rr, #n, radd PC + 3 + radd 2
CJNE @Rp, #n, radd PC + 3 + radd 2
111
DJNZ Rr, radd If (Rr- PC + 2 + radd 2
DJNZ add, radd If ([add]- PC + 3 + radd 2
AJMP sadd PC sadd 2
LJMP ladd PC ladd 2
SJMP radd PC PC + 2 + radd 2
JMP @A+DPTR PC A + DPTR 2
JC radd If (C=1); PC PC + 2 + radd 2
JNC radd If (C=0); PC PC + 2 + radd 2
JB b, radd If (b=1); PC PC + 3 + radd 2
JNB b, radd If (b=0); PC PC + 3 + radd 2
JBC b, radd If (b=1); PC PC + 3 + radd; b 0 2
JZ radd If (A=00); PC PC + 2 + radd 2
JNZ radd If (A>00); PC PC + 2 + radd 2
RET PC [SP] 2
RETI PC [SP]; Enable Interrupts 2
Boolean Instructions:
Code Description MC
CLR C C 0 1
CPL C C 1
SETB C C 1 1
CLR b b 0 1
CPL b b 1
SETB b b 1 1
MOV C, b C b 2
MOV b, C b C 2
ANL C, b C C AND b 2
ORL C, b C C OR b 2
ANL C, \ b C C AND (NOT b) 2
ORL C, \b C C OR (NOT b) 2
112
ARM7 Microcontroller
ARM 7 Operating mode:
ARM Register Organization
113
ARM7 CPSR/SPSR/Flag Register:
ARM7 Assembly Instruction Set:
114
Second Operand: Using a Shifted Register
LSL Shifts left by the specified amount (multiplies by powers of two)
LSR Shifts right by the specified amount (divides by powers of two)
ASR Shifts right (divides by powers of two) and preserves the sign bit, for 2's
complement operations.
ROR Similar to an ASR but the bits wrap around as they leave the LSB and appear as the
MSB.
RRX This operation uses the CPSR C flag as a 33rd bit. Rotates right by 1 bit
115
Multiple Byte Load- Store: Any Subset of current bank of registers can be transferred to
memory or Fetched from memory. The base register Rn determines the source or destination
address.
LDM<mode> Rn, {<registers>}
STM<mode> Rn, {<registers>}
116
For Example
LDMIA Rn!, {R1-R3}
N is the Number of Registers to load.
Addressing modes for stack operations
Full ascending (FA): Stack grows up. SP points to the highest address containing a valid item.
Empty ascending (EA): Stack grows up. SP points to the first empty location above stack
Full descending (FD): Stack grows down. SP points to the lowest address containing a valid
data
Empty descending (ED): Stack grows down. SP points to the first location below the stack.
Memory Instructions in Functions
Branch Instructions
117
Branch Conditions
Swap Instructions
118
