DATA BOOK
PACKAGE OUTLINE
LEADFRAME EXAMPLE
4204035
DRAFTER: DATE:
T. LEQUANG 01/08/2016 DIMENSIONS IN MILLIMETERS
DESIGNER: DATE: CODE IDENTITY
NUMBER
CHECKER: DATE: SEMICONDUCTOR OPERATIONS 01295
K. SINCERBOX & V. PAKU 01/08/2016
ENGINEER: DATE:
APPROVED:
D. MELENDEZ
DATE:
01/08/2016
ePOD, DWP0020B / SOIC,
RELEASED:
E. REY
DATE:
01/08/2016
20 PIN, 1.27 MM PITCH
WDM 01/08/2016
SCALE SIZE REV PAGE
TEMPLATE INFO:
EDGE# 4218519
DATE:
03/20/2013 5X A 4218913 A 1 OF 5
PACKAGE OUTLINE
DWP0020B SCALE 1.200
PowerPAD TM SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
10.65
TYP
10.16
A
PIN 1 ID AREA
18X 1.27
20
1
12.95
12.70 2X
NOTE 3
11.43
10
11
0.51
20X
7.59 0.35 0.1 C
B
7.45 0.25 C A B
SEE DETAIL A SEATING PLANE
C
(0.25) TYP
2X
0.13 MAX 2.79
NOTE 4 1.91 EXPOSED
THERMAL PAD
3.81 0.25 2.65
2.81 MAX
GAGE PLANE
1.27 0.15
2X 0.40 0.05
0.86 MAX 0 -8
NOTE 4
DETAIL A
TYPICAL
4218913/A 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Features may not present.
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EXAMPLE BOARD LAYOUT
DWP0020B PowerPAD TM SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
(6.2)
NOTE 8
(2.79) SOLDER MASK
DEFINED PAD
SYMM
20X (2) SEE DETAILS
1
20
20X (0.6)
18X (1.27)
(0.55) (12.95)
SYMM TYP NOTE 8
(3.81)
( 0.2) TYP
(1.1)
VIA
TYP
(R0.05) TYP
10 11
(0.55) TYP (1.1) TYP
METAL COVERED
BY SOLDER MASK (9.4)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK METAL UNDER
SOLDER MASK METAL SOLDER MASK
OPENING OPENING
0.07 MAX 0.07 MIN
AROUND AROUND
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4218913/A 01/2016
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DWP0020B PowerPAD TM SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
(2.79)
20X (2) BASED ON 0.125 THICK STENCIL
1
20
20X (0.6)
18X (1.27)
(3.81)
SYMM BASED ON
0.125 THICK
STENCIL
10 11
SEE TABLE FOR
METAL COVERED SYMM DIFFERENT OPENINGS
BY SOLDER MASK FOR OTHER STENCIL
THICKNESSES
(9.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL SOLDER STENCIL
THICKNESS OPENING
0.1 3.12 X 4.26
0.125 2.79 X 3.81 (SHOWN)
0.15 2.55 X 3.48
0.175 2.36 X 3.22
4218913/A 01/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
REVISIONS
REV DESCRIPTION ECR DATE ENGINEER / DRAFTER
A RELEASE NEW DRAWING 2154188 01/08/2016 D. MELENDEZ / T. LEQUANG
SCALE SIZE REV PAGE
A 4218913 A 5 OF 5
