A 9 pW/Hz Adjustable Clock Generator with

3-Decade Tuning Range for Dynamic Power

Management in Subthreshold SCL Systems
Armin Tajalli and Yusuf Leblebici
Microelectronic Systems Lab. (LSM)
Ecole Polytechnique Fédéral de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
E-mail: {armin.tajalli, yusuf.leblebici}@epfl.ch

Abstract— A widely-tunable and power-scalable clock gen-

erator for ultra-low power (ULP) applications is presented.
Benefitting from a novel self-adjustable loop frequency response,
the proposed phase-locked loop based clock generator exhibits a
tuning range of three decades. Implemented in 0.13 µm CMOS,
the circuit occupies 0.06 mm2 , while its power dissipation is 9
pW/Hz, proportional to the output clock frequency with 350
nW stand-by power. The circuit remains stable with scalable
dynamics for frequency steps (upward and downward) as large
as a factor of ×1024. The presented clock generator has been
designed to be compatible with subthreshold source-coupled
logic (STSCL) topology that can be used for ultra-low power
applications such as in bio-medical systems.

I. I NTRODUCTION
To minimize the energy consumption in ultra-low power
(ULP) systems, it is necessary to control the operating con-
ditions and clock frequency with respect to the work load of
the system [1]- [3]. When the system is in sleep mode, as
illustrated in Fig. 1(a), the clock frequency can be reduced con-
siderably to save energy. The clock frequency will be increased
only if there is any need for higher processing speed. In such
occasions, the clock frequency and the operating conditions
Fig. 1. (a) Dynamic power management by scaling operating conditions
are required to be switched quickly to high performance mode. (bias current) and clock frequency in proportion to the work load. (b) Dynamic
In addition, having scalable power-frequency controlling unit power-frequency scale in an STSCL based digital system. In this topology, the
and clock generator can further improve the overall system power dissipation and speed of operation both are controlled through adjusting
the tail bias current, IC .
power efficiency. Based on this, the main goal of this work has
been to implement an ultra-low-power clock generator with
arbitrary output frequency that can be adjusted over a very
wide range with scalable power-frequency property. Unlike conventional CMOS digital systems where the power
The clock generator presented in this article exhibits a very dissipation is controlled through adjusting the supply voltage,
wide and fast frequency response in which power consumption in STSCL topology the gate delay does not depend on the
is 9 pW/Hz with a standby dissipation of 350 nW. Shown supply voltage. The ability to control the bias current inde-
in Fig. 1(b), the proposed system uses a PLL (phase-locked pendently also allows significant reduction of leakage losses in
loop) to generate the appropriate clock for an ULP digital sleep/idle mode which is a major problem in nanometer CMOS
system based on subthreshold source-coupled logic (STSCL) [5]. In STSCL systems, the power dissipation and the gate
circuit family [4]. Having a very wide tuning range, the power delay can be controlled through the tail bias current as depicted
dissipation of each STSCL block can be reduced down to in Fig. 1(b). Hence there is no need to use complicated supply
about 2 pW/gate in sleep mode with a reduced clock frequency. regulation techniques. A copy of the bias current of the ring
In active mode, the clock frequency of the STSCL system oscillator inside the clock generator is supplied to the STSCL
can be increased rapidly by increasing the bias current of cells of the digital block. This way, gate delay scales in
each cell, e.g. to 500 nA, thereby allowing the scaling of proportion to the delay cells of the ring oscillator, which are
power dissipation of the STSCL circuit block by five orders based on STSCL topology, as well. The STSCL system shown
of magnitude. in Fig. 1(b) is a finite-impulse response filter designed using

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 where KOSC is the oscillator sensitivity factor and is defined
as the variation at the output oscillation frequency divided by
the input controlling signal.
The loop filter should be designed based on jitter and
dynamic performance requirements of the system. In Fig 3,
R1 and C1 create a zero to make the loop stable. The noise
associated with R1 can degrade the phase noise at the output of
oscillator, hence it is recommended to choose a small enough
value for R1 [10]. Meanwhile, C2 is used to reduce the ripples
on controlling signal, VC , and hence reduce the pattern jitter
Fig. 2. Circuit power efficiency with scaling the frequency [6]. [11]. However, the extra phase lag associated with the extra
pole created by C2 will cause some stability issues. The ratio
of b = C1 /C2 needs to be selected very carefully to avoid
instability [10]. To reduce the pattern jitter which is mainly
due to the variations on the controlling signal, VC , the order of
loop filter can be increased even more [10]. The design can be
made based on estimating the loop damping factor [7], [11]:
r
1 1
ζ= · · ICP C KOSC R12 C1 (2)
2 2πN
Fig. 3. Conventional charge-pump PLL (CPLL) topology. where
ωC = 2ζ/(R1 C1 ). (3)
specialized library cells, for an ULP application. After choosing a proper value for ζ, the value of the other
In the rest of this article, we discuss different circuit elements can be derived.
techniques employed to design and implement a very wide To implement a scalable output frequency PLL, it is possible
tuning range clock generator with scalable power-frequency to change the input frequency (fREF ), or the division ratio of
characteristics. the frequency dividers (N and P which are shown in Fig 3).
II. C LOCK G ENERATOR T OPOLOGY Therefore, the effect of changing these three parameters on the
loop dynamic behavior needs to be studied. To achieve a stable
A. Frequency Scalability PLL, it is necessary to properly set the values of ωC and loop
Fig. 2 shows the power dissipation of a conceptual system in zero, | z |= 1/(R1 C1 ) = 1/τ , with respect to the reference
different operating frequencies, fop . At intermediate operating frequency. Finally the bias current of the charge pump circuit
frequencies, the power dissipation is linearly proportional to (CPC) needs to be selected with respect to the input frequency
fop . In this region of operation, power efficiency of the system and also the division ratio.
remains independent to the operating condition. However, as The design process can be started by estimating the value
the frequency approaches to fM AX or reduces toward fmin , of τ with respect to the input reference frequency [10]:
the power efficiency starts to decline due to different reasons √ √
[6], and hence it is not desirable to operate in the two extremes b+1 b+1 1
τ = R1 C 1 = =( · MF ) · (4)
of the tuning range. Thereby, it is very desirable to make the ωC 2π fP
power dissipation of the proposed clock generator linearly where MF = 2πfREF /ωC and b are two constant numbers
proportional to the operating frequency in an as wide as (ωC needs to be smaller than 2πfREF by a factor of MF for
possible range. stability issues). Therefore, τ depends only on fP = fREF /P ,
To implement widely tunable PLL-based clock generators, and not on N . The next step is to calculate the charge-pump
adaptive bandwidth and self-biased topologies have been de- bias current from (2):
veloped [7]-[8]. In this work, we are introducing a PLL with
self-adjustable loop in which the poles and the zero of the N
ICP C ∝ (5)
system are automatically tuned with respect to the oscillation P2
frequency of the ring oscillator, fosc , and the input frequency, which indicates that for constant values of C1 , fREF , and
fREF . This approach helps to control the loop dynamics, and MF , the charge pump bias current needs to be changed
hence the loop bandwidth and jitter performance by frequency proportional to N and inversely proportional to the square
scaling. value of P . Therefore, a CPC with programmable or adjustable
Using continuous-time approximation [9] for the PLL bias current is required. Design of a charge pump circuit with
shown in Fig 3, the open loop gain can be calculated as: a bias current proportional to N/P 2 will be complicated and
ICP C KOSC 1 requires a complex current switching network. A remedy for
T (s) = · LF (s) · · (1) simplifying the circuit topology is to use a current-controlled
2π s N

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oscillator (CCO) instead of a voltage controlled oscillator in
which:
∂IC ∂fOSC
KOSC = · = Gm · KCCO . (6)
∂VC ∂IC
Based on (6), a transconductance, Gm , is inserted into the
loop in order to convert the controlling voltage to controlling
current. In this case, the controlling current is equal to the
fREF
oscillator current: IC = IOSC = N P × KCCO . Therefore, the
controlling current is always proportional to N/P . Based on
this, if we make Gm value proportional to its current, i.e.:
Gm = IC /Vchar , then using (5) and also [10]:
√
4π 3
 
IOSC Vchar C1 b+1
ICP C = × · · · (7)
N VSW CL b ln 2MF2 Nd
where Nd is the number of delay stages in ring oscillator, CL is
the output load capacitance that each STSCL-based delay cell
in ring oscillator observes, and VSW is the voltage swing at
the output of delay elements. As a conclusion, it is sufficient to
make the bias current of the charge pump circuit proportional
to IC /N , as shown it is in Fig 4.
B. Topology
Fig. 4 shows the topology of the proposed PLL. As ex- Fig. 4. Topology of the proposed wide tracking range PLL
plained, a transconductor has been added to the loop in order
to have an extra degree of freedom to keep the loop damping
factor constant over its tuning range. In addition, the pole and Therefore, the PLL circuit not only provides the system clock,
the zero of the loop are required to be scaled with fosc . For but also it controls the bias current, and hence the delay of
this reason, the charge pump circuit, ICP C , is biased with the gates. Unlike CMOS logic circuits where supply voltage
a fraction of IC in order to adjust the pole placement in needs to be adjusted using a DC-DC converter, there is no
proportion to fosc . To have a loop zero in proportion to fosc need for such a block implemented in STSCL, and hence
R1 is implemented using the same load resistance that has the system is more power efficient. The absolute value of the
been used in each STSCL gate (shown in Fig. 1(b)). Using supply voltage of STSCL system and its variation does not
this approach, and with an appropriate ratio between ICP C affect the circuit speed or performance as the core is based on
and IC , the system remains stable with a scalable dynamic differential topologies [4].
behavior for its entire tuning range which can be programmed The critical block in the proposed clock generator shown in
by division ratio inside the loop, N , and also division ratio Fig. 4 is the transconductor which needs to have a transcon-
outside the loop, P . ductance proportional to IC with a very wide output current
swing (Fig. 5). Biased in weak inversion, this circuit uses
C. Power Consumption Scalability a local feedback and replica circuit to control the circuit
To make the circuit power dissipation proportional to the transconductance precisely. M1 in this configuration acts as
operation frequency, and hence minimize it in sleep mode, a current buffer. The resistivity of M2 is controlled by a local
STSCL-based phase-frequency detection (PFD) and dividers loop and is equal to RM 2 = VSW /IC . Based on simulation
[4] have been employed. An appropriate fraction of the results, this circuit can provide an output current between 40
controlling current is used to bias these circuits. As the bias pA to 800 nA with a transconductance proportional to current.
current of the charge-pump circuit is also proportional to IC ,
IV. E XPERIMENTAL AND S IMULATION R ESULTS
the total power dissipation of PLL will become proportional
to IC , and hence to fosc . This property is especially important Fig. 6 shows the simulated transient response of the PLL
to reduce the clock generator power dissipation to only 350 at different operating frequencies. The time scale of the graph
nW in sleep mode. is normalized to the oscillation period. As can be seen, the
transient response of the PLL remains invariant with the
III. C IRCUIT I MPLEMENTATION frequency scaling and hence the ratio of the settling time with
A copy of the critical path of the digital STSCL system respect to the oscillation period remains almost unchanged.
has been used to construct the ring oscillator. In this way, the The proposed clock generator circuit has been implemented
delay of critical path will be always properly controlled with in 0.13 µm CMOS, and occupies 0.06 mm2 active area as
respect to the clock frequency. The controlling current will be shown in Fig. 7. As measurement results in Fig. 8 show, the
copied to all the digital STSCL gates with an appropriate ratio. oscillation frequency can be adjusted from 1 kHz to 3 MHz.

244
 Fig. 7. Chip photomicrograph implemented in 0.13 µm technology (inset
shows the mask layout: 200 µm × 300 µm).

Fig. 5. Widely adjustable transconductor circuit and its measured I/V

characteristics.

Fig. 8. Measured power dissipation versus the output frequency.

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the operating condition of ultra-low power STSCL based
digital systems has been presented. Using current-based PLL
topology, the loop dynamics are controlled to have a stable
system over its wide tuning range. Having a wide tuning
range (×1000), the power dissipation of the circuit is linearly
proportional to the output frequency and the supply voltage
can be reduced down to 0.9 V, while the frequency is scaled
from 1 kHz to 3 MHz.

ACKNOWLEDGMENT
The authors would like to thank Stephane Badel, and Fig. 9. Simulated step response of the PLL in response to a frequency jump
Sylvain Hauser for their valuable contribution in this work. equal to a factor of 1/200 followed by another jump by a factor of 200.

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