INDIAN INSTITUTE OF TECHNOLOGY ROORKEE
Inter - Integrated Circuit (I2C)
Bishnu Prasad Das
Dept of ECE, IIT Roorkee
Content
• What is the I2C Bus and what is it used for?
• Bus characteristics
• I2C Bus Protocol
• Data Format
• Typical I2C devices
• Example device
• Sample pseudo code
What is I2C ?
• The name stands for “Inter - Integrated Circuit Bus”
• A Small Area Network connecting ICs and other
electronic systems
• Originally intended for operation on one
single board / PCB
• Synchronous Serial Signal
• Two wires carry information between
a number of devices
• One wire use for the data
• One wire used for the clock
• Today, a variety of devices are available with I2C
Interfaces
• Microcontroller, EEPROM, Real-Timer, interface chips, LCD
driver, A/D converter
What is I2C used for?
• Data transfer between ICs and systems at
relatively low rates
• “Classic” I2C is rated to 100K bits/second
• “Fast Mode” devices support up to 400K
bits/second
• A “High Speed Mode” is defined for operation up to
3.4M bits/second
• Reduces Board Space and Cost By:
• Allowing use of ICs with fewer pins and smaller
packages
• Greatly reducing interconnect complexity
• Allowing digitally controlled components to be
located close to their point of use
I2C Bus Characteristics
• Includes electrical and timing specifications,
and an associated bus protocol
• Two wire serial data & control bus implemented
with the serial data (SDA) and clock (SCL) lines
• For reliable operation, a third line is required:
Common ground
• Unique start and stop condition
• Slave selection protocol uses a 7-Bit slave address
• The bus specification allows an extension to 10 bits
• Bi-directional data transfer
• Acknowledgement after each transferred byte
• No fixed length of transfer
I2C Bus Characteristics (cont’d)
• True multi-master capability
• Clock synchronization
• Arbitration procedure
• Transmission speeds up to 100KHz
(classic I2C)
• Max. line capacitance of 400pF,
approximately 4 meters (12 feet)
• Allows series resistor for IC protection
• Compatible with different IC technologies
I2C Communication
I2C Bus Definitions
• Master:
• Initiates a transfer by generating
start and stop conditions
• Generates the clock
• Transmits the slave address
• Determines data transfer direction
• Slave:
• Responds only when addressed
• Timing is controlled by the clock line
I2C Bus Configuration Example
Communication in the Bus
Timing Diagram of I2C Protocol
Acknowledgements
• Master/slave receivers pull data line low for one clock
pulse after reception of a byte
• Master receiver leaves data line high after receipt of
the last byte requested
• Slave receiver leaves data line high on the byte
following the last byte it can accept
Transmitter releases SDA
line during 9th clock pulse.
Acknowledgement
from receiver
Acknowledgements
• From Slave to Master Transmitter:
• After address received correctly
• After data byte received correctly
• From Slave to Master Receiver:
• Never (Master Receiver generates ACK)
• From Master Transmitter to Slave:
• Never (Slave generates ACK)
• From Master Receiver to Slave:
• After data byte received correctly
Negative Acknowledge
• Receiver leaves data line high for one clock pulse
after reception of a byte
Transmitter releases SDA
line during 9th clock pulse.
Not acknowledgement
(NACK) from receiver
Negative Acknowledge (Cont’d.)
• From Slave to Master Transmitter:
• After address not received correctly
• After data byte not received correctly
• Slave is not connected to the bus
• From Slave to Master Receiver:
• Never (Master Receiver generates ACK)
• From Master Transmitter to Slave:
• Never (Slave generates ACK)
• From Master Receiver to Slave:
• After last data byte received correctly
Data Transfer on the I2C Bus
• Start Condition
• Slave address + R/W
• Slave acknowledges with ACK
• All data bytes
• Each followed by ACK
• Stop Condition
SDA
ACK from Slave ACK from
Receiver
SCL
Remember : Clock is produced by Master
Start Stop
Data Formats
➢Master writing to a Slave
A A A
Data Format
➢Master reading from a Slave :
Master is Receiver of data and Slave is Transmitter of data.
1
I2C transmission Example1
I2C transmission Example2
I2C Transmission Example3
I2C Synchronization
Clock Synchronization is the procedure that will make the low period equal to the longest
clock low period and high is equal to the shortest one among the masters.
Data arbitration is the procedure the relative priority of the contending masters.
I2C Synchronization (Clock Stretching)
• If the slave is fast enough to capture the data
at maximum rate, then no clock stretching is
needed.
• If the slave is not fast enough to capture the
data at the maximum rate, then it can perform
a operation called clock stretching.
• Clock stretching means slave will hold the
clock low until it is ready.
TM4C I2C
TM4C I2C
Register Initialization
• Enable the I2C clock using the SYSCTL_RCGCI2C_R register
• Enable the clock to the appropriate GPIO module via the
SYSCTL_RCGCGPIO_R register
• Enable the appropriate pins for their alternate function using the
GPIOAFSEL register
• Enable the I2CSDA pin for open-drain operation. See page 676.
The SCL pin must not be configured as an open-drain signal.
• Configure the PMCn fields in the GPIOPCTL register to assign the
I2C signals to the appropriate pins. See page 688 and Table 23-5
on page 1351.
• Initialize the I2C Master by writing the I2CMCR register with a
value of 0x0000.0010
Register Initialization
• Set the desired SCL clock speed of 100 Kbps by writing the
I2CMTPR register with the correct value.
• The value written to the I2CMTPR register represents the number
of system clock periods in one SCL clock period. The TPR value is
determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
I2C Timing
