1734 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO.

6, JUNE 2009

Design of Three-Stage Class-AB 16 Headphone

Driver Capable of Handling Wide Range
of Load Capacitance
Vijay Dhanasekaran, Member, IEEE, Jose Silva-Martinez, Senior Member, IEEE, and
Edgar Sánchez-Sinenco, Fellow, IEEE

Abstract—In this paper, the effect of load capacitance variation

on the location of the closed loop poles of three-stage amplifiers
is analyzed and a frequency compensation scheme that automati-
cally adjusts the damping factor according to the load capacitance
is proposed. A class-AB 16 headphone driver designed using
the proposed scheme in 0.13 m technology can handle 1 pF to
22 nF capacitive load while consuming as low as 1.2 mW of quies-
cent power. It can deliver a peak power of 40 mW (1.6 Vpp swing)
to the load with 84.8 dB THD and 92 dB peak SNR. It occupies
0.1 mm2 area.
Index Terms—Class-AB amplifiers, class-AB drivers, audio
power amplifiers, headphone drivers, multi-stage amplifiers,
capacitive loaded amplifiers.
Fig. 1. 16 driver configuration.

I. INTRODUCTION Since the battery life is an important aspect of the portable

gadgets, driver’s power efficiency has to be maximized. The
UE to rapid growth in mobile entertainment electronics,
D the demand for high-efficiency headphone drivers has
generated a great deal of interest in recent times. Owing to
power efficiency is defined as the ratio of the average
power delivered to the load to the average power dissipated from
the supply. of the class-AB stage can be expressed as (see
electro magnetic interference (EMI) issues with class-D drivers, Appendix A)
class-AB architecture is preferred for headphone applications
[1]. In order to reduce design cycle time and time-to-market, a (1)
versatile driver that can be deployed to a variety of platforms is
desirable. Capacitive loads as large as 20 nF are used in some where is the peak load current, is the quiescent current
platforms for electro static discharge (ESD) protection and and CF is the peak-to-average ratio or the crest factor of the
EMI suppression. Other platforms may use low-capacitance waveform.
Since the CF of a music waveform can be as large as 19 dB
diodes for ESD protection. Also, the end-users typically prefer
[3], significantly affects the of the driver. From (1) it
to use the headphone output as an input for other devices like
can be seen that can be improved if .
desktop speakers, FM transmitters, home theater systems, etc.
Several solutions for low-voltage headphone driver design
Depending on the usage conditions, the cable capacitance can
for portable equipments were recently published. A low-voltage
range from few tens of pF to few 100 pF. Also, a series inductor
two-stage class-AB driver was proposed in [4]. This design
is employed in some platforms that functions as a FM choke. uses a folded-mesh biasing approach described in [5] to achieve
The target driver configuration with possible range of loads is 0.8 V operation. The main drawback of this design is that the
shown in Fig. 1. power delivered to the headphone (peak power of 3.2 mW on
16 load) is inadequate for many cases. In order to minimize
the cross-over distortion without consuming large quiescent
Manuscript received October 28, 2008; revised March 18, 2009. Current ver-
sion published May 28, 2009.
power, an interesting approach that uses an adaptive bias current
V. Dhanasekaran was with the Department of Electrical and Computer En- was proposed in [1]. This technique, however, fails to tackle
gineering, Texas A&M University, College Station, TX 77843 USA. He is now the distortion due to the triode region of operation of the output
with Qualcomm, San Diego, CA 92121 USA (e-mail: dvijay@ece.tamu.edu).
J. Silva-Martinez and E. Sánchez-Sinencio are with the Analog and
transistors, which is typically the dominant source of distortion
Mixed-Signal Center, Department of Electrical and Computer Engi- in low-voltage designs. Another design presented in [6] is based
neering, Texas A&M University, College Station, TX 77843 USA (e-mail: on three-stage nested Miller compensated (NMC) class-AB
jsilva@ece.tamu.edu; sanchez@ece.tamu.edu). amplifier. Since the three-stage amplifier has sufficiently large
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. gain, it achieves a reasonable distortion performance while
Digital Object Identifier 10.1109/JSSC.2009.2020461 delivering adequate power (peak power of 53.5 mW on 16
0018-9200/$25.00 © 2009 IEEE
DHANASEKARAN et al.: DESIGN OF THREE-STAGE CLASS-AB 16 HEADPHONE DRIVER 1735

load). The design also supports wide range of load capacitors

spanning from no load to 12 nF. The drawback of this approach
is that the quiescent power consumption of the amplifier is
quite large (12.5 mW), which is mainly attributed to the NMC
scheme. Some designs use a series resistor at the output to
achieve stability with large capacitive load. However, this
approach is undesirable for power efficiency and peak output
power in case low-voltage, low-power drivers.
A design that achieves stable operation for capacitive loads
ranging from 1 pF to 22 nF with only 1.2 mW of quiescent
power dissipation was presented in brief by the authors [7]. In
this paper, detailed analysis of three-stage amplifiers under large
load variation and evolution of the proposed architecture is pre-
sented. Also, description of a new class-AB bias scheme used
in the driver is provided.
The rest of the paper is organized as follows. An analysis of
the three stage amplifier compensation and its behavior under
large load variation is presented in Section II. A new equivalent
circuit used for this analysis is formally verified in Appendix B.
In Section III, an approximate solution for load invariant
damping based on an intuitive approach is proposed and is
corroborated by simulations. Transistor level implementation
of a 16 driver based on the proposed compensation scheme
is described in Section IV. Experimental results are shown in
Section V and conclusions are drawn in Section VI.

II. BEHAVIOR OF THREE STAGE AMPLIFIERS

UNDER LARGE LOAD VARIATION
Fig. 2. (a) Basic three-stage amplifier with dominant pole on the first stage.
Two stage amplifiers that support a wide range of capacitive (b) Cc1 providing unity feedback around second and third stage. (c) High-fre-
loads have been reported in [8], [9] but so far this capability has quency equivalent circuit.
not been demonstrated in three-stage amplifiers. Several com-
pensation schemes for three-stage amplifiers driving large ca-
pacitance load with power efficiency more than 10 times that provides the unity feedback assuming high output impedance
of the conventional NMC scheme have been reported recently for and ignoring the parasitic capacitance at the output
[10]–[14]. The damping factor control frequency compensation node of . Now, the full circuit can be modeled as an
(DFCFC) presented in [10] has the core idea for reducing power integrator cascaded by * in unity feedback
consumption for large capacitive loads and is also suitable for [see Fig. 2(b)], which yields the equivalent circuit in Fig. 2(c).
low-resistance drivers. The main aim of these compensation This simplified equivalent circuit breaks up the problem of
schemes is to maximize the performance for a single value of three-stage compensation to that of an integrator and a biquad
capacitive load. However, all of these schemes are vulnerable design, which are very well understood. It also provides good
to large peaking in frequency response and potential instability insight and helps understanding of complicated cases without
when the load capacitance is dropped to small values. In order relying on exact transfer functions with several unimportant
to come up with a compensation scheme for a wide range of ca- terms.
pacitive loads, an insightful analysis of the three-stage amplifier The equivalent circuit can be verified using a formal analysis
compensation scheme and the pole locus as a function of capac- (see Appendix B) and the following assumptions. 1) The capac-
itive load is required. itance at the output node of is much smaller compared to
the compensation capacitance . 2) The loading of at the
A. Intuitive Interpretation of Three-Stage Amplifier output is small compared to that of the actual load capacitor at
Compensation and Power Efficiency Improvement in DFCFC the output. 3) The feed-forward current via to the output is
An equivalent circuit of a three-stage amplifier that assists insignificant. Due to low resistance and large capacitance load,
in gaining insight on the behavior of its closed-loop poles is the frequency at which the forward current from the capacitor
presented in this section. A three-stage amplifier configuration dominates the current from to output stage (i.e., the zero
with first stage forming the dominant pole is shown in Fig. 2(a). frequency) is very large. Hence, the effect of the feed-forward
represents the transconductance of the first stage of the path can be safely ignored. Also, note that this equivalent cir-
amplifier. represents the gain of the second stage and cuit is not accurate at very low frequencies due to the ignorance
represents the third stage gain inclusive of the load capacitance. of the output conductance of the gain stages and is intended for
* along with acts like an “active RC” integrator stability analysis and studying high-frequency behavior of the
though the current generator is instead of a resistor. closed loop amplifier.
1736 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009

Note that for a given and , the output stage transcon-

ductance is fixed. This limitation is due to the fact that the
loss bandwidth of the biquad is solely determined by ,
as indicated by (2).
In case of DFCFC biquad, the transfer function contains an
additional pole-zero pair due to the damping network. The root
locus of the overall amplifier is largely independent of this pole-
zero pair and hence its effect can be ignored in this analysis.
The transfer function of the DFCFC biquad at frequencies well
above is thus approximated by

(4)

and are given by

Fig. 3. (a) Second and third stage in unity feedback loop—NMC. (b) Second and , respectively. The conditions for the Butter-
and third stage in unity feedback loop—DFCFC.
worth pole constellation can be verified to be

(5)
The biquad in the equivalent circuit is analyzed for the NMC
and the DFCFC schemes. The biquad formed by the second and
the third stage in the unity feedback loop for both of the cases are (6)
shown in Fig. 3. and represent the transconductance
of the second and third stage, respectively. is the second
Miller compensation capacitance. is the parasitic capaci- An important change enabled by the damping network is that
tance at the input node of the third stage. is the conduc- the loss bandwidth is determined by the independent param-
tance of the damping resistor and is the blocking capacitance eter . This allows the design to trade for
that ensures that the damping resistance does not reduce the gain for a given product shown in (6). Since is the par-
of the amplifier at low frequencies (within signal bandwidth). asitic capacitance of the transistors, it can be several orders of
In case of NMC, the transfer function of the biquad section is magnitude smaller than the largest supported . Hence, for a
given by given numerical value of the ratio, can be realized
with substantially lesser power than . This helps to
keep the power dissipation low and allows the quiescent power
to be dictated by the distortion performance rather than the fre-
quency compensation.

B. Effects of Load Capacitance Variation

Assuming that the three-stage amplifier is designed for But-
(2)
terworth pole constellation for 20 nF and using (2) and
(4), it can be seen that the magnitude of the complex poles of the
biquad increases as is dropped from 20 nF. In case of NMC,
The square root of the product of the poles the quality factor of the complex poles of the biquad is given by
is defined as the pole
magnitude and the sum of the poles is
defined as the “loss bandwidth” of the biquad, (7)
where refers to the quality factor of the biquad poles.
The closed loop poles of a typical amplifier with on-chip Since the quality factor is proportional to , it decreases
load are designed to fall in the Butterworth constellation [15]. as the load capacitance is reduced, eventually resulting in real
It can be shown that the conditions to achieve third order But- poles for the biquad. The pole locus of the overall closed loop
terworth pole constellation for the three-stage amplifier in in- third order system is shown in Fig. 4. The poles move such that
verting unity gain configuration are one real pole goes to high frequency while the other two poles
and , where is the closed loop are complex with magnitude and Q constrained to a narrow
pole magnitude [2]. This translates to the following conditions range. In case of DFCFC, the quality factor of the complex poles
on the bandwidth of the gain stages: of the biquad is given by

(3) (8)
DHANASEKARAN et al.: DESIGN OF THREE-STAGE CLASS-AB 16 HEADPHONE DRIVER 1737

Fig. 4. Pole locus of NMC and DFCFC as the load capacitance is varied from
C to C =100.

Since the quality factor is proportional to , it increases

as the load capacitance is dropped. Dropping from 20 nF to
200 pF, for instance, would increase by 10 times
(from 0.7 to 7). Note that the Q of the closed loop complex poles Fig. 5. (a) Three-stage amplifier with LHP zero resistor. (b) High-frequency
of the DFCFC in Fig. 4 eventually tracks , which follows a equivalent circuit. (c) Feedback factor used in biquad transfer function.
constant bandwidth (const. BW) path as indicated by (4). Thus,
the large resulting from the small load capacitance leads
to an under-damped third order system with large Q complex the closed loop complex poles of the third order system closely
poles. Also note that this effect exists regardless of the assump- follows , it is desirable to have a compensation scheme that
tion of Butterworth pole constellation for 20 nF. has a independent of . This provides a close approxi-
The Butterworth pole constellation yields a phase margin mation to the constant (const. ) path shown in Fig. 4. Hence
of about 60.5 for the open loop amplifier, which is not really the aim of the new compensation scheme is to achieve constant
needed for the headphone driver and can be traded for power (and hence constant ) and be more power efficient than
reduction. Since lower phase margin allows smaller product NMC.
, the power consumption in the As explained in Section II-A, a separate damping network at
second and third stage of the amplifier can be reduced. Further the output of the second stage improves the power efficiency
reduction in power can be achieved by introducing a RC net- over NMC for large . A damping network emulates a series
work in series with [see Fig. 5(a)]. The resistor Rc provides RC network, where the damping resistor provides the neces-
a LHP zero and capacitor C2 helps retain the gain margin for sary loss and the blocking capacitance prevents the from
small . The model for the three-stage amplifier now changes reducing the low-frequency gain. The role of is to provide
to the one shown in Fig. 5(b). The unity feedback around the necessary loss in the biquad so that the of the complex
second and third stage is modified to a feedback with a factor poles can be fixed to a desired value. From (8), it can be seen
as shown in Fig. 5(c) (see Appendix B for the derivation). that can be made independent of if the resistor
The exact pole locus as a function of load capacitance for a in Fig. 3(b) is replaced with a resistor that is proportional to
45 phase margin design with the RC network is presented in .
Section III. Due to the obvious difficulties in realizing the square root de-
pendence using linear circuits, a piece-wise approach is taken
in the proposed scheme. Fig. 6 shows the architecture of the
III. PROPOSED LOAD-CAPACITANCE-AWARE
proposed amplifier. The damping circuit formed by ,
COMPENSATION SCHEME
and emulates a damping resistance of and
In the previous section, it was shown that the DFCFC scheme an equivalent blocking capacitance of
could result in unstable system if the capacitive load is reduced. . Furthermore, provides the necessary small damping
From (4) and (8), it was predicted that becomes large when resistance in case of small , namely,
the load capacitance is dropped to small values. In other words, . It also provides a series blocking capacitance
the damping factor of the complex poles of , where is the output conductance of third
the DFCFC biquad is proportional to , which makes the stage. At high frequencies, the impedance is dominated by the
system under-damped for small load capacitance. Since the of damping resistors, which governs the of the complex poles.
1738 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009

Fig. 6. Architecture of the proposed compensation scheme.

Fig. 8. Pole locus for 45 phase margin cases as the load capacitance is varied
from C to C =100.

range of and roughly retains a constant factor. Due to the

piece-wise approximation of the proportional-to-square-root re-
sistor, the proposed structure shows a small acceptable deviation
from the constant case. Fig. 9 shows a family of Bode plots
from simulations with various values of ranging from
Fig. 7. Piecewise approximation for proportional-to-square-root resistor. to for the proposed scheme. Note that the proposed
scheme exhibits gracious frequency response for a wide range
of load capacitance. Process Monte Carlo stability simulations
The quality factor of the complex poles of the biquad in this new were performed on the transistor level implementation and the
scheme is approximated by phase and gain margin histograms are shown in Fig. 10 for load
capacitances of 20 nF and 200 pF. The histograms show that the
compensation scheme is robust to process variations.
(9)
IV. IMPLEMENTATION OF THE PROPOSED 16 DRIVER
The main concept in the proposed scheme can be better The transistor level implementation of the 16 driver using
understood with the aid of Fig. 7. It illustrates that the parallel the proposed architecture is shown in Fig. 11. The design con-
combination of (constant resistance) and (propor- siderations of each of the stages are given below.
tional-to- resistance) provides a reasonable approximation
A. First Stage (Gm1)
of the desired proportional-to- resistor. For large value
of the , provides the necessary damping and for , the input stage, is realized using the folded cascode
small values of , the equivalent resistor seen through transconductor formed by M9–M14. The input transistors M13
provides adequate damping. For intermediate values of , are carefully sized and matched to minimize the offset voltage
both the damping resistances ( and ) contribute to the and noise. The highest noise contribution of a PMOS-
loss. Due to the approximation, the small and large region input folded cascode amplifier comes from the NMOS current
would be somewhat over-damped and the intermediate region source transistors (M9). Resistors are used to minimize the
is somewhat under-damped. It is worth noting that is much noise contribution of M9. The bias voltages , , and
smaller than the second Miller capacitor used by NMC. This is are generated using standard low-voltage cascode bias gen-
the case since is meant to provide damping for small erators while is generated by a simple diode connected
conditions in the proposed scheme whereas the second Miller transistor. The bias currents of M13 and M12 are made equal
capacitance in the NMC scheme needs to provide damping to ensure equal slew rate for positive and negative transitions.
even for the largest .
The pole locus as a function of load capacitance is shown B. Second Stage (Gm2)
in Fig. 8 for the case of 45 phase margin design. As the load Transistors M7, M7’, and M8 realize the amplifier’s second
capacitance is dropped, the poles of the DFCFC amplifier are stage . This is implemented as “positive stage” in order
pushed to the RHP plane, yielding unstable systems. The pro- to ensure negative feedback around second and third stage. The
posed architecture provides necessary damping across a wide transconductance of M8 is augmented by a current mirror gain
DHANASEKARAN et al.: DESIGN OF THREE-STAGE CLASS-AB 16 HEADPHONE DRIVER 1739

Fig. 9. Simulated Bode plots of proposed scheme as load capacitance is varied from C to C =1e4.

of 2 in M7, M7’. The output current of the second stage is at frequencies much higher than that. Thus, the pro-
pumped into the floating current mirror formed by M3 and M4. posed circuit provides a damping network with a resistance
These floating current mirrors, described in [16], provide the of in series with an equivalent capacitance of
necessary biasing for the class-AB output stage. .

C. Proposed Damping Stage (GmD) D. Output Stage (Gm3)

Due to large swings associated with the class-AB output Fig. 13 shows the schematic of the output stage. In order to
stage, the damping network is split such that M5 and M6 realize avoid a large DC blocking capacitor at the output, dual supply
for the NMOS and the PMOS path respectively. M6 also is used. The class-AB output stage and the level shifters (LS)
serves as a bias current source for . The gate of M5/M6 is are operated from a 1 V supply while the rest of the amplifier
biased using the resistor and the drain node is connected uses 0.6 V supply.
directly to the output. This enables the circuit to work In order to prevent oxide breakdown in the gate-drain overlap
under large swing conditions without pushing M5/M6 into region, cascoding is employed. When the output swings close
triode region. The damping circuit used in [10] is meant for an to VDDD (VSSD), the output voltage is effectively shared be-
amplifier with predominantly capacitive load and it relies on tween the VDS of the main transistor M1 (M2) and cascode tran-
the assumption that the voltage swings at node (in Fig. 6) sistor M1c (M2c). The cascode transistors (M1c, M2c) are bi-
is small. This assumption is not valid for low-resistance drivers ased such that the VDS of the output transistors are maintained
with class-AB output where the input swing of the output to be 1.2 V under all swing conditions. The NMOS output de-
stage is intentionally kept large for power efficiency vices are in triple well, which allows their sources and bodies
reasons. Hence, a damping network that works under large to be 0.4 V below the substrate voltage. The level shifters are
swing conditions is desirable. The proposed circuit, shown in implemented using source followers. The NMOS level shifter
Fig. 12, serves this purpose. The impedance of the proposed also makes use of triple well transistors to handle voltage levels
damping circuit is given by below the substrate potential.

E. Class-AB Bias Generation Circuit

The NMOS part of the class-AB bias generation circuit is
illustrated in Fig. 14. The straightforward approach to generate
(10) the bias voltage is to pump current into three diode con-
nected copy-transistors with sizes proportional to transistors
where is the transconductance of the OTA, M1, Mls, and M3 connected in series (similar to the biasing
is the output conductance of the OTA and scheme in [16]). This, however, results in extremely large
is the conductance of the resistor used to bias the OTA. mirroring error. The main source of the error arises due to
can be approximated as a capacitor of value mismatch in the drain voltages of the main transistors M1,
at frequencies well below and as a resistor of value Mlsb, and M3 and their corresponding copy-transistors in the
1740 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009

Fig. 10. Process Monte Carlo histograms for phase and gain margins.

Fig. 11. Transistor level schematic of the proposed 16 driver.

bias circuit. This mismatch results in different channel length by diode connecting the copy transistor M1b and M3b via level
modulation and drain induced barrier lowering experienced shifters formed by Mlsb, Ib2 and M3b’, Ib3, respectively. In
by these transistors (especially for M1 since it uses minimum case of M3b, the size of M3b’ and Ib3 is designed so that the
length). drain voltage of M3b matches that of M3. For M1b, the drain
The proposed bias generation circuit takes into account the voltage is set by the sum of of M1b and that of Mlsb, which
drain voltage of the output transistors M1 and M2 as well as was close to the drain voltage of M1 in this design. With this
the mirror transistors M3 and M4 (in Fig. 11). This is achieved technique, the mirroring error is substantially reduced.
DHANASEKARAN et al.: DESIGN OF THREE-STAGE CLASS-AB 16 HEADPHONE DRIVER 1741

Fig. 12. Proposed damping network.

Fig. 15. Micrograph of the test chip.

Fig. 13. Schematic of the output stage of the driver.

Fig. 16. Pulse response as load capacitance is varied from 8 pF to 22 nF.

confirms the automatic damping control across a wide range of

load capacitors. The minimum capacitance in the test setup is
limited to 8 pF by the probe capacitance. However, simulations
confirm that there is no peaking/ringing behavior even in the
case of 1 pF load. The slew rate is limited by the second stage
to 0.4 V/ S, which is more than what is required by a full-scale
20 kHz signal. When fast changing input is applied, the second
stage output momentarily charges in the opposite direction be-
fore returning to slewing state. This effect produces some cross
over distortion for fast changing input and is more prominent
Fig. 14. NMOS part of class-AB bias generation circuit. for smaller load capacitance. This, however, is not an issue for
signals in audio frequency range.
Fig. 17 shows the measured FFT of 1.4 Vpp, 1 kHz sine-wave
V. EXPERIMENTAL RESULTS output and the noise floor with zero input condition under 1 nF
The driver prototype was fabricated in UMC 130 nm CMOS capacitor load in both cases. A maximum THD of 84.8 dB and
technology and packaged in a SOIC20 package. The die photo- a maximum unweighted SNR of 92 dB in 20 Hz–20 kHz band-
graph with markings of essential circuit components is shown width was measured with 1.6 Vpp 1 kHz tone. Since the head-
in Fig. 15. The output stage is placed as close to the bond-pad phone outputs are always single-ended, dominant second har-
as possible. The power supply and the ground lines of the monic distortion is inevitable. Higher harmonics are observed
output stage are double bonded to minimize parasitic resis- due to small cross-over distortion in the class-AB stage that is
tance. The total layout area occupied by the driver is 0.1 mm unsuppressed by the loop gain.
(350 m 290 m). Fig. 18 shows the THD+N as a function of output signal am-
The pulse responses of the driver measured for various load plitude for a 1 kHz tone and as a function of frequency for
capacitors are shown in Fig. 16. Absence of ringing in all cases 1.4 Vpp amplitude under 1 nF capacitor load in both cases.
1742 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009

TABLE I
COMPARISON OF MEASUREMENT RESULTS WITH STATE-OF-THE-ART

VI. CONCLUSION
A 16 headphone driver design that can handle 1 pF–22 nF
of load capacitance was demonstrated. A simple and intuitive
method to analyze three-stage amplifiers was described and a
load capacitance aware compensation scheme was introduced.
Experimental result shows that the proposed driver has signif-
icant power efficiency improvement over the state-of-the-art.
Since the design uses only the 1.2 V core devices, it may be
easily ported to a smaller feature size technology.

APPENDIX A
The power efficiency of the class-AB stage is defined
Fig. 17. Spectrum of 1 kHz tone and noise. as the ratio of the average power delivered to the load to
the average power dissipated from the supplies . With
the simplifying assumption of rail-to-rail output voltage swing,
the is given by

(A.1)

where is the peak output voltage, is the quiescent current,

is the load resistance and is the crest factor of the wave-
form. The first term of represents the signal dependant
power dissipation, which is a product of supply voltage (posi-
tive and negative) of the class-AB stage and the average
load current . The second term represents the
power due to the quiescent current used to bias the class-AB
stage.
Fig. 18. THD+N across output amplitudes and load capacitances. Since is the RMS output voltage, is given by

For small output amplitude cases, THD+N are limited by the (A.2)
noise and hence the decreasing trend. As expected, the THD+N
If the peak current delivered to the load is represented by
measurements did not show any appreciable change with load
can be expressed as
capacitance variation. The output stage and the bias generation
loop consume a quiescent current of 400 A from 1 V supply (A.3)
while the rest of the amplifier consumes 330 A from 0.65 V
supply, which is intended to be the same supply as the core
analog supply. APPENDIX B
Some recent headphone driver designs are compared with the Formal Verification of the Proposed Equivalent Circuit: Con-
presented work in Table I. The quiescent power of the proposed sider the general representation of a feedback gain stage driven
driver is about 1/10th of that reported in [6] and [17]. A figure of by a current source as shown in Fig. 19(a). Using node analysis,
merit (FOM) defined as a ratio of the peak power delivered to the following expressions can be written:
load to the quiescent power is included in the table. The total
compensation capacitors used is less than half of that in [6],
which translates to reduced area. (B.1)
DHANASEKARAN et al.: DESIGN OF THREE-STAGE CLASS-AB 16 HEADPHONE DRIVER 1743

ACKNOWLEDGMENT
The authors thank Madhu Parameswaran of Texas Instru-
ments for driver specs and UMC for chip fabrication.

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Based on (B.4) and (B.5), Fig. 19(a) can be redrawn as shown pp. 1026–1034, Dec. 1986.
in Fig. 19(b). This circuit can be modified to a node scaled ver- [17] “80 mW, Direct Drive Stereo Headphone Driver with Shutdown, Rev.
sion in Fig. 19(c) by reducing the gain term to 2,” Maxim, Oct. 2002 [Online]. Available: http://datasheets.maxim-ic.
com/en/ds/MAX4410.pdf, accessed on Jun. 28, 2008.
and increasing the voltage at to .
The second step is achieved by simply replacing the admittance
with . Vijay Dhanasekaran (M’00) received B.E. degree
There are two admittance components at the output node in electronics and communication engineering from
in Fig. 19(b). The component is manifestation of the P.S.G. College of Technology, Coimbatore, India, in
1999 and the Ph.D. degree in electrical engineering
feedforward current produced by the voltage at on . from Texas A&M University, College Station, TX, in
Due to the assumption of insignificant feedforward current in 2008.
the concerned frequency range, this component can be dropped. He is currently working as a Senior Engineer at
Qualcomm, San Diego, CA. He was with Broadband
The remaining component of the admittance can be merged Silicon Technology Center, Texas Instruments, Ban-
with the load or simply ignored if it is substantially smaller than galore, India between 2000 and 2003. His current
the load admittance. Also, note that leads to the research interest is in low-power audio drivers and
time-to-digital-based ADCs for nanoscale CMOS technologies.
unity feedback case . Hence the equivalent circuits pre- Dr. Dhanasekaran holds four U.S. patents and authored or co-authored several
sented in Figs. 2 and 5 are formally verified. referred journal papers.
1744 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009

Jose Silva-Martinez (SM’98) was born in Teca- Edgar Sánchez-Sinencio (F’92) was born in
machalco, Puebla, México. He received the M.Sc. Mexico City, Mexico. He received the degree in
degree from the Instituto Nacional de Astrofísica communications and electronic engineering (Pro-
Optica y Electrónica (INAOE), Puebla, México, in fessional degree) from the National Polytechnic
1981, and the Ph.D. degree from the Katholieke Institute of Mexico, Mexico City, the M.S.E.E.
Univesiteit Leuven, Leuven, Belgium, in 1992. degree from Stanford University, Stanford, CA, and
From 1981 to 1983, he was with the Electrical the Ph.D. degree from the University of Illinois
Engineering Department, INAOE, where he was at Urbana-Champaign, in 1966, 1970, and 1973,
involved with switched-capacitor circuit design. In respectively.
1983, he joined the Department of Electrical Engi- He is currently the TI J. Kilby Chair Professor and
neering, Universidad Autónoma de Puebla, where Director of the Analog and Mixed-Signal Center at
he remained until 1993; He pioneered the graduate program on Opto-Elec- Texas A&M University, College Station, TX. His present research interests are
tronics in 1992. In 1993, he rejoined the Electronics Department, INAOE, and in the area of power management, RF communication and biomedical circuits
from 1995 to 1998, was the Head of the Electronics Department. He was a and analog and mixed-mode circuit design.
co-founder of the Ph.D. program on Electronics in 1993. He is currently with Dr. Sánchez-Sinencio is the former Editor-in-Chief of IEEE TRANSACTIONS
the Department of Electrical and Computer Engineering (Analog and Mixed ON CIRCUITS AND SYSTEMS, PART II. In November 1995, he was awarded an
Signal Center), Texas A&M University, College Station, TX, where he is an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics
Associate Professor. His current field of research is in the design and fabrication and Electronics, Mexico. This degree was the first honorary degree awarded
of integrated circuits for communication and biomedical application. for microelectronic circuit design contributions. He is co-recipient of the 1995
Dr. Silva-Martínez has served as IEEE Circuits and Systems Society Guillemin-Cauer Award for his work on cellular networks. He was also the
Vice President Region 9 (1997–1998), and as an Associate Editor for IEEE co-recipient of the 1997 Darlington Award for his work on high-frequency
TRANSACTIONS ON CIRCUITS AND SYSTEMS (TCAS), PART II from 1997 to filters. He received the IEEE Circuits and Systems Society (CASS) Golden
1998 and 2002 to 2003, and Associate Editor of IEEE TCAS PART I from Jubilee Medal in 1999. He recently received the IEEE CASS 2008 Tech-
2004 to 2005 and 2007 to the present, and as a member of the editorial boards nical Achievement Award. He was the IEEE CASS Representative to the
of five other journals. He was the inaugural holder of the TI Professorship-I Solid-State Circuits Society from 2000 to 2002. He was a member of the
in Analog Engineering, Texas A&M University (2002–2008). Among other IEEE Solid-State Circuits Society Fellow Award Committee from 2002 to
recognitions, he is the recipient of the 2005 Outstanding Professor Award 2004. He is a former IEEE CASS Vice President–Publications. His website is
by the ECE Department, Texas A&M University, co-author of the paper that http://amesp02.tamu.edu/~sanchez.
received the 2003 Best Student Paper Award in RF-IC and co-recipient of the
1990 European Solid-State Circuits Conference Best Paper Award. His website
is http://amesp02.tamu.edu/~jsilva.