Laptop Chip Level Repair Guide 35

Chapter 4
The Common Concepts of
Laptop and Noun
Explanation

About laptop mainboard maintenance it is often involving some professional

terminologies of the circuit and signal. To understand the schematic circuit
diagram and learn to repair well we must understand these concepts first.

4.1: Power Supply and Signal

On the mainboard, some places have 5V voltage, we called 5V power supply.
And some places also have 5V voltage, we called signal, so what's the
difference between them?

1. Power Supply
Power supply is an output current of the voltage and current is large. During
working, the voltage cannot be set higher or lower. If the power supply is low,
it's short circuit. In general, set high is not allowed.

The power supply is providing the power to the devices, it's marking name as:
VCC, VDD, VCC3, VDDQ, VTT, VBAT, 5VALW, +3VO or etc.

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The circuit symbol of power supply is shown in figure 4-1.

Figure 4-1: The circuit symbol of power supply

In the circuit diagram of Apple products, the power supply us generally

beginning with PP and haven't other special symbol as shown in 4-2

Figure 4-2: Apple product circuit symbol of power supply

The Grounding is to form a loop for power supply. Without grounding, it is no

current will flow through the devices. The marking names are VSS and GND.

The circuit symbol of grounding is shown in figure 4-3.

Figure 4-3: The circuit symbol of grounding

2. Signal
In theory, the voltage signal only considers the voltage change and current is
low. In the working process of the mainboard, it can be set higher or lower at
any time according to the needs. The arrow of signal in the circuit diagram
below is not representing the flow of signal completely. It is because of the
schematic diagram designer when drawing the circuit in unprofessional skill.

The circuit diagram of signal is shown in figure 4-4.

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Figure 4-4: The circuit diagram of signal

4.2: High Level and Low Level

In the digital logic circuit, the low level is represented by "0", and the high level
is represented by "1". The high and low level in the circuit needs to be decided
by the circuit, not to be limited to a certain value. But in general, 0V is low level
and 3.3V is high level.

4.3: Jump and Pulse

From high level jump to a low level also called the falling edge, shown in figure 4-
5.

Figure 4-5: The falling edge waveform

From low level jump to low then jump to high also called rising edge, as shown in
figure 4-6.

Figure 4-6: The rising edge waveform

From high jump to low then jump to high also called high-low-high pulse
waveform is as shown in figure 4-7.

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Figure 4-7: The high-low-high pulse waveform

4.4: The Clock Signal

The clock signal CLK (CLOCK) is to provide a benchmark for the digital
circuit work, so that each connected device unified work pace. The basic unit of
the clock is Hz (Hertz). There is a main clock generating circuit on the
mainboard. The function of this circuit is to provide the clock for all devices on
the mainboard. For different devices, the clock circuit will send different
frequency, such as to the frequency of CPU is more than 100Mhz, to PCI device
is 33MHz, to PCI-E device is 100MHZ , to USB controller (integrated in the
South Bridge internal) is 48 Mhz. But the two connected devices must have the
same clock frequency and voltage to communicate. For example, memory and
North Bridge need the same clock and voltage to transmit signal normally. After
main board powering on normal and also the clock chip work normal, then the
clock signal can be measured correctly. We can use the oscilloscope or
multimeter to measure the clock signal.

The clock signal of clock chip benchmark- 14MHz is shown in figure 4-8.

Figure 4-8: The clock signal of clock chip benchmark- 14MHz

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4.5: Reset Signal

The literal meaning of reset signal (RST) is a restart/new signal. When power
on laptop, it will reset automatically and jump from low level to high level;
during normal operation, press the reset button, it will from high level to jump
to the low level then back to high level. For example, for PCI, from 3.3V to
jump to 0V, after that to 3.3V, that's mean it is a normal reset jump. Reset
signal is generally expressed as ***RST#, such as PCIRST#, CPURST#,
IDERST# and so on.

In short, the reset can only be momentary low level, but when the mainboard
works normally, the reset is high level. We said not reset usually refers to no
reset voltage, which is the measurement point voltage of the reset signal is 0V.

The 3.3V platform reset from the South Bridge, after dividing into 1.1V as the
CPU reset, shown in figure 4-9.

Figure 4-9: The circuit of the CPU reset

4.6: The Power Good Signal

The power good signal PG (POWERGOOD) is used to describe the normal
power supply is usually active high. For example, after sending the CPU voltage
normally, then the CPU power supply chip can send PG signal. The common
abbreviations of PG signal are PD, PWRGD, POK, PWRG, VTTPWRGD,
CPUPWRGD and so on.

For example the RT8205 chip, when it is working normally, then it will send
SPOK, is shown in figure 4-10.

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Figure 4-10: PG signal diagram

4.7: Open Signal (or Start-up Signal)

Some chip called it as EN (Enable), the high level represents the open signal.
But some chip called SHDN#, namely SHUTDOWN, "#" represents active -
low level. It means that signal is closed when it's low level. So to open it or
laptop mainboard power on, it must be high level.

We need to emphasize that we must be combined to full name in English of

signal to understand signal with "#" (when active-low level), some signal with
"#", when it's low level the mainboard can work normally. For example, signal
VR-PWRGD-CK410# in figure 4-11, sending the low level to open the clock
chip after power supply is normal.

But some signal with "#", the mainboard working normally must be high. For
example 1999_SHDN# shown in figure 4-12 is the low level control signal for
closing MAX1999.

Figure 4-11:VR_PWRGD signal Figure 4-12: 1999_SHDN signal

Timing is through EN, PG and other signals to achieve control.

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4.8: Chip Select Signal

CS is the Chip Select short form. When many of the chips on the same bus, then it
is need a signal to distinguish data and address on bus managed by which chip.
So we need a chip select signal to control it. Chip Select signal is common in
BIOS chip with symbol CS#, and "#" represents active-low level. It's sent by
CPU, from the North Bridge to the South Bridge and finally reaches to the
BIOS. It exist or not, which can initially judge whether the North Bridge, South
Bridge and CPU to work or not. And also whether BIOS information is
destroyed SPI BIOS pin shown in figure 4-13 and pin-1 CS# is the BIOS chip
select signal.

Figure 4-13: SPI BIOS pins

4.9: The Explanation of Common Signal

Name/Symbol for Laptop Mainboard
Manufacturers

4.9.1 Wistron
Some of common signals names about Wistron Laptop Mainboard shown in
table 4-1.

Signal Names/Symbols Description

AD+ The first voltage that the power
adapter converts.

DCBATOUT Common point

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+3VL 3.3V linear power supply, supply

voltage to EC.

DCIN Power supply input for charging chip.

ACIN Power adapter detection input for

charging chip.

ACAV-IN Power adapter detection output for

charging chip.

PWR-S5-EN A control signal used to open standby

voltage of South Bridge.

+5VALM, +3VALM The standby power supply of South

Bridge

AD_IN# , AC_IN# The power adapter detection signal to

EC, the low level represents that the
adapter is inserted.

KBC-PWR-BTN# Press the on/off switch to produce the

trigger signal to EC.

LID_CLOSE# Close cover switch

CLK_EN# After CPU power supply being

normal, send the low level that can be
used to open the clock.

G792-RST# The high level s4end by the

temperature control chip when the
temperature is normal.

CK-PWRGD After the South Bridge receiving

VRMPWRGD, sent this signal as high
level for opening the clock.

Table 4-1 The list of some common signal names/symbols about Wistron

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4.9.2 Quanta
Some of common signals names/symbols about Quanta Mainboard shown in
table 4-2.

Signal Names/Symbols Description

VIN The common point voltage

ACIN, ACOK Power Adapter detection

3V_AL, 5V_AL, VL 3V, 5V Linear power supply

+3VPCU, +5VPCU EC Standby power supply

3V_S5 The voltage under the condition of S5;

The South Bridge power supply;
Opened by EC after Trigger switch.

+3VSUS, +5VSUS The voltage under the condition of S3;

Memory power supply; Sent by EC
and opened by SUSON.

NBSWON# Trigger signal for power on; Press the

power on key to produce high-low-
high signal to EC.

DNBSWON# EC sent high-low-high effective

trigger signal to the South Bridge
PWRBTN#.

SLP_S3#, SLP_S4# ACPI controller signal sent by the

South Bridge is used to opening
voltage when the power is turned on,
and it also used to shutting off voltage
when the power is turned off.

S5_ON The opening signal of the South

Bridge standby voltage sent by EC; Its
use to convert the PCU to voltage S5.

SUSON After EC receiving SLP_S5# from the

South Bridge, then producing S3

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voltage opening signal.

MAINON After EC receiving SLP_S3# from the

South Bridge, after that producing S3
voltage opening signal.

VR_ON The CPU core voltage opening signal

sent by EC.

HWPG By the PG Logic and all power supply

except the CPU core power supply.

PWROK_EC After EC received high level HWPG

signal, delay producing the
PWROK_EC signal.

DELAY_VR_PWG CPU core voltage power-good signal.

VR-PWRGD-CK410# CPU core voltage power managed the

clock open signal from chip; Active
low level.
CK_PWRGD The South Bridge sent CL-PWRGD
open clock chip after receiving
VRMPWRGD.

CPUPWRGD In the South Bridge internal, PWROK

pin and VRMPWRGD pin signal
through the logic generated
CPUPWRGD.

PLTRST# The platform reset signal; After the

South Bridge sending CPUPWRGD
signal, through the delay buffer sent
PLTRST#.

PCIRST# The PCI reset; Used for resetting the

device on the PCI bus when powered
on; Making the device work from an
initial state.

CPURST# CPU reset signal; The North Bridge

sent CPURST# to CPU after received

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PLTRST#.

BL/C# Represents high level, low battery

(only for battery mode).

D/C# Inverse relationship with ACIN (Just

for mainboard with D/C# signal, where
the mainboard is without BL/C#
signal).

Table 4-2 The List of some common signal names/symbols about Quanta
Mainboard

4.9.3 ASUS
Some of common signals names/symbols ASUS Laptop Mainboard shown in
table 4-3.

Signal Names/Symbols Description

AC_BAT_SYS The common point voltage

ACIN Power adapter detection

+5VAO 5V linear voltage

+3VAO 3V linear voltage

+5VA +5VAO renamed to +5VA after

jumper.

+3VA +3VAO renamed to +3VA after

jumper JP8101.

+3VA_EC +3VA renamed to +3VA_EC after

through the inductance; As the EC
standby power supply.

+5VO 5V standby voltage in S5dormant

state.

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+3VO 3V standby voltage in S5dormant

state.

+5VSUS +5VO renamed to +5VSUS after

jumper.

+3VSUS +3VO renamed to +3VSUS after

jumper.

VSUS_ON SUS voltage open signal.

SUS_PWRGD SUS voltage power-good signal; Send

to EC.

PM_RSMRST# The reset signal of the South Bridge

ACPI controller; Can be understood
that the South Bridge standby voltage
is normal when received this signal.

PWRSW_EC# Laptop boot-up trigger signal.

PM_PWRBTN# After receiving PWRSW_EC, EC sent

PM_PWRBTN# effective trigger to
the South Bridge PWRBTN# pin.

SUSC_ON, SUSC_PWR S3 voltage open signal.

SUSB_ON, SUSB#_PWR S0 voltage open signal.

ALL_SYSTEM_PWRGD Generated by memory power supply,

Bridge power supply, bus power
supply, graphics card power supply
and PG signal logic.

CPU_VRON EC delayed 99ms to send VR_ON

after sending SUSB_ON; For opening
CPU core voltage.

EC_CLK_EN EC sent VRMPWRGD to the South

Bridge pin to inform the South Bridge
that CPU core voltage is normal.

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CLK_PWRGD The South Bridge generated

CLK_PWRGD to IC clock after
receiving VRMPWRGD; For opening
the clock signal.

PM_PWROK After receiving

ALL_SYSTEM_PWRGD, EC delayed
sending PW_PWROK.

H_CPURST# The North Bridge sent H_CPURST#

to CPU after receiving PLTRST#
signal.

GATE_PWR_SW# The booth trigger signal.

LID_SW# Close-lid sleep switch signal; When

the machine is closed, this signal is
low level.

LID_KBC# The close-lid sleep switch detection

signal for EC.

KBCRSM The keyboard wake-up signal.

FORCE_OFF# The forced shutdown signal;

Generated by the under voltage
protection circuit.

HW_PROTECT# CPU over temperature protection

signal.

OTP_RESET# CPU over temperature indication

signal.

Table 4-3 The List of some common signal names/symbols about ASUS Laptop
Mainboard

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4.9.4 Compal
Some of common signal names about Compal shown in table 4-4.

Signal Names/Symbols Description

B+ Common point voltage.

PACIN The detection output signal is inserted

to the adapter; The high level
represents that the adapter is inserted.

VL 5V linear power supply.

+3VALW, +5VALW Inserting the adapter, that is the

opened voltage.

ON/OFFBTN# Press power on key signal.

ON/OFF# The trigger signal sent by boot trigger

circuit to EC.

PBTNOUT# The boot trigger signal sent by EC to

the South Bridge.

SYSON S3 voltage open signal.

SUSP# S0 voltage open signal.

+VCCP The working voltage of CPU front side

bus; This voltage distributes in CPU,
the North Bridge, and the South
Bridge.

+CPU_CORE CPU core voltage.

VGATE CPU core voltage power-good signal.

ICH_POK PWROS for the South Bridge; Inform

the South Bridge system voltage
power good.

BCLK The front side bus clock signal.

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SUS_STAT# Sent by the South Bridge; The low

level indicates that the system will be
in power-down (save power) mode.

Table 4-4 The list of some common signal names/symbols about Compal

4.9.5 DELL
Some of common signal names about Dell shown in table 4-5.

Signal Names/Symbols Description

RTC_CELL The mainboard button battery voltage.

+DC_IN Power Adapter voltage input.

+PWR_SRC The common point voltage.

ALWON EC sent a ALWON signal to the

system power supply chip to
open/start-up the system power supply.

THERM_STP# Overheat protection signal; Active-low

level.

ACAV_IN The Power Adapter detection signal.

POWER_SW# A low voltage signal generated by the

power switch or keyboard and EC chip
receives this boot signal.

SUS_ON After receiving the trigger signal, EC

sent SUS_ON to use to open the South
Bridge standby power supply and
memory main power supply.

RUN_ON EC sent open S0 state voltage.

GFX_ON Open discrete graphics card power

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supply.

_VCC_GFX_CORE The discrete graphic card core power

supply.

+0.9V_DDR_VTTP Memory VTT power supply.

RUNPWROK The PGD signal of all RUN power

convergence to this signal.

SUSPWROK The reset signal of all SUS power

brings together to generate the
SUSPWROK signal.

+VCCP_1P05VP The front side bus power supply:

1.05V.

PGD_IN One of the conditions of that CPU

power supply chip sent CLK_EN#,
PGOOD and others.

CLK_ENABLE# The open signal of clock chip: Active-

low level.

H_PWRGOOD PGD reset signal sent by the South

Bridge to CPU.

H_RESET# The North Bridge sent CPU reset

signal.

+VCHGR Charging output voltage.

+SBATT Auxiliary/Sub battery power supply

terminal.

+PBATT Main battery power supply terminal.

SBAT_PRES# Detection of insert the auxiliary

battery.

PBAT_PRES# Detection of insert main battery.

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IMVP_VR_ON Open CPU power supply.

IMVP_PWRGD Power supply good signal sent by CPU

power supply chip.

Table 4-5 The list of some common signal names/symbols about Dell

4.9.6 Apple
Some of common signal names about Apple shown in table 4-6.

Signal Names/Symbols Description

=PP3V42_G3H_REG 3.42V power supply in the condition
of G3 equivalent to the linear power
supply of other machine.

=PP3V3_S5_REG 3.3V power supply in the condition of

S5 provided the standby voltage to the
South Bridge and others.

PP3V3_G3_SB_RTC 3.3V power supply of the South

Bridge RTC circuit.

=PPBUSA_G3H Common point voltage.

PM_BATLOW_L The indicator signal of low battery

voltage; Active-low level.

1V8S3_RUNSS S3 state voltage (memory supply) of

1.8V open signal.

ALL_SYS_PWRGD Convergence from all power supply

good signal except CPU power supply.

VR_PWRGOOD_DELAY The power good signal sent by CPU

power supply after generating CPU
voltage normally and it will delay to
send the power-good.

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VR_PWRGD_CK505_L The lower level signal of open clock;

After CPU power supply chip
generating CPU voltage normally, it
will send the low level signal to open
clock.

SMC_BC_ACOK The Adapter detection signal; Active -

high level.

SMC_ADAPTER_EN The high-level signal output by SMC

after receiving the adapter detection
signal.

SMC_BATT_CHG_EN The charging enable signal sent by

SMC; Active-high level.

ACPRN Low level ACPRN signal sent by

charging chip after the adapter is
detected.

ONEWIRE_EN ONEWIRE enable signal; For the

adapter to identify circuit (the power
connector LED green light).

Table 4-6 The list of some common signal names/symbols about Apple

4.9.7 Inventec
Some of common signal names about Inventec shown in table 4-7.

Signal Names/Symbols Description

+VADP Power adapter voltage.

ADP_EN# Power adapter enable signal; Active

low level.

ADP_PRES Adapter detection output voltage; It

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can be use to open the system power

supply directly.

+VBATR Common point voltage.

+3VAL, +5VAL Linear power supply.

PWR_SWIN_3# The signal sent by trigger switch to EC

chip.

KBC_PW_ON The power signal; It is sent by EC after

EC receiving trigger switch; It is use to
open the system standby power supply
under the battery mode (backup
battery).

VCCI_POR#3 The initial reset signal of EC.

+V3A, +V5A Power supply of standby system.

LIMIT_SIGNAL The power adapter connector

intermediate pin; Power identification
signal.

OCP Over-current protection.

Table 4-7 The list of some common signal names/symbols about Inventec

4.9.8 ThinkPad (IBM)

Some of common signal names about ThinkPad (IBM) show in table 4-8.

Signal Names/Symbols Description

DOCK_PWR20_F The power adapter voltage.

CV20 The voltage between adapter and

common point.

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VINT20 The common point.

DISCHARGE Forced to close adapter; Battery

discharge signal.

-PWRSHUTDOWN Over-Temperature and Under-voltage

protection signal; Use to isolate the
adapter.

VCC3SW 3.3V voltage; Output by TB chip; Pull-

up -PWRSHUTDOWN; To supply
power to the Lenovo chip.

-EXTPWR The adapter detection signal; Output

by charging chip; Active low level.

-EXTPWR_ASIC The adapter detection input signal of

the Lenovo chip.

-EXTPWR_H8 The adapter detection input signal of

H8S.

VL5 The 5V linear voltage; Generated by

the standby chip.

DCIN_DRV The spacer tube use to control the

adapter; Fully turn-on the adapter
spacer tube at high level.

BAT_DRV The spacer tube uses to control the

battery; Isolated the battery in a low
level. Turn-on the battery at high level.

M1_ON The high level signal of standby

voltage sent by Lenovo chip for
opening the South Bridge.

VCC5M 5V standby voltage of the South

Bridge.

VCC3M 3.3V standby voltage of the South

Bridge; It is also the power supply of

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H8S.

TH_DET Multiple Thermistors connected in

series; Detect temperature; When the
temperature is normal, this pin is lower
than 0.5V.

ACDET The adapter of the charging chip

detects input pin.

SWPWRG The standby voltage power good

signal of the Lenovo chip.

VREGIN20 The voltage with a small current

generated after the adapter or battery
accessing to or connected; The power
supply of TB chip.

BAT_VOLT VREGIN20 voltage detection pin; The

threshold voltage is 2.9V.

MPWRG After TB chip detected VCC3M,

VCC5M voltages are normal, sent the
PG signal to South Bridge RSMRST#.

-H8-RESET The reset signal sent by Lenovo chip

to H8S.

VDD15 After TB chip detects M voltage is

normal, bootstrap boost 15V; To
provide power to xx_DRV of TB chip
output.

VCPIN28 After TB chip detects M voltage is

normal, bootstrap boost 28V (is 25V in
fact); Use to driving and protecting the
isolating circuit with N-channel FET.

A_ON A voltage is turned on (S3 voltage,

such as memory power supply).

B_ON B voltage is turned on (S0 voltage,

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such as the bus power supply).

B_DRV B voltage drive signal; Sent by TB

chip.

BPWRG Power-good signal; Sent by TB chip

after detecting VCC3B, CVCC5B
normal.

AMT_ON ME module voltage is turned on.

SLP_M# Sent by the South Bridge; Use to

control the opening of AMT power
supply.

AMTPWRG AMT power-good.

-PWRSWITCH, -PWRSW Power switch signal.

BATMON_EN Battery voltage monitoring enable.

M_BATVOLT Main battery voltage feedback.

M1_DRV, M2_DRV Main battery charging and discharging

driving signal.

BAT_CRG Battery large current charge control

switch.

CHARGE_OUT12 12.6V charging voltage control output

by charging chip.

M_TRCL The main battery trickle charging

control switch.

S_TRCL The auxiliary/sub battery trickle

charging control switch.

Table 4-8 The list of some common signal names/symbols about ThinkPad
(IBM)

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