ADS7830

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8-Bit, 8-Channel Sampling

ANALOG-TO-DIGITAL CONVERTER
with I2C™ Interface
Check for Samples: ADS7830

1FEATURES APPLICATIONS
•
23 70kHz SAMPLING RATE • VOLTAGE-SUPPLY MONITORING
• ±0.5LSB INL/DNL • ISOLATED DATA ACQUISITION
• 8 BITS NO MISSING CODES • TRANSDUCER INTERFACE
• 4 DIFFERENTIAL/8 SINGLE-ENDED INPUTS • BATTERY-OPERATED SYSTEMS
• 2.7V TO 5V OPERATION • REMOTE DATA ACQUISITION
• BUILT-IN 2.5V REFERENCE/BUFFER
• SUPPORTS ALL THREE I2C MODES: DESCRIPTION
Standard, Fast, and High-Speed The ADS7830 is a single-supply, low-power, 8-bit
data acquisition device that features a serial I2C
• LOW POWER: interface and an 8-channel multiplexer. The Analog-
180μW (Standard Mode) to-Digital (A/D) converter features a sample-and-hold
300μW (Fast Mode) amplifier and internal, asynchronous clock. The
675μW (High-Speed Mode) combination of an I2C serial, 2-wire interface and
• DIRECT PIN COMPATIBLE WITH ADS7828 micropower consumption makes the ADS7830 ideal
for applications requiring the A/D converter to be
• TSSOP-16 PACKAGE
close to the input source in remote locations and for
applications requiring isolation. The ADS7830 is
available in a TSSOP-16 package.

CH0
SAR
CH1
CH2
CH3
8-Channel
CH4
MUX
CH5
SDA
CH6
SCL
CH7 CDAC Serial
COM Interface
A0
S/H Amp Comparator A1

2.5V VREF
REFIN/REFOUT
Buffer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
2 I C is a trademark of NXP Semiconductors.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS7830

SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

MAXIMUM
INTEGRAL SPECIFIED
LINEARITY ERROR PACKAGE TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY
ADS7830IPWT Tape and Reel, 250
ADS7830I ±0.5 TSSOP-16 PW –40°C to +125°C
ADS7830IPWR Tape and Reel, 2500

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

VALUE UNIT
+VDD to GND –0.3 to +6 V
Digital Input Voltage to GND –0.3 to +VDD + 0.3 V
Operating Temperature Range –40 to +125 °C
Storage Temperature Range –65 to +150 °C
Junction Temperature (TJ max) +150 °C
TSSOP Package
Power Dissipation (TJ max – TA)/θJA
θJA Thermal Impedance 240 °C/W

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.

PIN CONFIGURATION PIN DESCRIPTIONS

PIN NAME DESCRIPTION
1 CH0 Analog Input Channel 0
PW PACKAGE
TSSOP-16 2 CH1 Analog Input Channel 1
(Top View) 3 CH2 Analog Input Channel 2
4 CH3 Analog Input Channel 3
CH0 1 16 +VDD 5 CH4 Analog Input Channel 4

CH1 2 15 SDA 6 CH5 Analog Input Channel 5

7 CH6 Analog Input Channel 6
CH2 3 14 SCL
8 CH7 Analog Input Channel 7
CH3 4 13 A1 9 GND Analog Ground
CH4 5 12 A0 REFIN /
10 Internal +2.5V Reference, External Reference Input
REFOUT
CH5 6 11 COM 11 COM Common to Analog Input Channel
CH6 7 10 REFIN / REFOUT 12 A0 Slave Address Bit 0
13 A1 Slave Address Bit 1
CH7 8 9 GND
14 SCL Serial Clock
15 SDA Serial Data
16 +VDD Power Supply, 3.3V Nominal

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ELECTRICAL CHARACTERISTICS: +2.7V

At TA = –40°C to +125°C, +VDD = +2.7V, VREF = +2.5V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-Scale Input Scan Positive Input – Negative Input 0 VREF V
Positive Input –0.2 +VDD + 0.2 V
Absolute Input Range
Negative Input –0.2 +0.2 V
Capacitance 25 pF
Leakage Current ±1 µA
SYSTEM PERFORMANCE
No Missing Codes 8 Bits
Integral Linearity Error ±0.1 ±0.5 LSB (1)
Differential Linearity Error ±0.1 ±0.5 LSB
Offset Error +0.5 +1 LSB
Offset Error Match ±0.05 ±0.25 LSB
Gain Error ±0.1 ±0.5 LSB
Gain Error Match ±0.05 ±0.25 LSB
Noise 100 µVRMS
Power-Supply Rejection 72 dB
SAMPLING DYNAMICS
High-Speed Mode: SCL = 3.4MHz 70 kSPS (2)
Throughput Frequency Fast Mode: SCL = 400kHz 10 kSPS
Standard Mode, SCL = 100kHz 2.5 kSPS
Conversion Time 5 µs
AC ACCURACY
Total Harmonic Distortion VIN = 2.5VPP at 1kHz –72 dB (3)
Signal-to-Ratio VIN = 2.5VPP at 1kHz 50 dB
Signal-to-(Noise+Distortion) Ratio VIN = 2.5VPP at 1kHz 49 dB
Spurious-Free Dynamic Range VIN = 2.5VPP at 1kHz 68 dB
Isolation Channel-to-Channel 90 dB
VOLTAGE REFERENCE OUTPUT
TA = –40°C to +85°C 2.48 2.52 V
Range
TA = –40°C to +125°C 2.47 2.53 V
TA = –40°C to +85°C 15 ppm/°C
Internal Reference Drift
TA = –40°C to +125°C 40 ppm/°C
Internal Reference ON 110 Ω
Output Impedance
Internal Reference OFF 1 GΩ
Internal Reference ON,
Quiescent Current 850 µA
SCL and SDA pulled HIGH
VOLTAGE REFERENCE INPUT
Range 0.05 VDD V
Resistance 1 GΩ
Current Drain High-Speed Mode: SCL= 3.4MHz 20 µA

(1) LSB means least significant bit. When VREF = 2.5V, 1LSB is 9.8mV.
(2) kSPS means kilo samples-per-second.
(3) THD measured out to the 9th-harmonic.

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ELECTRICAL CHARACTERISTICS: +2.7V (continued)

At TA = –40°C to +125°C, +VDD = +2.7V, VREF = +2.5V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic Family CMOS
VIH +VDD × 0.7 +VDD + 0.5 V
Logic Levels VIL –0.3 +VDD × 0.3 V
VOL Minimum 3mA Sink Current 0.4 V
IIH VIH = +VDD + 0.5V 10 µA
Input Leakage
IIL VIL = –0.3V –10 µA
Data Format Straight Binary
ADS7830 HARDWARE ADDRESS (10010 Binary)
Power-Supply Requirements
Power-Supply Voltage, +VDD Specified Performance 2.7 3.6 V
High-Speed Mode: SCL = 3.4MHz 225 320 µA
Quiescent Current Fast Mode: SCL = 400kHz 100 µA
Standard Mode, SCL = 100kHz 60 µA
High-Speed Mode: SCL = 3.4MHz 675 1000 µW
Power Dissipation Fast Mode: SCL = 400kHz 300 µW
Standard Mode, SCL = 100kHz 180 µW
Power-Down Mode High-Speed Mode: SCL = 3.4MHz 70 µA
Fast Mode: SCL = 400kHz 25 µA
Power-Down Mode with Wrong Address Selected
Standard Mode, SCL = 100kHz 6 µA
Full Power-Down SCL Pulled HIGH, SDA Pulled HIGH 400 3000 nA
TEMPERATURE RANGE
Specified Performance –40 +125 °C

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ELECTRICAL CHARACTERISTICS: +5V

At TA = –40°C to +125°C, +VDD = +5.0V, VREF = External +5.0V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode),
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-Scale Input Scan Positive Input – Negative Input 0 VREF V
Positive Input –0.2 +VDD + 0.2 V
Absolute Input Range
Negative Input –0.2 +0.2 V
Capacitance 25 pF
Leakage Current ±1 µA
SYSTEM PERFORMANCE
No Missing Codes 8 Bits
Integral Linearity Error ±0.1 ±0.5 LSB (1)
Differential Linearity Error ±0.1 ±0.5 LSB
Offset Error +0.5 +1 LSB
Offset Error Match ±0.05 ±0.25 LSB
Gain Error ±0.1 ±0.5 LSB
Gain Error Match ±0.05 ±0.25 LSB
Noise 100 µVRMS
Power-Supply Rejection 72 dB
SAMPLING DYNAMICS
High-Speed Mode: SCL = 3.4MHz 70 kSPS (2)
Throughput Frequency Fast Mode: SCL = 400kHz 10 kSPS
Standard Mode, SCL = 100kHz 2.5 kSPS
Conversion Time 5 µs
AC ACCURACY
Total Harmonic Distortion VIN = 5VPP at 1kHz –72 dB (3)
Signal-to-Ratio VIN = 5VPP at 1kHz 50 dB
Signal-to-(Noise+Distortion) Ratio VIN = 5VPP at 1kHz 49 dB
Spurious-Free Dynamic Range VIN = 5VPP at 1kHz 68 dB
Isolation Channel-to-Channel 90 dB
VOLTAGE REFERENCE OUTPUT
TA = –40°C to +85°C 2.48 2.52 V
Range
TA = –40°C to +125°C 2.47 2.53 V
TA = –40°C to +85°C 15 ppm/°C
Internal Reference Drift
TA = –40°C to +125°C 40 ppm/°C
Internal Reference ON 110 Ω
Output Impedance
Internal Reference OFF 1 GΩ
Internal Reference ON,
Quiescent Current 1300 µA
SCL and SDA pulled HIGH
VOLTAGE REFERENCE INPUT
Range 0.05 VDD V
Resistance 1 GΩ
Current Drain High-Speed Mode: SCL= 3.4MHz 20 µA

(1) LSB means least significant bit. When VREF = 2.5V, 1LSB is 9.8mV.
(2) kSPS means kilo samples-per-second.
(3) THD measured out to the 9th-harmonic.

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ELECTRICAL CHARACTERISTICS: +5V (continued)

At TA = –40°C to +125°C, +VDD = +5.0V, VREF = External +5.0V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode),
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic Family CMOS
VIH +VDD × 0.7 +VDD + 0.5 V
Logic Levels VIL –0.3 +VDD × 0.3 V
VOL Minimum 3mA Sink Current 0.4 V
IIH VIH = +VDD + 0.5V 10 µA
Input Leakage
IIL VIL = –0.3V –10 µA
Data Format Straight Binary
ADS7830 HARDWARE ADDRESS (10010 Binary)
Power-Supply Requirements
Power-Supply Voltage, +VDD Specified Performance 4.75 5 5.25 V
High-Speed Mode: SCL = 3.4MHz 750 1000 µA
Quiescent Current Fast Mode: SCL = 400kHz 300 µA
Standard Mode, SCL = 100kHz 150 µA
High-Speed Mode: SCL = 3.4MHz 3.75 5 mW
Power Dissipation Fast Mode: SCL = 400kHz 1.5 mW
Standard Mode, SCL = 100kHz 0.75 mW
Power-Down Mode High-Speed Mode: SCL = 3.4MHz 400 µA
Fast Mode: SCL = 400kHz 150 µA
Power-Down Mode with Wrong Address Selected
Standard Mode, SCL = 100kHz 35 µA
Full Power-Down SCL Pulled HIGH, SDA Pulled HIGH 400 3000 nA
TEMPERATURE RANGE
Specified Performance –40 +125 °C

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TIMING DIAGRAM

SDA

tBUF

tLOW
tR tF tHD; STA tSP

SCL

tHD; STA

tSU; STA tSU; STO

tHD; DAT tHIGH tSU; DAT

STOP START REPEATED
START

TIMING CHARACTERISTICS (1)

At TA = –40°C to +125°C and +VDD = +2.7V, unless otherwise noted.
PARAMETER SYMBOL CONDITIONS MIN MAX UNIT
Standard Mode 100 kHz
Fast Mode 400 kHz
SCL Clock Frequency fSCL
High-Speed Mode, CB = 100pF max 3.4 MHz
High-Speed Mode, CB = 400pF max 1.7 MHz
Bus Free Time Between a STOP Standard Mode 4.7 µs
tBUF
and START Condition Fast Mode 1.3 µs
Standard Mode 4.0 µs
Hold Time (Repeated) START
tHD; STA Fast Mode 600 ns
Condition
High-Speed Mode 160 ns
Standard Mode 4.7 µs
Fast Mode 1.3 µs
LOW Period of the SCL Clock tLOW
High-Speed Mode, CB = 100pF max (2) 160 ns
High-Speed Mode, CB = 400pF max (2) 320 ns
Standard Mode 4.0 µs
Fast Mode 600 ns
HIGH Period of the SCL Clock tHIGH
High-Speed Mode, CB = 100pF max (2) 60 ns
High-Speed Mode, CB = 400pF max (2) 120 ns
Standard Mode 4.7 µs
Setup Time for a Repeated
tSU; STA Fast Mode 600 ns
START Condition
High-Speed Mode 160 ns
Standard Mode 250 ns
Data Setup Time tSU; DAT Fast Mode 100 ns
High-Speed Mode 10 ns

(1) All values referred to VIHMIN and VILMAX levels.

(2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.

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TIMING CHARACTERISTICS(1) (continued)

At TA = –40°C to +125°C and +VDD = +2.7V, unless otherwise noted.
PARAMETER SYMBOL CONDITIONS MIN MAX UNIT
Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
Data Hold Time tHD; DAT
High-Speed Mode, CB = 100pF max (3) 0 (4) 70 ns
High-Speed Mode, CB = 400pF max (3) 0 (4) 150 ns
Standard Mode 1000 ns
Fast Mode 20 + 0.1CB 300 ns
Rise Time of SCL Signal tRCL
High-Speed Mode, CB = 100pF max (3) 10 40 ns
(3)
High-Speed Mode, CB = 400pF max 20 80 ns
Standard Mode 1000 ns
Rise Time of SCL Signal After a Fast Mode 20 + 0.1CB 300 ns
Repeated START Condition and tRCL1 (3)
After an Acknowledge Bit High-Speed Mode, CB = 100pF max 10 80 ns
High-Speed Mode, CB = 400pF max (3) 20 160 ns
Standard Mode 300 ns
Fast Mode 20 + 0.1CB 300 ns
Fall Time of SCL Signal tFCL (3)
High-Speed Mode, CB = 100pF max 10 40 ns
High-Speed Mode, CB = 400pF max (3) 20 80 ns
Standard Mode 1000 ns
Fast Mode 20 + 0.1CB 300 ns
Rise Time of SDA Signal tRDA
High-Speed Mode, CB = 100pF max (3) 10 80 ns
High-Speed Mode, CB = 400pF max (3) 20 160 ns
Standard Mode 300 ns
Fast Mode 20 + 0.1CB 300 ns
Fall Time of SDA Signal tFDA
High-Speed Mode, CB = 100pF max (3) 10 80 ns
High-Speed Mode, CB = 400pF max (3) 20 160 ns
Standard Mode 4.0 µs
Setup Time for STOP Condition tSU; STO Fast Mode 600 ns
High-Speed Mode 160 ns
Capacitive Load for SDA and
CB 400 pF
SCL Line
Fast Mode 50 ns
Pulse Width of Spike Suppressed tSP
High-Speed Mode 10 ns
Standard Mode 0.2VDD V
Noise Margin at the HIGH Level
for Each Connected Device VNH Fast Mode 0.2VDD V
(Including Hysteresis)
High-Speed Mode 0.2VDD V
Standard Mode 0.1VDD V
Noise Margin at the LOW Level
for Each Connected Device VNL Fast Mode 0.1VDD V
(Including Hysteresis)
High-Speed Mode 0.1VDD V

(3) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(4) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

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TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +2.7V, VREF = External +2.5V, and fSAMPLE = 50kHz, unless otherwise noted.

INTEGRAL LINEARITY ERROR vs CODE

FFT vs FREQUENCY (2.5V Internal Reference)
0 0.5
0.4
-20 0.3
0.2
Amplitude (dB)

0.1

ILE (LSB)
-40
0
-60 -0.1
-0.2
-80 -0.3
-0.4
-100 -0.5
0 10 20 25 0 64 128 192 255
Frequency (kHz) Output Code
Figure 1. Figure 2.

DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs CODE

(2.5V Internal Reference) (2.5V External Reference)
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
ILE (LSB)
ILE (LSB)

0 0
-0.1 -0.1
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0 64 128 192 255 0 64 128 192 255
Output Code Output Code
Figure 3. Figure 4.

DIFFERENTIAL LINEARITY ERROR vs CODE

(2.5V External Reference) CHANGE IN OFFSET vs TEMPERATURE
0.5 0.10
0.4
0.3
Delta from 25°C (LSB)

0.05
0.2
0.1
ILE (LSB)

0 0
-0.1
-0.2
-0.05
-0.3
-0.4
-0.5 -0.10
0 64 128 192 255 -50 -25 0 25 50 75 100
Output Code Temperature (°C)
Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VDD = +2.7V, VREF = External +2.5V, and fSAMPLE = 50kHz, unless otherwise noted.
CHANGE IN GAIN vs TEMPERATURE INTERNAL REFERENCE vs TEMPERATURE
0.10 2.51875

2.51250
Delta from 25°C (LSB)

0.05

Internal Reference (V)

2.50625

0 2.50000

2.49375
-0.05
2.48750

-0.10 2.48125
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
Figure 7. Figure 8.

POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE
750 400

600 350
Supply Current (mA)
Supply Current (nA)

450 300

300 250

150 200

0 150

-150 100
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)
Figure 9. Figure 10.

SUPPLY CURRENT vs I2C BUS RATE INTERNAL VREF vs TURN-ON TIME

300 100

250 No Cap
80 1mF Cap
(37ms)
(930ms)
Supply Current (mA)

8-Bit Settling
Internal VREF (%)

200 8-Bit Settling

60
150
40
100

20
50

0 0
10 100 1k 10k 0 200 400 600 800 1000 1200 1400
2
I C Bus Rate (KHz) Turn-On Time (ms)
Figure 11. Figure 12.

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THEORY OF OPERATION
REFERENCE
The ADS7830 is a classic Successive Approximation
Register (SAR) A/D converter. The architecture is The ADS7830 can operate with an internal 2.5V
based on capacitive redistribution which inherently reference or an external reference. If a +5V supply is
includes a sampleand- hold function. The converter is used, an external +5V reference is required in order
fabricated on a 0.6µ CMOS process. to provide full dynamic range for a 0V to +VDD analog
input. This external reference can be as low as
The ADS7830 core is controlled by an internally 50mV. When using a +2.7V supply, the internal +2.5V
generated free-running clock. When the ADS7830 is reference will provide full dynamic range for a 0V to
not performing conversions or being addressed, it +VDD analog input.
keeps the A/D converter core powered off, and the
internal clock does not operate. As the reference voltage is reduced, the analog
voltage weight of each digital output code is reduced.
The simplified diagram of input and output for the This is often referred to as the LSB (least significant
ADS7830 is shown in Figure 13. bit) size and is equal to the reference voltage divided
by 256. This means that any offset or gain error
ANALOG INPUT inherent in the A/D converter will appear to increase,
When the converter enters the hold mode, the in terms of LSB size, as the reference voltage is
voltage on the selected CHx pin is captured on the reduced.
internal capacitor array. The input current on the The noise inherent in the converter will also appear to
analog inputs depends on the conversion rate of the increase with lower LSB size. With a 2.5V reference,
device. During the sample period, the source must the internal noise of the converter typically contributes
charge the internal sampling capacitor (typically only 0.02LSB peak-to-peak of potential error to the
25pF). After the capacitor has been fully charged, output code. When the external reference is 50mV,
there is no further input current. The amount of the potential error contribution from the internal noise
charge transfer from the analog source to the will be 50 times larger—1LSB. The errors due to the
converter is a function of conversion rate. internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.

+2.7V to +3.6V

5W

+ 1mF to
10mF

2kW 2kW
REFIN/ VDD
0.1mF REFOUT + 1mF to
10mF

CH0 SDA Microcontroller

CH1 SCL
CH2 ADS7830 A0
CH3 A1
CH4 GND
CH5
CH6
CH7
COM

Figure 13. Simplified I/O of the ADS7830

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DIGITAL INTERFACE A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
The ADS7830 supports the I2C serial bus and data way that the SDA line is stable LOW during the HIGH
transmission protocol, in all three defined modes: period of the acknowledge clock pulse. Of course,
standard, fast, and high-speed. A device that sends setup and hold times must be taken into account. A
data onto the bus is defined as a transmitter, and a master must signal an end of data to the slave by not
device receiving data as a receiver. The device that generating an acknowledge bit on the last byte that
controls the message is called a “master.” The has been clocked out of the slave. In this case, the
devices that are controlled by the master are “slaves.” slave must leave the data line HIGH to enable the
The bus must be controlled by a master device that master to generate the STOP condition.
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP Figure 14 details how data transfer is accomplished
conditions. The ADS7830 operates as a slave on the on the I2C bus. Depending upon the state of the R/W
I2C bus. Connections to the bus are made via the bit, two types of data transfer are possible:
open-drain I/O lines SDA and SCL. 1. Data transfer from a master transmitter to a
The following bus protocol has been defined (as slave receiver. The first byte transmitted by the
shown in Figure 14): master is the slave address. Next follows a
number of data bytes. The slave returns an
• Data transfer may be initiated only when the bus
acknowledge bit after the slave address and each
is not busy.
received byte.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes 2. Data transfer from a slave transmitter to a
in the data line while the clock line is HIGH will be master receiver. The first byte, the slave
interpreted as control signals. address, is transmitted by the master. The slave
then returns an acknowledge bit. Next, a number
Accordingly, the following bus conditions have been of data bytes are transmitted by the slave to the
defined: master. The master returns an acknowledge bit
after all received bytes other than the last byte. At
Bus Not Busy: Both data and clock lines remain
the end of the last received byte, a not-
HIGH.
acknowledge is returned.
Start Data Transfer: A change in the state of the
The master device generates all of the serial clock
data line, from HIGH to LOW, while the clock is
pulses and the START and STOP conditions. A
HIGH, defines a START condition.
transfer is ended with a STOP condition or a
Stop Data Transfer: A change in the state of the repeated START condition. Since a repeated START
data line, from LOW to HIGH, while the clock line is condition is also the beginning of the next serial
HIGH, defines the STOP condition. transfer, the bus will not be released.
Data Valid: The state of the data line represents valid The ADS7830 may operate in the following two
data, when, after a START condition, the data line is modes:
stable for the duration of the HIGH period of the clock • Slave Receiver Mode: Serial data and clock are
signal. There is one clock pulse per bit of data. received through SDA and SCL. After each byte is
Each data transfer is initiated with a START condition received, an acknowledge bit is transmitted.
and terminated with a STOP condition. The number START and STOP conditions are recognized as
of data bytes transferred between START and STOP the beginning and end of a serial transfer.
conditions is not limited and is determined by the Address recognition is performed by hardware
master device. The information is transferred byte- after reception of the slave address and direction
wise and each receiver acknowledges with a ninth-bit. bit.
• Slave Transmitter Mode: The first byte (the slave
Within the I2C bus specifications a standard mode address) is received and handled as in the slave
(100kHz clock rate), a fast mode (400kHz clock rate), receiver mode. However, in this mode the
and a highspeed mode (3.4MHz clock rate) are direction bit will indicate that the transfer direction
defined. The ADS7830 works in all three modes. is reversed. Serial data is transmitted on SDA by
Acknowledge: Each receiving device, when the ADS7830 while the serial clock is input on
addressed, is obliged to generate an acknowledge SCL. START and STOP conditions are
after the reception of each byte. The master device recognized as the beginning and end of a serial
must generate an extra clock pulse that is associated transfer.
with this acknowledge bit.

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 ADS7830

www.ti.com SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012

SDA

MSB
Slave Address R/W
Direction Acknowledgement
Bit Signal from
Receiver
Acknowledgement
Signal from
Receiver

SCL 1 2 6 7 8 9 1 2 3-8 8 9
ACK ACK

START Repeated If More Bytes Are Transferred STOP Condition

Condition or Repeated
START Condition

Figure 14. Basic Operation of the ADS7830

Address Byte Command Byte

MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB
1 0 0 1 0 A1 A0 R/W SD C2 C1 C0 PD1 PD0 X X

The address byte is the first byte received following The ADS7830 operating mode is determined by a
the START condition from the master device. The command byte which is illustrated above.
first five bits (MSBs) of the slave address are factory
SD: Single-Ended/Differential Inputs
pre-set to 10010. The next two bits of the address
byte are the device select bits, A1 and A0. Input pins 0: Differential Inputs
(A1-A0) on the ADS7830 determine these two bits of 1: Single-Ended Inputs
the device address for a particular ADS7830. A
C2 - C0: Channel Selections
maximum of four devices with the same pre-set code
can therefore be connected on the same bus at one PD1: Power-Down
time. 0: Power-Down Selection
The A1-A0 Address Inputs can be connected to VDD X: Unused
or digital ground. The device address is set by the
See Table 1 for a power-down selection summary.
state of these pins upon power-up of the ADS7830.
See Table 2 for a channel selection control summary.
The last bit of the address byte (R/W) defines the
operation to be performed. When set to a ‘1’ a read
Table 1. Power-Down Selection
operation is selected; when set to a ‘0’ a write
operation is selected. Following the START condition PD1 PD0 DESCRIPTION

the ADS7830 monitors the SDA bus, checking the 0 0 Power Down Between A/D Converter Conversions

device type identifier being transmitted. Upon 0 1 Internal Reference OFF and A/D Converter ON

receiving the 10010 code, the appropriate device 1 0 Internal Reference ON and A/D Converter OFF

select bits, and the R/W bit, the slave device outputs 1 1 Internal Reference ON and A/D Converter ON
an acknowledge signal on the SDA line.

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Table 2. Channel Selection Control Addressed by Command BYTE

CHANNEL SELECTION CONTROL
SD C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0 0 0 0 +IN –IN — — — — — — —
0 0 0 1 — — +IN –IN — — — — —
0 0 1 0 — — — — +IN –IN — — —
0 0 1 1 — — — — — — +IN –IN —
0 1 0 0 –IN +IN — — — — — — —
0 1 0 1 — — –IN +IN — — — — —
0 1 1 0 — — — — –IN +IN — — —
0 1 1 1 — — — — — — –IN +IN —
1 0 0 0 +IN — — — — — — — –IN
1 0 0 1 — — +IN — — — — — –IN
1 0 1 0 — — — — +IN — — — –IN
1 0 1 1 — — — — — — +IN — –IN
1 1 0 0 — +IN — — — — — — –IN
1 1 0 1 — — — +IN — — — — –IN
1 1 1 0 — — — — — +IN — — –IN
1 1 1 1 — — — — — — — +IN –IN

INITIATING CONVERSION READING DATA

Provided the master has write-addressed it, the Data can be read from the ADS7830 by read-
ADS7830 turns on the A/D converter section and addressing the part (LSB of address byte set to ‘1’)
begins conversions when it receives BIT 4 of the and receiving the transmitted byte. Converted data
command byte shown in the Command Byte. If the can only be read from the ADS7830 once a
command byte is correct, the ADS7830 will return an conversion has been initiated as described in the
ACK condition. preceding section.
Each 8-bit data word is returned in one byte, as
shown below, where D7 is the MSB of the data word,
and D0 is the LSB.
MSB 6 5 4 3 2 1 LSB
DATA D7 D6 D5 D4 D3 D2 D1 D0

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www.ti.com SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012

READING IN F/S MODE At the end of reading conversion data the ADS7830
can be issued a repeated START condition by the
Figure 15 describes the interaction between the master to secure bus operation for subsequent
master and the slave ADS7830 in Fast or Standard conversions of the A/D converter. This would be the
(F/S) mode. most efficient way to perform continuous conversions.

ADC Power-Down Mode ADC Sampling Mode

S 1 0 0 1 0 A1 A0 W A SD C2 C1 C0 PD1 PD0 X X A

Write-Addressing Byte Command Byte

ADC Converting Mode ADC Power-Down Mode

(depending on power-down selection bits)

Sr 1 0 0 1 0 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 N P

See Note (1)

Read-Addressing Byte 1 x (8 Bits + not-ack)

From Master to Slave A = acknowledge (SDA LOW) W = '0' (WRITE)

N = not acknowledge (SDA HIGH) R = '1' (READ)
S = START Condition
From Slave to Master P = STOP Condition
Sr = repeated START condition

(1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.

Figure 15. Typical Read Sequence in F/S Mode

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READING IN HS MODE See Figure 16 for a typical read sequence for HS

mode. Included in the read sequence is the shift from
High Speed (HS) mode is fast enough that codes can F/S to HS modes. It may be desirable to remain in
be read out one at a time. In HS mode, there is not HS mode after reading a conversion; to do this, issue
enough time for a single conversion to complete a repeated START instead of a STOP at the end of
between the reception of a repeated START condition the read sequence, since a STOP causes the part to
and the read-addressing byte, so the ADS7830 return to F/S mode.
stretches the clock after the read-addressing byte has
been fully received, holding it LOW until the
conversion is complete.

F/S Mode

S 0 0 0 0 1 X X X N

HS Mode Master Code

HS Mode Enabled
ADC Power-Down Mode ADC Sampling Mode

Sr 1 0 0 1 0 A1 A0 W A SD C2 C1 C0 PD1 PD0 X X A

Write-Addressing Byte Command Byte

HS Mode Enabled

ADC Converting Mode

(2)
Sr 1 0 0 1 0 A1 A0 R A SCLH is stretched LOW waiting for data conversion

Read-Addressing Byte

(1)
HS Mode Enabled Return to F/S Mode
ADC Power-Down Mode
(depending on power-down selection bits)

D7 D6 D5 D4 D3 D2 D1 D0 N P

1 x (8 Bits + not-ack)

From Master to Slave A = acknowledge (SDA LOW) W = '0' (WRITE)

N = not acknowledge (SDA HIGH) R = '1' (READ)
S = START Condition
From Slave to Master P = STOP Condition
Sr = repeated START condition

(1) To remain in HS mode, use repeated START instead of STOP.

(2) SCLH is SCL in HS mode.

Figure 16. Typical Read Sequence in HS Mode

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www.ti.com SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012

READING WITH REFERENCE ON/OFF then the settling time must be reconsidered after
PD1 is set to logic ‘1’. In other words, whenever
The internal reference defaults to off when the the internal reference is turned on after it has
ADS7830 power is on. To turn the internal reference been turned off, the settling time must be long
on or off, see Table 1. If the reference (internal or enough to get 8-bit accuracy conversion.
external) is constantly turned on and off, a proper
amount of settling time must be added before a 3. When the internal reference is off, it is not turned
normal conversion cycle can be started. The exact on until both the first Command Byte with PD1 =
amount of settling time needed varies depending on ‘1’ is sent and then a STOP condition or repeated
the configuration. START condition is issued. (The actual turn-on
time occurs once the STOP or repeated START
See Figure 17 for an example of the proper internal condition is issued.) Any Command Byte with
reference turn-on sequence before issuing the typical PD1 = ‘1’ issued after the internal reference is
read sequences required for the F/S mode when an turned on serves only to keep the internal
internal reference is used. reference on. Otherwise, the internal reference
When using an internal reference, there are three would be turned off by any Command Byte with
things that must be done: PD1 = ‘0’.
1. In order to use the internal reference, the PD1 bit The example in Figure 17 can be generalized for a
of Command Byte must always be set to logic ‘1’ HS mode conversion cycle by simply swapping the
for each sample conversion that is issued by the timing of the conversion cycle.
sequence, as shown in Figure 15. If using an external reference, PD1 must be set to ‘0’,
2. In order to achieve 8-bit accuracy conversion and the external reference must be settled. The
when using the internal reference, the internal typical sequence in Figure 15 or Figure 16 can then
reference settling time must be considered, as be used.
shown in the Internal VREF vs Turn-On Time
Typical Characteristic plot. If the PD1 bit has
been set to logic ‘0’ while using the ADS7830,

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Internal Reference
Internal Reference Turn-On Sequence Turn-On
Settling Time

Wait until the required

S 1 0 0 1 0 A1 A0 W A X X X X 1 X X X A P settling time is reached

Write-Addressing Byte Command Byte

Typical Read
Settled Internal Reference (1)
Sequence
in F/S Mode
ADC Power-Down Mode ADC Sampling Mode

S 1 0 0 1 0 A1 A0 W A SD C2 C1 C0 1 PD0 X X A

Write-Addressing Byte Command Byte

Settled Internal Reference

ADC Converting Mode ADC Power-Down Mode

(depending on power-down selection bits)

Sr 1 0 0 1 0 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 N P

See Note (2)

Read-Addressing Byte 1 x (8 Bits + not-ack)

From Master to Slave A = acknowledge (SDA LOW) W = '0' (WRITE)

N = not acknowledge (SDA HIGH) R = '1' (READ)
S = START Condition
From Slave to Master P = STOP Condition
Sr = repeated START condition

(1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.

Figure 17. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S mode shown)

The ADS7830 architecture offers no inherent

LAYOUT rejection of noise or voltage variation in regards to
For optimum performance, care should be taken with using an external reference input. This is of particular
the physical layout of the ADS7830 circuitry. The concern when the reference input is tied to the power
basic SAR architecture is sensitive to glitches or supply. Any noise and ripple from the supply will
sudden changes on the power supply, reference, appear directly in the digital results. While high-
ground connections, and digital inputs that occur just frequency noise can be filtered out, voltage variation
prior to latching the output of the analog comparator. due to line frequency (50Hz or 60Hz) can be difficult
Therefore, during any single conversion for an “n-bit” to remove.
SAR converter, there are n “windows” in which large The GND pin should be connected to a clean ground
external transient voltages can easily affect the point. In many cases, this will be the “analog” ground.
conversion result. Such glitches might originate from Avoid connections that are too near the grounding
switching power supplies, nearby digital logic, and point of a microcontroller or digital signal processor.
high-power devices. The ideal layout will include an analog ground plane
With this in mind, power to the ADS7830 should be dedicated to the converter and associated analog
clean and well-bypassed. A 0.1μF ceramic bypass circuitry.
capacitor should be placed as close to the device as
possible. A 1μF to 10μF capacitor may also be
needed if the impedance of the connection between
+VDD and the power supply is high.

18 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated

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 ADS7830

www.ti.com SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012

REVISION HISTORY
Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2008) to Revision C Page

• Extended specified temperature range from –40°C to +85°C to –40°C to +125°C throughout document .......................... 1
• Changed operating temperature range maxmimum value in Absolute Maximum Ratings table ......................................... 2
• Changed Voltage Reference Output, Range and Internal Reference Drift parameters in 2.7V Electrical
Characteristics table ............................................................................................................................................................. 3
• Changed Voltage Reference Output, Range and Internal Reference Drift parameters in 5V Electrical Characteristics
table ...................................................................................................................................................................................... 5

Changes from Revision A (March 2005) to Revision B Page

• Changed Low Power sub-bullets in Features section to show correct values; High Speed and Fast modes were
reversed (typo). ..................................................................................................................................................................... 1

Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: ADS7830
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

ADS7830IPWR ACTIVE TSSOP PW 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ADS
& no Sb/Br) 7830I
ADS7830IPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ADS
& no Sb/Br) 7830I
ADS7830IPWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ADS
& no Sb/Br) 7830I
ADS7830IPWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ADS
& no Sb/Br) 7830I

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Oct-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7830IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
ADS7830IPWT TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Oct-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7830IPWR TSSOP PW 16 2500 367.0 367.0 35.0
ADS7830IPWT TSSOP PW 16 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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