Fundamentals of Electronic

Packaging
Lecture-0
08/19/2024
Instructor information
• Prof. Dereje Agonafer
Presidential Distinguished Professor in the Department of Mechanical and Aerospace Engineering
Director of “Electronics, MEMS and Nanoelectronics Systems Packaging Center.
University of Texas at Arlington
Email Address: agonafer@uta.edu
Office Number Woolf Hall Room 211A

• Dr. Prasanna Jayaramu

Postdoctoral Research Associate
Electronics, MEMS and Nanoelectronics Systems Packaging Center
University of Texas at Arlington
Email Address: prasanna.jayaramu@uta.edu
Office Number Woolf Hall Room 310
Instructor information
• Dr. Prasanna Jayaramu
Current Position: Postdoctoral Research Associate at Electronics, MEMS and Nano-
electronics Systems Packaging Center, University of Texas at Arlington
Education: PhD in Mechanical Engineering
Indian Institute of Technology, Madras, India
Research Interest: Thermal Management of Electronic devices
Electronic packaging
Two-phase flow heat transfer
Microchannel flow.
Contact Info: Email Address: prasanna.jayaramu@uta.edu
Office Number Woolf Hall Room 310
 Course Information
• Section Information: MAE 4305-001, ME 5352-001, ME 5352-002,
ME 5352-003
• Description of Course Content: Fundamentals of electronic packaging
primarily focusing on single chip modules, including materials,
electrical design, thermal design, mechanical design, package
modeling and simulation, processing considerations, reliability, and
testing
• Prerequisites: Heat Transfer, Material Science, and Fluid Dynamics.
 Course Information
Syllabus :
• Introduction to Microsystems Packaging
• Role of Packaging in Microelectronics
• Fabrication of Integrated Circuits
• Review of Fluid Mechanics & Heat Transfer
• Fundamentals of Chip Packaging
• Fundamentals of Reliability – Package
• Guest Lecture
• Fundamentals of Reliability –Board Level
• Guest Lecture
• Fundamentals of Thermal Management
• State of the Art in IC and its impact on Packaging – 2.5D & 3D Packages
• Internet of Things & Packaging
• Guest Lecture
Course Information
➢Student Learning Outcomes: In-depth understanding of the various
types of components and packages, the printed wiring boards and
laminates, the materials and processes used in electronic packaging, the
fundamentals of reliability and relevant reliability enhancement methods,
and typical failures observed. Basic simulation skills for electronic
packaging models

➢Required Textbooks and Other Course Materials

▪ Essentials of Electronic Packaging: A Multidisciplinary Approach (Required Book)
Author: Puligandla Viswanadham, Editor in Chief: Agonafer, Publisher: McGraw
Hill
▪ Fundamentals of Microsystems Packaging (Reference Book)
Author: Rao Tummala, Editor: McGraw Hill
Grading Information
• Grading policy
Class participation/attendance: 5 %
Assignments: 15 %
Special Project: 25 %
Mid Term: 25 %
Final Exam: 30 %
Introduction to Electronic packaging
➢ Electronic Packaging: a multi-disciplinary subject
✓Mechanical, Electrical and material Engineering, Chemistry, Physics, etc.
➢Electronic Packaging: Interconnecting, powering, cooling, and protecting
all the system components that make up that entire system for the reliable
performance over a period of time
➢Electronic Packaging: Must provide
– Circuit support and protection
– Electrical and mechanical connection
– Heat dissipation
– Signal distribution
– Manufacturability and serviceability
– Power distribution
Source: Fundamentals of Device and Systems Packaging: Technologies
and Applications, 2nd Edition. Dr. Rao R. Tummala

Electronic Packaging starts with design, then device and packaging, and ends up with a system like a smartphone.
Introduction to Electronic Packaging
 Introduction to Electronic Packaging
Electronic packaging serves several key purposes, including:
➢ Protection:
• Mechanical Protection: Shielding components from physical damage such as shocks, vibrations, and impacts.
• Environmental Protection: Safeguarding against dust, moisture, corrosion, and other environmental factors that could degrade the
performance of electronic components.
• Thermal Management: Managing the heat generated by electronic components to prevent overheating, which could lead to failure.
➢ Interconnection:
• Electrical Connections: Packaging provides the necessary pathways for electrical signals to travel between components, such as
through soldered connections on a printed circuit board (PCB).
• Signal Integrity: Ensuring that the electrical signals are transmitted without interference or degradation, which is crucial for high-
speed and high-frequency applications.
➢ Structural Support:
• Packaging provides structural support for electronic components, keeping them in place within the device and ensuring they remain
connected and aligned.
➢ Form Factor and Aesthetics:
• The physical size, shape, and appearance of the electronic device, which is important for user interfaces and the overall design of
consumer products.
➢ Functional Integration:
• Some electronic packaging includes additional functionalities, such as shielding against electromagnetic interference (EMI) or
integrating passive components like capacitors and resistors directly into the package.
➢ Testing and Reliability:
• The packaging must allow for testing and validation of the components and systems to ensure reliability over the product's expected
lifespan.
Electronic Industry
❑Multi trillion-dollar industry
➢Growing at 5 to 8% YOY
➢Growth very high for consumer electronics
❑Electronics influence the way we live
❑Possibilities turn into commodity product in a very short time span.
❑Technological Advancement and price erosion enables high growth
rate

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
 Features of Electronic Industry

❑ Technology driven business

❑ Continuous price erosion
❑ High growth rate
❑ Large volume in Global market
❑ Short life cycle

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
Major Electronic System and Market
❑ Computer and business equipment
➢ Calculators, Desktop, Printers, Photocopiers etc.
❑ Communication
➢ Telephone, Fax, Modem
❑ Automotive electronics
➢ Engine control management, Cruise control, power steering, Safety features, Sensors
❑ Consumer electronics
➢ TV, VCR, Audio, Watches, Games etc.
❑ Medical Electronics
➢ CT Scan, MRI, X-Ray, Ultrasound machines, Robotic surgery system, etc.
❑ Military and aviation electronics
➢ Missile, Radar, Fire control system, Communications etc.
❑ Remote sensing
➢ Satellites, Sensors, Cameras, Drones etc.
❑ Industrial electronics
➢ Automation equipment, Drives and motor control, Control systems, Data acquisition and analysis, etc.
(Toyota's global production capacity is around 10 million vehicles per year (27,000 vehicles per day)!!!)
END
Fundamentals of Electronic
Packaging
Lecture 1
08/21/24

1
Electronic Industry
❑Multi trillion-dollar industry
➢Growing at 5 to 8% YOY
➢Growth very high for consumer electronics
❑Electronics influence the way we live
❑Possibilities turn into commodity product in a very short time span.
❑Technological Advancement and price erosion enables high growth
rate
Features of Electronic Industry

❑ Technology driven business

❑ Continuous price erosion
❑ High growth rate
❑ Large volume in Global market
❑ Short life cycle

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
Major Electronic System and Market
❑ Computer and business equipment
➢ Calculators, Desktop, Printers, Photocopiers etc.
❑ Communication
➢ Telephone, Fax, Modem
❑ Automotive electronics
➢ Engine control management, Cruise control, power steering, Safety features, Sensors
❑ Consumer electronics
➢ TV, VCR, Audio, Watches, Games etc.
❑ Medical Electronics
➢ CT Scan, MRI, X-Ray, Ultrasound machines, Robotic surgery system, etc.
❑ Military and aviation electronics
➢ Missile, Radar, Fire control system, Communications etc.
❑ Remote sensing
➢ Satellites, Sensors, Cameras, Drones etc.
❑ Industrial electronics
➢ Automation equipment, Drives and motor control, Control systems, Data acquisition and analysis, etc.
(Toyota's global production capacity is around 10 million vehicles per year (27,000 vehicles per day)!!!)
 Integrated circuit
• Main Elements of an electronic product
• A Product also requires
➢Passive components- Resistors, Capacitors, Inductors
➢Electrical and Mechanical Components – Switches, connectors, cables etc.
➢Cooling Components
➢Batteries/Power supply
➢Display Components- LED, LCD, Plasma display

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing

5
 Electronic Packaging
• Multidisciplinary Technology
• Physics
• Chemistry
• Materials Science
• Engineering
• Mechanical
• Electrical/Electronics
• Thermal
• Chemical

• Statistics Source: Fundamentals of Device and Systems Packaging: Technologies and Applications, 2nd Edition. Dr.
Rao R. Tummala

• Modeling and Simulation

6
 Electronic Packaging 1. Processor (CPU) -Acts as the brain of the smartphone, handling all instructions and processing tasks.
2. Graphics Processing Unit (GPU) - Responsible for rendering images, video, and animations.
3. Memory (RAM) - Temporary storage used by the CPU to store data for quick access while tasks are being processed.
4. Storage (Internal Memory)- Stores the operating system, apps, and user data (e.g., photos, videos).
5. Battery - Powers the smartphone, typically rechargeable lithium-ion batteries.
6. Display - The screen, often an OLED or LCD, that shows visuals, touch inputs, and media.
7. Camera Systems - Includes multiple lenses and sensors for taking photos and recording video.
8. Oscillators and Crystal Clocks - Generate precise timing signals for synchronizing various operations in the phone.
9. Sensors
Accelerometer: Detects orientation.
Gyroscope: Measures rotation and movement.
Proximity Sensor: Detects how close the phone is to objects.
Light Sensor: Adjusts screen brightness.
Fingerprint Sensor: For biometric authentication.
Magnetometer: Functions as a compass.
Face ID Components
10. Wireless Connectivity Modules
Wi-Fi
Bluetooth
Cellular Antennas (for 4G, 5G)
GPS Module
NFC (Near Field Communication)
11. Audio Components
Speakers
Microphones
Audio Jacks (if available)
Amplifiers
Source: https://fossbytes.com/whats-inside-smartphone-depth-look-parts- DAC (Digital-to-Analog Converter): Converts digital audio signals into analog sound.
powering-everyday-gadget/ 12. Charging Port -Typically a USB-C or Lightning port for charging and data transfer.
13. SIM Card Slot - Holds the SIM card used for network identification and connection.
14. MicroSD Card Slot
15. Inductors, Capacitors, and Resistors
16. Motherboard and Integrated Circuits -Houses the main circuitry, connecting all other components.
17. Flashlight/LED Flash
18. Heat sink or Cooling Components -Thermal Pads or Heat Pipes
19. Power Button
20. Volume Buttons
21. Casing

All these components are connected through intricate copper traces on the PCB, forming a complex circuit that
powers and operates the smartphone.
Source: Dr. Rao R. Tummala 2019

• Packaging starts with design, then device and packaging, and ends up • 400+ components in the smart phone
with a system like a smartphone. 7
 What is Electronic Packaging?
Electronic packaging is:

• A support structure for the reliable performance of an appliance through interconnection schemes in an

environment to process, transmit and/or store information.

• The functions of an electronic package are to protect, power, and cool the microelectronic chips or

components and provide electrical and mechanical connection between the microelectronic part and the

outside world.

Reference: Fundamentals of Device and Systems Packaging: Technologies and Applications, 2nd Edition. Dr. Rao R. Tummala 8
 Electronic Packaging
Electronic packaging serves several key purposes, including:
➢ Protection:
• Mechanical Protection: Shielding components from physical damage such as shocks, vibrations, and impacts.
• Environmental Protection: Safeguarding against dust, moisture, corrosion, and other environmental factors that could degrade the
performance of electronic components.
• Thermal Management: Managing the heat generated by electronic components to prevent overheating, which could lead to failure.
➢ Interconnection:
• Electrical Connections: Packaging provides the necessary pathways for electrical signals to travel between components, such as
through soldered connections on a printed circuit board (PCB).
• Signal Integrity: Ensuring that the electrical signals are transmitted without interference or degradation, which is crucial for high-
speed and high-frequency applications.
➢ Structural Support:
• Packaging provides structural support for electronic components, keeping them in place within the device and ensuring they remain
connected and aligned.
➢ Form Factor and Aesthetics:
• The physical size, shape, and appearance of the electronic device, which is important for user interfaces and the overall design of
consumer products.
➢ Functional Integration:
• Some electronic packaging includes additional functionalities, such as shielding against electromagnetic interference (EMI) or
integrating passive components like capacitors and resistors directly into the package.
➢ Testing and Reliability:
• The packaging must allow for testing and validation of the components and systems to ensure reliability over the product's expected
lifespan.
 Nomenclature

• Electronic Packaging is categorized hierarchically

• A Nomenclature of Convenience

• Plurality of Levels of Packaging

• Zero, First, Second, etc.

10
Levels of Packaging

Level 0 – Wafer-Level Packaging

Level 1 – Chip-Level or Die-Level Packaging

Level 2 – Printed Circuit Board (PCB) Assembly

Level 3 – Module-Level Packaging
Level 4 – Box or System-Level Packaging
Level 5 – System-of-Systems Packaging

Source: Tummala, Rao R. "Fundamentals of microsystems packaging." (2001)

11
 Mechanical design aspects of packaging
• Connections
• Manufacturing
• Thermal Management
• Maintenance
• Shock and Vibration
• Ergonomics
• Environment

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing

12
 Silicon wafer formation
Czochralski Process: Named after Jan Czochralski (discovered the method in 1916)

➢ Molten Silicon (Ultra pure) in a heated crucible

Schematic setup of a Czochralski crystal puller
• Adding dopant impurities atoms such as Boron, Phosphorous
➢ Seed Crystal brought in contact with fused Si
• Rotated (for homogeneity) and pulled upwards Watch Video:
➢ Crystal start growing in the form of an ingot. https://www.youtube.com/watch?v=xftnhfa-Dmo
• Thin wafers are chopped off 13
 Silicon wafer to Microchip formation

Slicing into Silicon wafer using

diamond saw

Watch Video: https://www.youtube.com/watch?v=g8Qav3vIv9s

• The die-sawing,
• Wire Bonding
• Molding and Solder Plating
• Marking and Lead Trim/Form

Encapsulated microchip
Final wafer production after cleaning,
A silicon wafter fabricated with polishing and inspection 14
Microelectronic circuit
 Zero Level Packaging
❑ Zero Level Packaging (Wafer-level Packaging)
It represents a key step in the transition from raw silicon wafers to fully functional dies or packaging
of integrated circuits (ICs) directly on the wafer before it is diced into individual chips.

• Packaging Different functions on a semiconductor

• Several Transistors, Circuits,
• Gate to Gate Interconnections
• Multitudes of Functions, processors, logic, memory
• Chip level interconnects etc.

15
 First Level Packaging
❑First Level Packaging (Chip-Level or Die-Level Packaging)
• Process of assembling a semiconductor Chip or Chips into an enclosure/package as a
1. Single Chip Module (SCM) - Individual chips and includes necessary electrical connections
2. Multichip Module (MCM)- Two or more chips interconnected on a single carrier. Ex: 2D, 2.5D, 3D
To facilitate Assembly on to a Board.

➢ Importance of First-Level Packaging:

• Electrical Performance: Ensures that signals can efficiently enter and exit the chip,
minimizing delays and interference.
• Mechanical Integrity: Protects the delicate chip from physical and environmental
damage.
• Thermal Management: Helps to dissipate heat generated by the chip, ensuring reliable
performance and preventing overheating.

16
Many changes on the horizon
New driving factor → performance, power and bandwidth
Tummala, Rao R. "Fundamentals of microsystems packaging." (2001)
 Second Level Packaging
❑Second Level Packaging (Printed Circuit Board Assembly)
• Assembling
• First level Packages on to a Printed Wiring Board
• Capacitors, Resistors, Inductances
• Switches Connectors
• Assembling number of smaller card with specific functionalities

• Key Aspects of Second-Level Packaging:

1. Mounting: Surface Mount Technology (SMT), Through-Hole Technology (THT)
2. Electrical Connections: Soldering, Wire Bonding:
3. Thermal Management: Heat Sinks, Thermal Via:
4. Testing: In-Circuit Testing and Functional Testing

19
 Third and Higher-Level Packaging
• Third Level Packaging (Module-Level Packaging)
• Assembling mother boards, daughter cards, baby board etc.

• Fourth Level Packaging (Box or System-Level Packaging)

• Box Level Assembly with
• Storage devices
• Cables
• Rack and box assembly

• Fifth Level Packaging(System-of-Systems Packaging)

• Host to terminals
• Printers, displays, keyboard, etc.

20
Packaging and Product Classification

21
 Components of Package
• The Package/component can be

• Leaded- J-leaded or Gull wing leaded

• Leadless- Bottom leaded

• Area Array
✓ Ball Grid Array
✓ Column Grid Array
✓ Pin Grid Array
• Package(chip carrier) can be
✓ Ceramic (Hermetic)
✓ Plastic (non-hermetic)
22
 Ceramic and Plastic Packages
• Relative Advantages and Disadvantages of Ceramic and Plastic Packaging

Source: Viswanadham, Puligandla. Essentials of Electronic Packaging: A Multidisciplinary Approach. ASME. 2011.
23
 Packaging Schemes in Semiconductor Packaging

Source: Viswanadham, Puligandla. Essentials of Electronic Packaging: A Multidisciplinary Approach. ASME. 2011. 24
 Product Categories and Environments
• Product Categories, Typical Operating Temperatures Extremities, and Designed Life

Source: Viswanadham, Puligandla. Essentials of Electronic Packaging: A Multidisciplinary Approach. ASME. 2011. 25
END
Fundamentals of Electronic
Packaging
Lecture 2
08/26/24

1
 Alternative definition: Electronic Packaging
Physical realization of an electronic system based on:
• Design
• Materials
• Choice of technology to implement design
• Electrical and thermal analysis
• Reliability analysis
• Much more

Packaging is the first step after semiconductor design and fabrication

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing

2
 Why packaging important?
Processor capability Challenges:
• 64 bits processor • Connections of a small chip with
• Billions of transistors so many I/Os over a tiny area
• Ensure that the transistors do-not
overheat

The processor or central processing unit (CPU) of a device acts like its brain, telling other components what
to do.
Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing 3
 Transistors
• A transistor is a miniature semiconductor that regulates or controls current or voltage flow in
addition amplifying and generating these electrical signals and acting as a switch/gate for them

➢ Heterojunction bipolar transistor (HBT)

➢ Field effect transistor (FET)
• Junction FET
• Metal-Oxide-Semiconductor FET(MOSFET)
➢ Bipolar junction transistor (BJT)
➢ Avalanche transistor
➢ Insulated gate bipolar transistor (IGBT)

➢ What do transistors do in a CPU?

• Transistors are the main component of the microchips used in computers. Computers operate on a
binary system, which uses only two digits: 0 and 1. In a computer microchip, transistors act as
switches, letting current through to represent the binary digit 1, or cutting it off to represent 0.
• More transistors can increase parallelism which increases speed, more things done at the same
time rather than serially
4
 Transistors
• Bipolar Junction Transistors are transistors that are
built up of 3 regions, the base, the collector, and the
emitter.
• Bipolar junction transistors come in two major types,
NPN and PNP.
• An NPN transistor is one in which the majority of the
current carriers are electrons.

• Field Effect Transistors are made up of 3 regions, a gate,

a source, and a drain.
• A voltage placed at the gate controls current flow from
the source to the drain of the transistor.
• MOSFET is most frequently used among all kinds of
transistors (Suitable for modern electronic applications)

Source: https://www.elprocus.com/different-types-of-transistors-and-their-functions/ 5
 N-type MOSFET
➢ A block, also known as a substrate of p-type
semiconductor acts as the base for MOSFET
➢ Two sides on this p-type substrate are made highly
doped with an n-type impurity (marked as n+)
• The drain terminals (Source and Drain) are then
brought out from these two end regions
➢ The entire surface of the substrate is coated with a layer
of silicon dioxide
• Silicon dioxide acts as insulation
➢ A thin insulated metallic plate is then placed on top of
the silicon dioxide, acting as a capacitor plate
• The gate terminal is then brought out from the thin
metallic plate
Source: Hiroshi Iwai. Downsizing of transistors towards its Limits. Tokyo Institute of
Technology.
➢ A DC circuit is then formed by connecting a voltage
source between these two n-type regions (marked in red)
Watch Video:
https://www.youtube.com/watch?v=Bine_PbyFSQ&t=69s

➢ When voltage is applied at the gate, it generates an electrical field that changes the width of the channel region,
where the electrons flow. The wider the channel region, the better conductivity of a device will be.
6
 Miniaturization and Transistor Scaling
• Digital integrated circuits generally contain transistors and interconnections. Depending on the
complexity and sophistication of the device design, the structure may contain several overlapping
layers.
• Many millions of gates are accommodated on a single chip with a multiplicity of layers and associated
interconnects. A transistor is formed whenever a gate layer crosses a diffusion layer.
• A variety of materials is used for interconnection, including tungsten, copper, aluminum.
• Fabrication of transistors include photolithography, etching, ion implantation, doping, and
metallization to create the intricate circuitry on a wafer.
• A silicon nitride layer is applied as the last layer to protect the circuits as a passivation layer. Sometimes
silicon dioxide or polyimides are also used as passivation films

➢ Intel Core i7-12700K (12th Generation):

• Transistor Count: Approximately 7 billion transistors
• Transistor size: 10nm

7
 Evolution of Transistor Sizes

Source: Hiroshi Iwai. Downsizing of transistors towards its Limits. Tokyo

8
Institute of Technology.
 Moors’s Law
• Moore’s Law: States that the number of transistors on a microchip
doubles approximately every 2 years, leading to smaller, faster, and
more powerful chips over time.

Intel co-founder Gordon Moore predicted a doubling of transistors every

year for the next 10 years in his original paper published in 1965.

Ten years later, in 1975, Moore revised this to doubling every two years -
Predicted that one can integrate 6.5 x 104 components by 1975

This extrapolation based on an emerging trend has been a guiding

principle for the semiconductor industry for close to 60 years.

In 1965, number of transistors in a single chip was roughly 50 transistors

per square inch.

Gordon Moore (1929 – 2023)

Source: Viswanadham, Puligandla. Essentials of Electronic Packaging: A Multidisciplinary Approach. ASME. 2011.
9
 Moore's Law (Cont.)

• At different times, interpretation of

“Moore’s law” revised

• Generally accepted definition:

• Number of components per chip
double every 18 months

Source: Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices.
PhD thesis. Chapter 2. The scaling of MOSFETs, Moore’s law, and ITRS.
10
 Moore's Law Implications
• Some of the implications include:
• Increase functionality
• Cost per function reduction
• Better Performance

• According to International Technology Roadmap for Semiconductors

(ITRS), functionality is defined as the number of bits in a DRAM chip
or the number of logic transistors in a microprocessor unit

• Reduction on the manufacturing cost per function is one of the

primary implications
Source: Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices.
PhD thesis. Chapter 2. The scaling of MOSFETs, Moore’s law, and ITRS. 11
 Challenges
• Compliance to “Moore’s law” requires geometrical shrinkage of transistor feature
sizes
• Delays due to metal interconnects and formation of hot spots limit performance due
to density improvements
• Circuit density increasing
• Operation frequency saturated

12
Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.
 Dennard’s Scaling
• In 1974, Dennard outlines:
• Rules for scaling of transistors
• Rules for scaling of interconnection lines
• Scaling of Transistors: Dennard's Scaling states that as
transistors are miniaturized, their power density
remains constant, meaning that power consumption
per transistor remains the same while transistor density
increases.
• Predicted that the fact the “line response time” for the
interconnects did not scale would create an issue
Source: Dennard, Robert H., et al. "Design of ion-implanted MOSFET's with
very small physical dimensions." IEEE Journal of Solid-State Circuits 9.5 (1974):
256-268.

Watch Video:
https://www.youtube.com/watch?v=dK66m
V6RU5Q

Source: Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices. PhD 13
thesis. Chapter 2. The scaling of MOSFETs, Moore’s law, and ITRS.
 ITRS
• International Technology Roadmap for Semiconductors (ITRS)
• Comprehensive guide that enables the semiconductor industry to transform
“Moore’s law” observations into reality

• Outlines requirements and identifies challenges that allow “Moore’s

law” to be maintained in the coming years
• Needs and requirements of solutions under development
• Outline limitations of interim solutions
• Identify areas where there are “no known manufacturing solutions”

• Help in synchronize technology development efforts by providing

guidance to research communities and funding agencies
Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.
14
 2015 ITRS Roadmap
• Expectation on device feature size
reduction revised on 2015

• Other approaches without reducing

transistor size

• Any further increase in circuit density

to come from 3D architectures
• Homogenous integration

Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.

15
 Looking Forward
• Integration density improvements
are saturating

• Two paths for increasing integration

and functional density:
• More Moore (MM) roadmap
• New path to increase integration density

• More than Moore (MtM) roadmap

• Increase in functionality density

Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD. 16

 More than Moore (MtM)
• More functions are offered per given chip area through heterogeneous
integration

• Heterogenous integration
• IEEE definition “Integration of separately manufactured components into a
higher-level assembly that, in the aggregate, provides enhanced functionality
and improved operating characteristics.”

• Allows the best available technology node to be used for each application to
maintain maximum performance

17
Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.
 18
Source: Will Chen. HIR Roadmap Workshop Presentation. 2017.
 19
Source: Will Chen. HIR Roadmap Workshop Presentation. 2017.
END

20
Fundamentals of Electronic
Packaging
Lecture 1
08/28/24

1
 Zero Level Packaging
Zero Level Packaging (Wafer-level Packaging): It represents a key step in the transition from raw silicon
wafers to fully functional dies or packaging of integrated circuits (ICs) directly on the wafer before it is diced
into individual chips.

• Packaging Different functions on a semiconductor

• Several Transistors, Circuits,

• Gate to Gate Interconnections

• Multitudes of Functions, processors, logic, memory

• Chip level interconnects etc.

Yield Rate:
➢ Yield refers to the number of functioning chips per wafer. Not all dies on a wafer are fully functional due to
defects in the manufacturing process. The higher the yield, the lower the cost per working die.
➢ At advanced process nodes (like 5nm), yield rates can be lower, driving up the cost per die.
2
 Fabrication of Chips
• Process of making chips involves as many as 300 steps that use chemicals, gas, or light

• Silicon chemically refined until it is 99.9999 % pure

• Purified silicon melted into long cylindrical Ingots

• Photolithographic “printing” process used to form a chip’s multi-layered transistors and electrical
passages

▪ Typically costs around $500 to $1,000 per wafer and

increases to between $3,000 and $10,000 when
processed with advanced nodes (e.g., 7nm, 5nm).

Source: http://download.intel.com/pressroom/kits/45nm/SandToCircuit_FINAL.pdf 3
 Optical Photolithography
Positive Photoresist(PPR) Negative Photoresist(NPR)
UV rays UV rays

Mask Mask

Photoresist material Photoresist

Substrate Substrate

Watch Video: https://www.youtube.com/watch?v=Z9zZoVJkafI&t=617s

4
 Fabrication Process of a Diode and Bi-polar junction
Transistor

Fabrication of a silicon diode junction. Fabrication of a bipolar junction transistor

Watch Video:
➢ Global Foundries Sand to Silicon (~10 min)
https://www.youtube.com/watch?v=UvluuAIiA50
➢ All About Semiconductor' by Samsung Semiconductor
Source: All about electronics https://www.youtube.com/watch?v=Bu52CE55BN0&t=330s
https://www.allaboutcircuits.com/textbook/semiconductors/chpt-2/semiconductor-manufacturing-techniques/ 5
 Fabrication process of MOSFET
Etching: Etching can be
done using a variety of
Pattern Transfer: The techniques, including wet
mask has a pattern etching, dry etching, and
on it that plasma etching
corresponds to the
electronic
component that is
being created Doping or ion implantation:
Boron or phosphorus, which
are added in small amounts
Deposition: Chemical to create either p-type or n-
vapor deposition type semiconductors,
(CVD), physical vapor respectively.
deposition (PVD), and
atomic layer
deposition (ALD).
Ex: metals, oxides,
and nitrides

1) p-type substrate wafer, 2) thermal oxidation, 3) photolithography, 4) oxide etching, 5) n+ ion implantation, 6) thermal oxidation, 7) gate
photolithography, 8) gate oxide etching, 9) metal deposition, 10) metal contact photolithography, 11) metal etching, and 12) final device.
Source: https://www.renesas.com/us/en/blogs/semiconductor-device-manufacturing-process-challenges-and-opportunities 6
 GaN Based Power Devices
• Better performance for power electronic applications

• Relatively low price when compared to SiC based technology

Source: https://www.infineon.com/dgdl/560pee0811.pdf?fileId=5546d462533600a4015356925db52b5d 7
 Carbon Nanotube Transistors
• ‘Faster and less power hungry than silicon chips’
• Active area of research to address manufacturing challenges

https://www.technologyreview.com/s/614247/the-worlds-most-advanced-nanotube- 8
https://www.nature.com/articles/s41586-019-1493-8 computer-may-keep-moores-law-alive/
 Additional Reference

• Fairchild Briefing on Integrated Circuits: (~ 30 min)

• https://www.youtube.com/watch?v=z47Gv2cdFtA

9
END

10
Lecture 4
04 September 2024

1
 Zeroth Level Packaging
• Purified silicon -> Ingots -> Wafer

• Photolithographic “printing” process used to form a chip’s multi-

layered transistors and electrical passages

2
A Sample of a Semiconductor Wafer

3
 Wafer
• Silicon Wafer is the starting point for all First Level Packaging
• Each wafer contains many devices
• Number depends on the device size and wafer size
• Wafers are 6”, 8”, or 12” diameter
• Wafers are cut to yield individual devices viz., chip or die
• Die has bond pads on the surface
– Perimeter pads single or multiple rows
– Area array pads

4
 First Level Packaging
➢ First Level Packaging:
• The Process of packaging semiconductor device(s) in a format to facilitate
attachment to the Printed wiring Board. Also called module or component

➢ Semiconductor devices are also called die, semiconductor, chip,

etc.
• Single Chip Module (SCM)
• Multi -Chip Module (MCM)

➢ Components maybe active or passive

• Active : Ability to electrically control electric charge flow. Eg : diodes, transistors
• Passives : Do not generate energy but can store it or dissipate it. Eg : Resistors,
capacitors, inductors
5
 First Level Packaging (Cont.)
➢ Importance of First-Level Packaging:
• Electrical Performance: Ensures that signals can efficiently enter and exit the
chip, minimizing delays and interference.
• Mechanical Integrity: Protects the delicate chip from physical and
environmental damage.
• Thermal Management: Helps to dissipate heat generated by the chip, ensuring
reliable performance and preventing overheating.

6
Chip to Chip carrier
❑ Chip carrier
➢ Housing for the thin and fragile chip

❑Purpose:
➢ Protect the chip from environmental and abusive handling
➢ Facilitate interconnection from chip to pad/holes on the circuit
board
➢ Provides pins/pads for that serve as bases for solder joints
➢ Also involved in the heat transfer process as the first step in the
heat flow path from source to sink

7
 Chip carrier
Parts of chip carrier
(Optional) • Chip
• Case
• Leads and Leads frame
• Chip to package bond
• Bonding wire
• Lid

➢ Many different chip carrier exist today but they all more or less conforms to this
parent structure

8
I/O counts
Needs for pin-outs is defined by Rent’s rules
NP = a NGb Number of I/O
Circuit Block
terminals, NP
NG
Where,
• NP is the number of pins (I/O terminals)
• NGis the number of logic gates in the block
• a is proportionality constant –normally between 0.5 and 1.5
• b is a constant that depends on the functionality of the package
Examples:
For low end memory chips, a= 6 and b=0.12
For high end, high-speed mainframe computer logics, a=1.4 and b = 0.63

9
 Key design features of a chip carrier
➢I/O counts
• Modern VLSI or ULSI chips have thousands of gates thereby requiring larger
number of I/Os
➢Hermeticity
• Ensure reliable operations
• Entry of moisture is avoided- can corrosion of pins, wires
• Organic materials that out-gas(release volatiles) with time are not used.
➢Heat dissipation
• Modern circuitry result in very high heat flux

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
10
Types of chip carrier
➢Based on materials
• Plastic
• Ceramic
• Tapes
➢Based on connection
• Through hole
• Surface Mount
• Leadless
➢Based on I/O layout
• Peripheral
• Area Array
• Flip Chip

11
 Classification
❑ Two classes of chip carrier: Ceramic vs. Plastic

• Ceramic Packages • Plastic Packages

– High performance
– High I/O capability – Also called Plastic Encapsulated Microcircuits
– High Reliability (PEM)
– Hermetic – Used for most commercial, consumer, and
– Suitable for Harsh environments business applications
– Bonding material - Eutectic Solder of gold – Lighter
and Silicon
• Inorganic-does not release volatiles – High volume Manufacturing capability
• Melting point 390oC – Greater Availability
• Thermal Conductivity is 296 W/mK
• Aids in heat transfer from chip to case – Cheaper
– Expensive – Not hermetic (Prone to Moisture sensitivity)
– Brittle
– Heavy – Not for high temperature applications

12
 Classification (Cont.)
• Both ceramic and plastic components are made in different termination
formats depending on design and application requirements
• Components/Packages are either inserted into corresponding Cu-plated holes on
PWB or mounted on the surface pads
• Another classification of electronic components based on termination or lead
configurations
✓ Insertion mount or through-hole packaging
✓ Leadless packaging
✓ Surface mounted leaded packages
✓ Area array packaging etc.

13
Ceramic package - assembly process
• A lead frame is a metal structure inside a chip package that
carries signals from the die to the outside

Lead frame for a QFP package, before encapsulation

• Wire bonding is used to connect semiconductor chip electrodes to

the electric conductors of lead frames with thin wires of gold,
aluminum, or copper.

Schematic of ceramic package - assembly process

A wire bonding mechanism.

14
 Ceramic chip carriers

Flat pack Pin-grid array(PGA)

Leadless chip carrier(LCC) Plastic leaded chip

carrier(LCC)
Different types of ceramic chip carriers

15
 Plastic Encapsulated Microcircuit (PEM)
• It consists of an integrated circuit chip physically
attached to a lead frame, electrically
interconnected to input-output leads, and
molded in a plastic that is in direct contact with
the chip, lead frame, and interconnects

Used for product with

• Low power
• Moderate I/O Count
• Lenient hermetically requirement

16
 Plastic Package Encapsulation
• First introduced in the late 1960s
• Preferred packaging scheme b/c of high volume, large – scale production capability
• Some advantages
– To provide rigidity, mechanical protection
– Insulate and protect wire bonds
– Resist effects of vibration
– Dust protection

– Protection from moisture-condensing and noncondensing

– Corrosion prevention

17
 Plastic Package Encapsulation (Cont.)
➢ Types of materials:
• Thermoplastic and Thermoset
➢ Thermoplastics
• Soften on heating
• Repeated heating and cooling does not alter properties
• Amenable for rework and repair
• Not for moderately high temperatures
➢ Thermoset
• Do not soften on heating
• More prevalent use
• Epoxy and modified epoxy resin systems

18
PEM Assembly flow chart

19
Dual Inline Package(DIP)
• First package (invented in 1960s)
• Both plastic and ceramic
• Low wattage chip
• Fully encapsulated
• Pin inserted in hole
⁻ Attached to the underside of the board by
wave soldering

20
 Dual Inline Package(Cont.)
➢ Advantages ➢ Disadvantages
• Robust pins and connections • Poor area efficiency
• Automated assembly- pick and place machine • Limited wireability
• Width of pin increased near the body-provide a • Limited I/O counts(100 mil pitches
shoulder

21
 Types of Leads

Pin-in-hole Gull wing type leads J-type leads

22
Through (Thru’) Hole Mounting

The pins of the components go through the previously drilled

PCB holes
➢ Benefits
• Easy to solder, either automatically (wave) or by hand
• Easy to desolder and test
• Implement interconnections between upper and
lower layers (vias) in nonplated hole technologies
➢ Drawbacks
• Signals must necessarily go through all PCB layers
• Low density due to minimum pin diameter and only
one-sided mounting

23
 Surface-Mount Technology (SMT)
The pins of the devices are mounted directly onto the surface
of the PCB
➢ Benefits
• Much higher density: pins can be thinner, devices can
be mounted on both sides of the PCB, components do
not block signals in inner layers
• Higher degree in the automation of the mounting
process Less parasitic inductance and capacitance
• Reduced costs (½ to ¼) and size (¼ to one tenth)
USB flash drive's circuit board.
➢ Drawbacks
• Poor manual solderability and reparability
• Started in 1960s • Reliability issues due to thermal/mechanical stress
• Gain impetus in the 1980s during soldering and operation (different thermal
• Can be plastic or ceramic package expansion coefficients)
• Several styles have evolved • Classic verification procedures no longer valid

24
 Types of surface-mount packaging

➢Peripheral packaging
• Dual inline package
• Small Outline pack
• Quad flat pack
➢Area array packaging
• Pin grid array(PGA)
• Ball grid array(BGA)
• Land grid array(LGA)

25
 Peripheral packaging
• Dual inline package

• Small Outline package

• Quad flat pack

26
 Dual Inline Package

Max pins 50-60

1970
27
Quadruple Flat Package(QFP)

# of Pins
• DIP – up to 50
• QFP – up to 200

1975-80
28
Area array packages
• Utilizes the entire bottom side of the carrier for interconnections
instead of only the perimeter.
• Since area available is higher, it is possible to have
⁻ Higher I/O counts (high density of connections in a relatively small footprint)
⁻ Increased lead pitches
• Provides better thermal dissipation compared to traditional packages,
which helps manage heat more effectively and enhances reliability.
• Types of Area array packaging
➢ Pin grid array(PGA)
➢ Ball grid array(BGA)
➢ Land grid array(LGA)
29
 Pin Grid Array (PGA)
• Can handle larger I/O Counts
• The pins are arranged in a regular array on the underside of the
package
• Pins to go vias (holes) in the socket
• CPU Socket allows for placing and replacing the package without CPU Socket
soldering.

Motorola 68020

Watch Video: Click

1985
30
 Ball Grid Array (BGA)

• Utilizes small solder balls for connection between

components and mother board
• Active chip can be interconnected to the package by wire
bonding or flip chip technology

Watch video: Click

Intel Mobile Celeron in a flip-chip BGA2 package: the die appears dark
blue. Here the die has been mounted to a PCB substrate below it (dark
yellow, also called an interposer) using flip chip and underfill. 1990
31
 Ball Grid Array (Cont.)
Advantages
• Improved electrical performance due to shorter distance between chip and solder balls
• Improved thermal performance by use of thermal vias incorporated in the substrate
• Occupies less board real estate(less package area I/O)
• Reduced handling related lead damages due to use of solder balls instead of metal leads
• When reflow attached to boards, solder balls self align leading to higher manufacturing yields.

Disadvantages
• Difficult to inspect formed solder joint after assembly
• X-ray technique used normally- but not effective in determining if a joint is cold or wet.
• Other techniques involve fiberoptic light and optical instrument
• Keep-out area required in board for such technique

32
 Land Grid Array (LGA)

Package Watch Video: Click

Socket

• A land grid array(LGA) is an integrated circuit design involving a square grid of contacts that are connected to other
components of a printed circuit boards.
• LGA sockets are designed to hold LGA packages, which have an array of pads or lands on their underside
• In contrast to most other design, LGA Configuration have pins in the socket rather than on the package/chip

2000
33
 Land Grid Array (Cont.)
• No solder joint/balls
• Uses lands and connections pads
• Pins on the socket side
• Designed for lesser lead usage allowing for better restrictions of hazardous substances(RoHS)
• Advantages
✓ Ease of assembly/ disassembly
✓ Thinner and lighter packages
✓ Short electrical path
• Click this link for more information on LGA package

34
Watch video: Click

35
 Next Lecture:
First Level Packaging Continued

36
Lecture 5
09 September 2024

1
 Chip Scale Packages (CSPs)
• Evolved in the mid 1990s
• Its greatest advantage is size reduction
• A CSP is any package that has a foot print no greater than 1.2 times that of the IC (Silicon device)
• Have an interposer layer that absorbs CTE mismatch related stresses
• The name, CSP, does not give details about package construction
• CSP classified into four categories:
➢ Flex Circuit interposer
➢ Custom Lead frame based
➢ Rigid substrate interposer
⁻ Organic
⁻ Inorganic
➢ Wafer level Assembly
FIGURE: Schematic of a u-star flex-based chip scale package

2
 Wafer Level Chip Scale Packages (WLCSP)
• Wafer level chip scale packaging
➢Packaging operations performed on a wafer and then singulated to individual
packages for shipment

Watch Video 1: Click

Watch Video 2: Click

Source: https://www.argenox.com/static/assets/qfn_wlcsp.png 3
Packaging Efficiency

• Packaging Efficiency is defined as

𝐼𝐶 𝑆𝑖𝑧𝑒
Efficiency =
𝑃𝑎𝑐𝑘𝑎𝑔𝑖𝑛𝑔 𝑆𝑖𝑧𝑒

• Examples:
DIP: 2%
QFP: 5%
BGA/CSP : 30-80%
Bare Chip : 100 %

4
 Flip chip
▪ A chip packaging technique in which the active area of the chip is
"flipped over" facing downward. Instead of facing up and bonded
to the package leads with wires from the outside edges of the
chip, any surface area of the flip chip can be used for
interconnection, which is typically done through metal bumps of
solder, copper or nickel/gold. These "bumps" or "balls" are
soldered onto the package substrate or the circuit board itself
and underfilled with epoxy. The flip chip allows for a large
number of interconnects with shorter distances than wire, which
greatly reduces inductance.

5
 Flip chip

Source: https://www.pcmag.com/encyclopedia/term/flip-chip
6
 Flip chip
• Bare semiconductor chips are turned upside down and bonded directly into the
motherboard or chip carrier
➢Connections are made through solder bumps and (solder wettable) pads
➢High I/O count
➢All connections can be made simultaneously
➢Top surface (back side of the chip) is available for heat dissipation.
• First introduced by IBM in 1962.
➢Path breaking technology invention
➢Introduced for ceramic substrates (Solid Logic Technology)
➢ Converted in 1970 to C4 (Controlled Collapse Chip Connection) for ICs
➢Initially used for peripheral packages but quickly progressed to area arrays

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
7
 Flip chip - Process

1. Pads are metallized 2. A solder balls are 3. Chips is flipped 4. Flipped chip is positioned so that the solder 5. Flipped chip is placed
on the surface of deposited on each of the balls are facing the connectors(pads) on on the connectors
the chip. pads, the external circuitry

6. Solder balls are then remelted 7. Mounted chip is "underfilled" using a 8. Final - Flip chip package
(capillary flow) electrically-insulating adhesive

8
Source: https://en.wikipedia.org/wiki/Flip_chip
 Why use Flip Chip?
• Small size
➢ Reduced board area, less height, lesser weight
• Improved performance - high speed
➢ Eliminating bond wires reduces the delaying inductance and capacitance
➢ Shortens the path by a factor of 25 to 100
• Great I/O flexibility
• Rugged
➢ With "underfill", flip chips behave like small blocks of cured epoxy
• Availability of materials, equipment and services

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
9
 1st level connections

• Automated wire bonding

➢Thermo compression
➢Ultra sonic
➢Thermo sonic
• Flip chip bonding
• Tape automated bonding

10
 Wire bonding
▪ Wire bonding is an electrical interconnection technique using thin wire and a combination of heat,
pressure and/or ultrasonic energy. Wire bonding is a solid phase welding process, where the two
metallic materials (wire and pad surface) are brought into intimate contact. Once the surfaces are in
intimate contact, electron sharing or interdiffusion of atoms takes place, resulting in the formation of
wire bond.

Source: https://www.pcb-hero.com/blogs/lickys-column/wire-bonding
11
Wire bonding methods
• Two basic wire bonding methods
➢ Ball bonding
➢Wedge Bonding

12
 Ball Bonding
❑ Components
➢ Wire
➢ Capillary tool
➢ Electronic Flame off (EFO) system

Procedure
(1) Gold wire is threaded through the capillary and electric flame-off
(EFO) is used to form a ball on the end of the wire.
(2) The capillary descends and presses the gold ball onto an aluminum
terminal set on the surface of a semiconductor chip.
(3) Ultrasonic bursts of energy are applied with the capillary, creating a
weld using atomic interdiffusion between the gold ball and bonding
pad.
(4) The capillary ascends vertically to play out sufficient wire to form a
Figure: Procedure for ball bonding loop as it moves toward the second bond site.
(5) The capillary descends to make the second bond (crescent bond).
(6) The wire clamp is closed, and the capillary moves vertically to break
➢ Uses T/C or T/S bonding
the wire at the heel of the second bond.
➢ Temperature range is 100-500°C
➢ Fine gold wire (75µ) normally used where the pad pitch is greater Watch Video 1: Click
than 100m
Watch Video 2: Click
13
Source: Harman, G.G., 1997. Wire bonding in microelectronics materials, processes, reliability and yield.
 Ball Bonding(Cont.)

Source: Packaging of Electronic Systems: A Mechanical Engineering Approach, James W. Dally · 1990 14
 Wedge Bonding
• Name is based on shape of the tool
• Wire fed at 30-60° from the horizontal bonding
surface through a hole in the back of a bonding
wedge
• Process used is normally U/S or T/S
➢Al wire - U/S bonding process
➢Au wire - T/S bonding process
• Can be used for smaller pitches Speed is low

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing 15
 Wedge Bonding (Cont.)
❑Process
• Wire pinned against die pad
• U/S or T/S bond is formed
• Wedge ascends and forms the loop
• Descends on the substrate and forms the second bond
• Wire torn after second bond using clamp tear (wedge
stationary) or table tear (clamp stationary)

Watch Video: Click

Source: https://www.inseto.co.uk/fine-wire-bonding-explained-ikb-064/
16
Tape Automated Bonding (TAB)
• Process of mounting a die on a flexible tape made of polymer material,
such as polyimide.
• Mounting is done such that the bonding sites of the die, usually in the form
of bumps or balls made of gold or solder, are connected to fine
conductors on the tape, which provide the means of connecting the die to
the package or directly to external circuits.
• Sometimes the tape on which the die is bonded already contains the
actual application circuit of the die.

17
 Tape Automated Bonding (TAB)
Tape Carrier: A flexible, insulating film (typically made of polyimide or
polyester) embedded with a series of conductive traces.
Bonding Process: In TAB, the IC is mounted on the tape carrier, and the
bonding is performed using a combination of thermal and mechanical
processes.
Automated Equipment: TAB is often used with automated equipment that
performs the placement, alignment, and bonding of the IC to the tape carrier,
improving efficiency and precision.
Application:
• Consumer Electronics: TAB is commonly used in consumer electronics,
including LCD displays and other compact devices where space and
performance are critical.
• Automotive: In automotive applications, TAB can be used for sensors and
control units that require robust and compact packaging.
• Communication Devices: TAB is employed in communication devices where
high-density interconnections and small package sizes are needed.
Watch Video: Click
18
 Next Lecture:
Flip chip bonding

19
Lecture 6
11 September 2024

1
 Flip chip bonding

Bumping the die Attachment to substrate Epoxy Underfill

2
Flip chip bonding process
▪ Formation of solder bumps on the front face of the die/chip
➢ Under bump metallization (UBM)
➢ Solder deposited over the UBM by evaporation, electroplating, screen printing
solder paste, or needle-depositing
▪ Bumped die placed on substrate pads
➢ Wetted controlled collapse interconnection
➢ Solid state bond - uses T/C or T/S bonding techniques
➢ Solder flux helps in removal of oxide and ensures perfect wetting
▪ Under-chip space filled with a non-conductive "underfill" adhesive joining the entire
surface of the chip to the substrate

3
Bumping the die
▪ Formation of solder bumps on the front face of the die/chip
➢ Under bump metallization (UBM)
➢ Solder deposited over the UBM by evaporation, electroplating, screen
printing solder paste, or needle-depositing

4
 Under Bump Metallization (UBM)
• Under Bump Metallization (UBM) is an essential step where the
connection pads are coated/sputtered with a metallic layer
➢IC connection pads typically Al (oxidation, non wettable, non - solderable)
➢UBM layer produces a good bond to the aluminum pad, hermetically seals the
aluminum, and prevents the potential of diffusion of metals into the IC package
• Methods
➢ Dry vacuum sputter method combined with electroplating - multi-metal layers
sputtered in a high temperature evaporation system
➢Several UBM metllizations - (Al,Ni,Cu), (Ti,W,Cu),(Cr,Cu,Au), (Ni,Au), (Ni,V,Cu) etc.
➢Electroless Nickel/Immersion Gold (ENIG) - consists of wet chemical processes

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
5
Bumping Process

Source: https://www.practicalcomponents.com/Dummy-
Components/product.cfm?Flip-Chips-DE7E9895BEF7314E

https://www.flipchip.com/bumping.html
6
Attachment to the Substrate
• Bumped die placed on substrate pads
➢Solder is "reflowed" - typically using hot air reflow soldering process
➢Solder flux helps in removal of oxide and ensures perfect wetting

7
Underfill
• Underfill (Nonconductive adhesive fills the gap between the surface
of the chip and the substrate)
➢Needle-dispensed along the edges of each chip
➢Drawn into the under-chip space by capillary action
➢Heat-cured to form a permanent bond

8
 Why is underfill required?
➢ Compensate for any thermal expansion difference between the chip
and the substrate - mechanically "locks together" chip and substrate
so that differences in thermal expansion do not break or damage the
electrical connection of the bumps.
➢ CTE of silicon is 3 PPM/oC and typically FR4 material is 17 ppm/oC -
large strain is observed in solder bumps due to this thermal expansion
mismatch
➢ Protects the bumps from moisture or other environmental hazards A
➢ Provides additional mechanical strength to the assembly
➢ Thermally conductive and electrically insulating (Ex: Epoxy )

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
9
 Underfill Process

Injection flow
Capillary flow

Compression flow
Watch video -1: Click
Watch video -2: Click
10
 Flip Chip Assembly - On Organic Substrate

1 MHZ Wafer solder

Semiconductor Dicing/
Wafer Screen
Test
Bumping singulation

Pick and Solder

Place, apply Cleaning Test
Flux
Reflow

Underfill
Cure
Encapsulation

11
 Summary of first level packaging
• Types of packages
➢Material – Ceramic, Plastic
➢Interconnect type – Thru’ hole, Surface mounting
➢Peripheral – DIP, QFP
➢Area Array – PGA, BGA, LGA
➢Chip Scale Packages
➢Flip Chip
• Interconnection technology
➢Wire bonding – Ball bonding, Wedge bonding
➢Tap Automated Bonding
➢Flip chip bonding

12
 Advanced Packaging

• Multi-chip module (MCM)

• System on Chip(SoC)
• System in Package (SiP)
• Package on Package (PoP)

13
 Multi-chip module (MCM)
❑ Multiple Chips on the same substrate/package
• A multichip module (MCM) is a package that integrates multiple chips, or integrated circuits (ICs), onto a single
substrate
Advantages:
• Space Efficiency: Allows for the integration of multiple ICs in a compact form factor,
saving board space.
• Performance: Provides good electrical performance with low interconnect inductance
and resistance.
• Flexibility: Can combine different types of chips (e.g., analog, digital) in one module,
optimizing overall system performance.

A ceramic multi-chip module containing

Applications:
4 POWER5 processor dies (center) and • High-performance computing: Used in applications requiring high-density
four 36 MB L3 cache dies (periphery) integration, such as server processors and telecommunications equipment.
Source: Wikipedia
• Custom solutions: Ideal for custom or specialized applications where multiple chips
need to be combined.
• AMD’s high-end desktop CPUs, such as the Ryzen Threadripper and server CPUs like the EPYC, use a chiplet-based architecture, which is a form of MCM.
• High-end GPUs, such as NVIDIA's GeForce RTX series and AMD's Radeon RX series, may utilize MCM or multi-die designs, especially in professional and
workstation-grade models 14
Characteristics of MCMs
➢ Substrate materials: MCMs can use a variety of substrate materials, including ceramic, silicon, or
laminate.
➢ Bonding methods: Chips are attached to the substrate using wire bonding, flip chip bonding, or
wafer bonding.
➢ Thermal dissipation: MCMs with ceramic substrates can dissipate heat well in harsh environments.
➢ Size: MCMs are smaller than conventional single chip packages, which can lead to smaller
motherboards and enclosures.
➢ Complexity: MCMs can range in complexity, from pre-packaged ICs on a small printed circuit board
(PCB) to fully customized chip packages.
➢ Chiplets: Multiple chiplets, which each contain a limited set of functions, can be assembled into an
MCM

15
 System on a Chip (SoC)
❑A complex microelectronic circuit that integrates various key components of a
computing device into a single chip

• Multiple functions are implemented on a single die

➢ Highest performance at lowest power
➢ Extremely complex
• Possibilities
➢ one or more processor cores, memory blocks, peripheral
functions, and hardware accelerators, all created on the same
piece of silicon
➢ digital logic, memory, and analog/RF functions all on the same die

• Advantages of Consolidation
➢ Energy efficiency, compactness, and performance gains.

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing 16
 System in package (SiP)
• Chip-scale package (CSP) devices mounted on a common substrate used to
connect them all together. Ex: 2.5D and 3D Integration
• Substrate and its components then placed in a single package
• Possibilities
➢ can include analog, digital, and radio frequency (RF) dice in the same package, where
each die is implemented using that domain's most appropriate technology process

Typical SiP structure schematic.

17
Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
 Package on Package (PoP)
• Allow one peripheral package on top of another

• Package-on-Package (PoP) technology is a key innovation for achieving

compact and high-performance electronic designs.
• Applications, such as smartphones, tablets, and other portable devices.

18
Source: Puligandla Viswanadham
 Next Lecture:
2.5 D and 3 D integration

19
Lecture 7
18 September 2024

1
Second Level Packaging / Printed Circuit Board Assembly

➢Assembling
• First level Packages on to a Printed Wiring Board​
• Capacitors, Resistors, Inductances​
• Switches Connectors​
• Daughter Cards with devices already assembled

2
 Level - II Packaging: Circuit Boards
• PWB-Printed Wiring Board PCB-Printed Circuit Board
• CCA-Circuit Card Assembly PWA-Printed Wiring Assembly

Circuit board is the major element in the mechanical design of an electronic system
It is the "circulatory system" of the electronic product

Functions:
• Mounting surface for components
• Soldering pads for 1st to 2nd level and 2nd to 3rd level
• Wiring paths for chip-to-chip connections
• Test bed and points for circuit checks
• Marking surface for identification of components and assembly

3
 Printed Circuit Board

Through-hole devices mounted on the circuit board

of a mid-1980s Commodore 64 home computer

Printed circuit board of a DVD player

Simple PCB manufacturing process - Watch Video: Click

Source: https://en.wikipedia.org/wiki/Printed_circuit_board 4
 Printed Circuit Boards
➢ Laminates, Substrates and PCBs are Important Building Blocks of any Electronic Appliance. They are:​
• Carriers/Platforms for Silicon in First Level Packaging​
• Enablers in Connectivity of Different Elements​
➢ Their nature depends on the complexity and functionality of the device being packaged​
➢ Electrical, Mechanical, and Environmental Requirements dictate their design, materials, and construction
➢ Generally Multilayered- layers bonded together
➢ Signal, Power, Ground, thermal etc. layers

5
 Anatomy of circuit board
• Circuit board - laminate with copper cladding on one or both
sides
• Laminate - glass cloth, cotton fabric or paper reinforcement in a
polymer matrix
➢Thermosetting polymers (phenolics, epoxies, polyimides) are used for
rigid boards

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
6
 Printed Circuit Boards
• Single-side plated
• Low cost, low complexity applications.
• Unplated holes for insertion mount components
• Double-side plated
• Low complexity, holes or vias are plated, most widespread.
• In through hole technology, component leads are inserted in the plated through holes.
• In surface mount technologies the holes (called vias) are smaller in diameter, may be filled with
metal, and are used only for interconnection.

Non-plated trough holes Plated through holes in the Multi-layered PCB

7
Types of PCBs
Number of Conducting Layers and Role of Holes
➢Single-sided, double-sided
➢Multilayer
• Four or more layers, assembled with alternate layers of double-sided laminate and pre-
preg layers linked with vias.
• Used for high density applications.
• While most applications use 4-8 layers, some aerospace and high-speed computing
applications can use 24-32 layers

Watch Video: Click

Multilayer PCBs
8
 Laptop Motherboards

Dell Inspiron 15 Apple Macbook Air 13”

9
Circuit board materials
❑Selection criteria

➢ Cost

➢ Electrical characteristics
• Surface resistivity
• Dielectric constant - low k is desired for high-speed signal processing
• Dissipation factor - measure of loss/leakage of power

➢ Mechanical properties
• Flexural strength, modulus of elasticity
• Dimensional stability, CTE
• Glass transition temperature
• Resistance to humidity

➢Physical properties
• Corrosion and moisture resistant
• Able to drill through
• Thermal conductivity

10
 Glass Fibers
• Although several glass compositions have been developed, only a few of them
are used to make continuous glass fibers.
• The four main glasses used are: electrical grade (E- Glass), a modified E-Glass that
is chemically resistant (C-Glass), and high strength silica (S-Glass) and D-glass.
• E-Glass is most commonly used in PCBs.
• S and D glasses are typically used to lower thermal expansion, lower dielectric
constant, or provide high temperature stability. CTE is around 3 ppm/°C.

Source: https://www.sciencedirect.com/topics/physics-and-astronomy/e-glass 11
 Fabrics
• Fabrics are planar structures consisting of yarns of fibers .
• Yarns are interlaced at right angles to each other to form a fiber arrangement that determines
the fabric structure, as shown in the first figure .
• The second picture shows a cross-section of a typical fabric weave impregnated in epoxy
resin.

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing 12
 Circuit board materials (cont..)

➢Common PCB materials

• FR1 (XXXP) -Unwoven paper fabric with phenolic resin. Low temperature, low-
cost material. Used mainly in single-layer unplated boards.
• FR2 - Similar to XXXP except phenolic matrix has additives to make it fire
resistant
• FR4-Woven glass fiber fabric in epoxy resin. Moderate temperature (T < 135°C),
moderate cost, high reliability material. Used widely for double and multilayer
plated boards.
• High elastic modulus (3-4 MPa)
• CTE closely matched to copper
• Low Tg
• Fire resistant

13
 Circuit board materials (cont..)

• FR5-High temperature, higher cost, tetra-functional epoxy version of FR4 (T < 185
deg oC)
• Polyimide-Glass (or quartz) -Very high temperature, high-cost applications (T < 300
deg oC)

14
Copper Clad Laminates(CCL)

• A CCL is made up of a fully-cured epoxy resin fiber core sandwiched

between two layers of copper cladding.
• The copper cladding will eventually become two inner layers, and the
laminate will act as dielectric spacing between two layers. This eventually
becomes the base material for Printed Circuit Board (PCB) fabrication.

15
 Copper foil

➢Electrodeposited copper foil

➢Rolled copper foil
➢Thickness measured in oz./ft² (roofing industry)
• 1 oz/ft² => 1.35 mil (35 µm)
• 2 oz/ ft² => 2.70 mil (70 µm)
• 1/3 oz/ft² => 0.45 mil (12 µm)
• 1/2 oz/ft² => 0.675 mil (18 µm)

16
 Copper foil - Electrodeposition

Electro-deposited
• Copper foil deposited on a titanium rotating
drum from a copper solution.
• Cu surface smooth on drum side and
rough/matte on the opposite side
• Surface treatments enhance adhesion
• When an electric field is applied, copper is deposited on the drum as it
between copper and dielectric interlayer rotates at a very slow pace

during copper clad lamination process • The copper surface on the drum side is smooth while the opposite side
is rough.
• Slows down surface oxidation

Source: Recent Advances in Microelectronics Reliability, Spinger link:https://link.springer.com/book/10.1007/978-3-031-59361-1 17

 Copper foil - Rolling
• Successive cold rolling starting with a billet of pure copper; surface smoothness depends on
rolling mill.
• Surface treatment (oxidation) to form a good adhesive bond with the laminate. This oxidation
forms "toothy copper".
• Rolled copper offers higher ductility than electrodeposited copper - more suitable to flexible
PCB.

18
 Inner Layer Process steps

• Optical Photolithography technique is used

Source: https://ntrs.nasa.gov/api/citations/20180005658/downloads/20180005658.pdf
19
 Optical Photolithography
Positive Photoresist(PPR) Negative Photoresist(NPR)
UV rays UV rays

Mask Mask

Photoresist material Photoresist

Substrate Substrate

Watch Video: Click

20
 Lithography
➢ Transfer of image of circuit board features from photo tool to the copper clad laminate using
photo resist techniques
➢ Photo resist printing
• Photo resist - polymeric coatings that is sensitive to light
• Photo polymers must be resistant to select chemicals and adhere well to copper

Source: https://doi.org/10.1016/S0300-9440(01)00155-2
21
 Etching

➢ Chemical process that strips copper cladding away from

unprotected regions
➢ Copper that remains after etching defines the board features such
as circuit traces and solder pads
➢ Etching operation
➢ Automated etching lines - etchant sprayed to the board at high velocities
➢ Alkaline ammonia (NH4OH) - most commonly used etchant
➢ Ammonium ions combine with copper to form cupric ammonium complex
ions [Cu(NH3)4+2] that hold dissolved Cu in solution
➢ Spent etchant with high concentrations of dissolved copper is recycled to
recover copper (important for environmental issues)
➢ After etching board is washed to remove the etchant and treated
with mild acid to neutralize the surfaces

22
 Etching

Watch Video: Click

23
 Pre-impregnated Bonding Sheet (prepeg)

• Woven fiberglass cloth pre-impregnated

with resin/hardener in solvent (partially
cured).
• Resin gets activated and "melts" during the
lamination process from pressure and heat
• Flows across copper features and exposed
laminate on the core
• Bonds the layers of foil and core together as it
cools

Source: https://predictabledesigns.com/introduction-to-pcb-assembly-using-surface-mount-technology-smt/ 24
 Lay-up and lamination

• Lay-up: Prepreg and inner layer cores

are aligned on pins in special precision
ground steel plates
• Lamination (also called pressing or
bonding) happens at high temperature
and pressure in vacuum
• Epoxy at 185°C, Pl at 250°C.

Watch Video: Click

Source: https://www.pcbastore.com/blogs/pcb-thickness.html 25
.....Will be continued in the next lecture

26
Lecture 8
23 September 2024

1
 Outer layer process-1

Source: https://ntrs.nasa.gov/api/citations/20180005658/downloads/20180005658.pdf 2
 Drilling and punching

➢ PCBs require large number of holes at the designed

locations
• Accommodate pins/leads
• Serve as vias for interconnection
• Mechanical attachments

➢ Holes formed by drilling or punching

➢ Punching is limited
• Single sided boards of XXXPC
• Quality of punched walls not suitable for plating
Source: Dally 1990

➢ Mechanical drilling
• Performed with computer-controlled precision drill bits

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
3
 Plating
➢Now we have drilled the holes, we need to plate the inner walls with
a conductor
• necessary to connect circuits on both sides of the board
➢Inner plating divided into 2 steps
• Electroless plating of copper
• Electroplating
➢Electroless plating
• Chemical deposition process - inner walls activated first by stannous and
palladium ions followed by deposition of thin layer (5-10μ) of copper
➢Electroplating
• Additional deposition of copper in an electrolytic solution where the through
holes form the cathode accepting Cu ions.

4
 Solder Mask
➢Heat resistant thin polymeric coating applied to the board to
prevent the deposition of solder in areas where solder joints are
not to be made
➢Functions:
• Prevents solder bridging between conductive tracks
• Controls outer layer impedance
• Minimizes handling damage during assembly
• Increases resistance to corrosion
• flammability resistance
• Improves board appearance

Watch Video: Click

5
 Solder Mask - process

• Film lamination uses photopolymer mask to expose areas to be

soldered
• Screening - uses a fine mesh screen (nylon of SS fibres)
➢Stencil film placed on top of the screen
➢Liquid polymer forced through the screen using a "squeegee".
➢Polymer coating dries and forms the mask

6
 Silkscreen or Screen printing
• The silkscreen is a layer on the surface of a PCB that is used
to identify a lot of information about the electronic printed
circuit board.
• The silkscreen is a layer of ink traces that typically includes
labels for the various components on the PCB, such as the
names of the connectors and the values of resistors and
capacitors. It may also include other information, such as the
PCB's title, the polarity of parts, and the test point locations.
• The silkscreen is applied to the component part of the
printed circuit board.

7
 Outer layer process-2

Source: https://ntrs.nasa.gov/api/citations/20180005658/downloads/20180005658.pdf
8
 Outer layer process-3

Source: https://ntrs.nasa.gov/api/citations/20180005658/downloads/20180005658.pdf
9
Final step - Component assembly

➢Assembly Components placed on the board by automated pick

and place machines
➢The board with the components undergo soldering process
➢Cleaning and coating

Watch Video: Click

10
Characterizing PCB (Printed Circuit Board)
materials
• Characterizing PCB (Printed Circuit Board) materials involves assessing
their physical, mechanical, thermal, and electrical properties to
ensure they meet performance and reliability standards.

11
 Required Material Properties
• Thermal Properties
• Mechanical Properties
• Thermal Conductivity
• Young's Modulus
• Density
• Poisson's Ratio
• Specific Heat Capacity
• Coefficient of Thermal Expansion, etc…
• Emissivity, etc....
Any layer inner via hole (ALIVH) board

Representing PCBs for Simulation

 Digital Image Correlation(DIC)
• Digital image correlation is a non-contact optical method which measures deformation on the surface of an object
• This method tracks the displacements in the speckle pattern in small neighborhoods called subsets (indicated in red
dot in the figure below) during deformation.
• Used to evaluate Coefficient of thermal expansion(CTE)

Bare Board White Base Black Speckles

PCB

Testing Dummy Sample

Sample

Thermocouple 1
DIC with Oven and Illumination System
Sample Inside Oven 14
 Warpage Measurements
Package Full Board Warpage Single Package Warpage

2D and 3D Warpage Graph at 50°C 2D and 3D Warpage Graph at 125°C Warpage Graph 50°C

Warpage Graph at 125°C

15
 DIC Results for CTE

0.0025
exx [1] - engr. 0.0025 exx [1] - engr.
eyy [1] - engr. eyy [1] - engr.
0.002 y = 2.09E-05x - 5.44E-04
0.002
Strain(mm/mm)

y = 1.78E-05x - 3.91E-04

Strain(mm/mm)
0.0015
0.0015 y = 1.85E-05x - 4.11E-04

0.001
0.001
y = 1.72E-05x - 3.93E-04
0.0005
0.0005

0
0
0 20 40 60 80 100 120 140
0 20 40 60 80 100 120 140
Temperature(°C)
Temperature(°C)
 Instron Micro Tester
• To perform static tensile and compression tests

Dog bone Sample Dimensions

Dimensions Value (mm)
L - Overall Length 100

C – Width of grip section 10

W – Width 6
Instron Micro tester Sample Mounted in a Grip
A – Length of Reduced
32
Section

B – Length of Grip Section 30

Dc – Curvature Distance 4

R – Radius of Curvature 6
Standard Dogbone Sample
17
 Dynamic Mechanical Analyzer

DMA 7100

• Used for measuring frequency and temperature dependent Loss modulus (measure of a material's
ability to dissipate energy) and Storage modulus (measure of the energy stored during the load
phase.) 18
 Dynamic Mechanical Analysis
• Study and characterize materials
• Most useful for studying the viscoelastic behavior of polymers
• A sinusoidal stress is applied and the strain in the material is measured
• Strain gives the complex modulus, E ( A measure of a material's stiffness, calculated as the ratio of stress
and strain amplitude.)
• Temperature of the sample and the frequency of the stress are varied
• Used to locate the glass transition temperature of the material

19
Recommended Sample Size Requirement - DMA

Bending Mode

Tension Mode

𝜶: Geometry factor (m)

S : Sample Cross-Section (𝑚𝑚2 )
l : Sample Length (mm) = 20
w: Sample width(mm) = 10

20
 Thermo-Mechanical Analyzer (TMA)

TMA6000

• Used for measuring coefficient of thermal expansion (CTE) and glass

transition temperature (Tg)
21
 Thermo - Mechanical Analysis
• Measurement of a change of a dimension or a mechanical property of the sample while it is subjected to a
temperature regime

• Characterize physical properties of materials when force is applied at specified temperatures and time
periods

• Involve selection of an appropriate probe type for measuring the properties of interest

• Coefficient of thermal expansion(CTE), melting point, softening point, glass transition

Fig. Different types of probes used in TMA

22
https://www.hitachi-hightech.com/global/products/science/tech/ana/thermal/descriptions/tma.html
 Recommended Sample Size Requirement - TMA
• Sample should be less than ~10 mm in diameter
• With the TMA specs given below, the required minimum
thickness as a function of CTE values is given in the figure
o Maximum sensitivity: 0.1 μm
o Maximum resolution: 3 nm
o Baseline drift (0°C - 500°C): 0.5 μm**
Source: “Determining Minimum Usable Sample Thickness in TMA”, TA
Instruments

Required Thickness for expected CTE Values

700

600
Minimum Thickness (um)

500

400

300

200

100

0
0 100 200 300 400 500
CTE (ppm)
Stage with Sample for Compression Test

** The temperature range and base line drift assumptions kept constant. The assumptions were provided for a similar TMA equipment, and the extrapolation 23
to different temperature ranges not necessarily linear because of the different factors affecting the measured values. See slide 9 for details.
 Nano Indenter

• Nanoindenter is a quasistatic indentation system for

nanomechanical testing of mechanical properties, including
Young’s modulus, hardness, wear, fracture toughness

Images from: Characterization Center for Materials and Biology. ccmb.uta.edu Images from: Hysitron Probe Selection Guide. https://www.hysitron.com/
Thermophysical property
• Laser Flash Analysis (LFA) – To measure thermal diffusivity
• Differential Scanning Calorimeter (DSC)- To measure Specific heat
capacity (Cp)
• Infrared Thermography- For Surface temperature distribution and
heat dissipation
• Fourier Transform Infrared Spectroscopy (FTIR)- To measure
Chemical composition changes with heat
• Dielectric Thermal Analysis (DETA)- To measure dielectric properties
as a function of temperature

25
System Integration

26
Motherboards and Daughter Cards
• Motherboard: Major circuit board in a system that houses components
and smaller (daughter) boards and expansion cards
• Daughter or Expansion cards: smaller circuit card assemblies with special
functionalities that can be plugged into mating sockets on the
motherboard PCMCIA cards, memory cards, ethernet cards, etc

Memory card
Motherboard 27
 Typical Daughter cards

Audio daughter card

Ethernet card
Memory cards

Power supply daughter card

Wireless network card 28
Connectors
➢ Electromechanical device providing a separable interface
between two electronic subsystems
• With minimal loss of power and signal integrity
• Plays vital role in performance and reliability

➢ Functions and Features

• Meet functional criteria (current, connections)
• Maintain temperature rating
• Durability - number of insertions and extractions https://www.santec.com/connectors
Withstand vibrations and shock
• Resistance to moisture ingress and corrosion

➢ Surface materials
• Ability to maintain performance and reliability
• Gold, Gold over Ni, Tin-lead solder, beryllium-copper-
nickel with gold, silver

29
 Connectors

SCSI

Ribbon cable
VGA

Rounded cable USB HDMI

30
 Enclosure assembly

➢Final housing for all systems and subsystems

• Protection from external forces
• Protection of internal components from EM radiation
• Amenable to field replacement
• Adequate air flow for efficient cooling
• Easy access to essential controls, ports, switches
• Indicators (LEDs) to indicate/alert for functioning/
malfunctioning/warning
• AESTHETICS

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
31
Different form factors

32
Aesthetic

33
END

34
Lecture 9
30 September 2024

1
 Heat Generation in Electronics Circuits
• Electronic circuits are composed of components such as resistors, capacitors, inductors, transformers,
semiconductors, integrated circuits (ICs), etc. All these components are responsible for the production of heat in
electronic circuits. (Q = VI = I2R).
• In the case of conductors used for making wires, cables, or traces, the electrical resistance is less, but, depending
on the current flowing through it, is still capable of generating heat.
• The electrical resistance of semiconductors is greater than conductors. The semiconductor components produce
heat as they operate, which challenges the reliability, performance, and safety of the circuit by increasing junction
temperature (die surface).

https://aldservice.com/Thermal-Management-Overview.html

• Extreme temperatures can cause thermal runaway or burn off the components, which results in permanent damage
to the circuit.
 Thermal Management of Electronic Devices
• In electronics, thermal management methods utilize the principles of thermodynamics and heat transfer to
control the temperature and noise in a circuit.
• Thermal management takes into account the materials (such as coolants or thermal interface materials), heat
sink, and different technologies to remove excess heat from the components to the surroundings.
• Thermal management focuses on how to efficiently remove heat by means of conduction, convection, or
radiation from the electronic component without interrupting the system’s performance.
• Thermal Management Classifications
• Product-level - This level consists of two sub-classifications: printed wire board-level, which includes the chips,
processors, components, etc., and the system-level, which mainly focuses on single and multiple rack-based systems
such as servers or data centers.
• Industry-level - This level addresses the electronic systems used in medical, automotive, defense, aerospace, and
consumer electronic systems. The thermal management in each industry places importance on board-level, system-
level, and component-level thermal management. However, the importance given to each level differs in different
industries. For example, medical electronics gives more priority to system-level thermal management, whereas
consumer electronics focus on component-level thermal management.

Source: Cadence
 Cooling load of electronic device
Electric power consumption of the electronic device, which
constitutes the energy input to the device

We = VI = I2R Watt

Heat dissipation or cooling load of an electronic device is equal to its

power consumption in the absence of other energy interactions.
In the absence of other energy
Q = We interactions, the heat output of an
electronic device in steady
Electronic equipment outputs other forms of energy as well, such as the operation is equal to the power
emitter tubes of a radar, radio, or TV installation emitting radiofrequency input to the device
(RF) electromagnetic radiation.

Q = We - RF

Thermal design power (TDP), also known as thermal design point, is defined as the theoretical maximum amount of
heat generated by a CPU or GPU that its cooling system is designed to dissipate

Source: Heat and Mass Transfer: Fundamentals and Applications, By Yunus Cengel and Afshin Ghaja
What is heat transfer
• Heat transfer is energy in transit due to a temperature difference
• Temperature gradient has to exist - heat flow will be in a direction so as to equalize the temperature
at various points.
• 3 Modes: Conduction, Convection, & Radiation
 Modes of Heat Transfer
Heat flows from a high-temperature region to a low-temperature region

Conduction:
• needs matter
• molecular phenomenon (diffusion process)

Convection
• heat carried away by bulk motion of fluid
• needs fluid matter

Radiation:
• does not need matter
• Transmission of energy by electromagnetic waves
 Conduction heat transfer
Rate equations:
• Heat transfer processes can be quantified in terms of appropriate rate equations.
• For heat conduction, the rate equation is known as Fourier’s law of heat conduction.
• Fourier’s law of heat conduction states that in a material in which temperature gradient exist, the heat flux (heat
flow per unit time per unit area) in any direction is proportional to the gradient of temperature.

𝑄 𝜕𝑇
∝ Where n is the direction under consideration
𝐴 𝜕𝑛 𝑛
𝑄 𝜕𝑇
= −𝑘 K is thermal conductivity of the material, W/m oC
𝐴 𝜕𝑛
Negative sign indicates the heat flow in the direction of decreasing temperature.
In a rectangular coordinates, Fourier’s law can be
𝑄 𝜕𝑇
= −𝑘
𝐴 𝑥
𝜕𝑥 Similarly for other coordinate systems
𝑄 𝜕𝑇 𝑄
= −𝑘 = −𝑘∇𝑇
𝐴 𝑦
𝜕𝑦 𝐴 𝑥
𝑄 𝜕𝑇
= −𝑘
𝐴 𝑧
𝜕𝑧
 Conduction Heat transfer
• Rate equations (1D conduction):
qx is the heat flux (W/m2) is the heat transfer rate in the x-direction per unit area (A) perpendicular
to the direction of heat transfer
𝑄 𝑑𝑇 qx A
𝑞𝑥 = = −𝑘
𝐴 𝑥
𝑑𝑥
• k is a transport property known as the thermal conductivity (W/m oC)
• For isotropic material K is same throughout the material
• Generally, for solids and liquid K is a function of temperature, k = f(T)
• For gases and vapour, k = f(T, P)
• We often use average k for calculation

Under the steady-state conditions, the temperature distribution is linear

𝑑𝑇 𝑇2 − 𝑇1 • T is in oC or K,
= • L is in m
𝑑𝑥 𝐿
𝑇2 − 𝑇1 𝑘 ∆𝑇
𝑞𝑥 = −𝑘 =
𝐿 𝐿
Steady-state, one-dimensional conduction through the wall, constant thermal conductivity
 Thermal Conductivity
• The thermal conductivity is a measure of a material’s ability to conduct heat .
• The thermal conductivity (k) of a material can be defined as the rate of heat transfer through a unit thickness of the
material per unit area per unit temperature difference.
𝑄𝐿 𝑊
𝑘=
𝐴∆𝑇 𝑚 𝑜𝐶

• For Copper: k = 385 W/moC

Taken literally, this means that for a 1-m length of copper whose cross section is 1 m2 and whose end points
differ in temperature by 1 oC, heat will be conducted at the rate of 385 watt (J/s) in copper.

ΔT =T1 – T2 = 1.0 oC
A =1.0 m2
T1 T2
Hot L = 1.0 m Cold

❑ A high value of K is a good heat conductor, and a low value of K is a poor heat conductor or insulator.
 Thermal Conductivity
• The thermal conductivity of a substance is normally highest in the solid phase and lowest in the gas phase.
• Crystalline solids such as diamond and semiconductors such as silicon are good heat conductors but poor electrical
conductors. Copper and silver that are good electric conductors are also good heat conductors.
• Liquid metals such as sodium, potassium and mercury have high thermal conductivities

Source: Heat and Mass Transfer: Fundamentals and Applications, By Yunus Cengel and Afshin Ghaja
 Thermal Conductivity
Variable Thermal Conductivity, K (T )
• Solids and liquid, k = f(T)
• For gases and vapour, k = f(T, P)
• The thermal conductivity of nonmetallic liquids generally decreases
with increasing temperature, except water.

For many materials, the thermal conductivity can be approximated as a linear

function of temperature over limited temperature ranges:

k(T) = k0(1 + βkT )

𝑇2
‫( 𝑜𝑘 𝑇׬‬1+𝛽𝑘 T) d𝑇 𝑇2 − 𝑇1
1
Kavg = = 𝑘𝑜 1 + 𝛽𝑘 = 𝑘 𝑇𝑎𝑣𝑔
𝑇2 − 𝑇1 2

where kav is the value of k at the average temperature (Tavg)

T1+T2
Tavg =
2
Note: We often use average k for calculation
Source: Principles of Heat Transfer, by
Frank Kreith, Raj M. Manglik, Mark S.
Bohn 2010
 Convection heat transfer
• The transfer of energy from one region to another due to macroscopic motion in a fluid added on to the energy
transfer by conduction is called heat transfer by convection

Ts >T∞

Convective heat transfer = Conduction (heat diffusion) + advection (heat transfer by bulk fluid flow)

Fluid is forced to flow over the surface by Fluid motion is caused by buoyancy forces that are induced by
external means (fan) density differences due to the variation of temperature in the fluid.
It is also called free convection
 Convection heat transfer
Newton’s law of Cooling
𝑄
∝ (𝑇𝑠 − 𝑇𝑓 ) T(y)
𝐴 Slope of the
temp. profile
𝑄
𝑞 = = ℎ(𝑇𝑠 − 𝑇𝑓 )
𝐴

q
h is heat transfer coefficient, W/m2oC (Not a constant)

h (depends on properties of fluid, velocity of flow, shape of the surface, nature of the surface)
𝜕𝑇
Slope of the temperature profile = 𝜕𝑦

𝑄 𝜕𝑇
−𝑘𝑓
𝐴 𝜕𝑦 𝑦=0
ℎ= =
(𝑇𝑠 − 𝑇𝑓 ) (𝑇𝑠 − 𝑇𝑓 )

Alternative definition for Newton law cooling

Convection heat transfer

Typical values of convective heat transfer coefficient

 Nusselt number
The Nusselt number is the ratio of convective to conductive heat transfer across a
boundary.

𝐶𝑜𝑛𝑣𝑒𝑐𝑡𝑖𝑣𝑒 ℎ𝑒𝑎𝑡 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟 ℎ 𝐴 ∆𝑇 ℎ𝐿

𝑁𝑢 = = =
𝐶𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑣𝑒 ℎ𝑒𝑎𝑡 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟 𝑘𝑓 𝐴∆𝑇/𝐿 𝑘𝑓

Nusselt number: Dimensionless heat transfer coefficient.

It provides a measure of the convection heat transfer occurring at the surface

• The Nusselt number represents the enhancement of heat transfer through a fluid layer as a result of
convection relative to conduction across the same fluid layer.
• The larger the Nusselt number, the more effective the convection.
• A Nusselt number of Nu = 1 for a fluid layer represents heat transfer across the layer by pure conduction.

15
Nusselt Numbers for Common Geometries
Typically, for Forced convection, the Nusselt number is expressed as a function of the Reynolds
number and the Prandtl number,

𝑁𝑢 = 𝑓(𝑅𝑒, 𝑃𝑟)
A common form of Nusselt number,

𝑁𝑢 = 𝐶 𝑅𝑒 𝑚 , 𝑃𝑟 𝑛
 Radiation
• Solid and liquid surface at all temperature emits thermal radiation.
• All object above absolute zero (-273 oC or 0 K) give off thermal
radiation
• The Hotter an object the more radiation it gives off.
 Radiation
• The maximum radiation flux emitted by a body at temperature T is calculated by Stefan–Boltzmann law
given by
𝐸 ∝ 𝑇4
𝑄
4
𝐸 = σ𝑇 𝐴
T
where σ Stefan–Boltzmann constant is 5.67 x 10-8 W/m2 K4
Where, T is absolute temperature in K

• The idealized surface that emits radiation at this maximum rate is called a blackbody, and the
radiation emitted by a blackbody is called blackbody radiation

• The radiation emitted by all real surfaces is less than the radiation emitted by a blackbody at the
same temperature,
𝑄
= ɛσ𝑇 4
𝐴
where ɛ is the emissivity of the surface and that value is in the range 0≤ ɛ ≤1,
 Radiation
Emissivities of some materials at 300 K

• Emissivity depends strongly on

the surface material and finish.
 Radiation
• Another important radiation property of a surface is its absorptivity, α
• Absorptivity is the fraction of the radiation energy incident on a surface that is absorbed by the
surface.
• The rate at which a surface absorbs radiation is
Qabsorbed = αQ incident

• A blackbody absorbs the entire radiation incident on it.

• A blackbody is a perfect absorber (α = 1) as it is a perfect emitter
• In general, both ɛ and α of a surface depend on the temperature and the wavelength of the radiation.
 Radiation
Radiation exchange between a surface and surrounding

Large surface area can be

T2, A2 approximated as a black body in
relation to the small area A1
𝑞2 = σ𝑇24

𝑞1 = ɛ1 σ𝑇14
A1, ɛ1, 𝑇1

• Radiation absorbed by the surface A1 is 𝛼1 𝐴1 σ𝑇2 4

Net radiation loss at the surface A1 is the difference between the energy emitted and energy absorbed
4
𝑄 = 𝜀1 𝐴1 σ𝑇14 − 𝛼1 𝐴1 σ𝑇2 watt

For ɛ1 = α1
4
𝑄 = 𝜀1 𝐴1 σ(𝑇14 −𝑇2 ) watt
…………Wil be continued in the next lecture
Lecture 10
02 October 2024

1
 Concept of heat flux
Another important quantity is the HEAT FLUX, which is the rate of heat transfer
per unit area.
Consider the silicon die in a IC Package below:
Power dissipated by the die = Q [Watts]
Area of the die = A [cm²]
Heat Flux: q" = Q/A [W/cm²]
• A Consider a CPU die:
Power: q" = 25 W
Area: A = 0.8 cm²

• Therefore, the heat flux through the die is: q" = 31.25 W/cm²

➢ Heat flux is critical because it offers detailed insights into the spatial
distribution of heat, ensuring better thermal management and the prevention
of overheating, which directly impacts the performance and reliability of
electronic devices.
https://doi.org/10.1016/j.tsep.2021.101182Get rights and content
Concept of thermal resistance
• Thermal resistance(electrical analogy)
OHM’s LAW: Flow of Electricity
Electrical

R
I

V1 V2

V1 > V2

Potential difference = Current flow × Resistance

ΔV = I × R
V1 - V2 = I × R
 Concept of thermal resistance
• Thermal Analogy to Ohm’s Law
Thermal

Rth
Heat
Q

T2
T1 Temperature
difference
T1 > T2

Temperature Difference = Heat Flow × Resistance

ΔT = Q × Rth
T1 - T2 = Q × Rth
𝑇1 − 𝑇2
𝑅𝑡ℎ =
𝑄
 Thermal resistance and Ohm’s law

Voltage A Temperature A

Current Heat
𝐸𝑙𝑒𝑐𝑡𝑟𝑖𝑐𝑎𝑙
𝐿 𝐶𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛
𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 = 𝐿
σ𝐴 𝑇ℎ𝑒𝑟𝑚𝑎𝑙 𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 =
𝑘𝐴

Voltage B Temperature B

𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝐴 − 𝑉𝑜𝑙𝑎𝑡𝑎𝑔𝑒 𝐵 Temperature 𝐴 − Temperature 𝐵

𝑅= 𝑅=
𝐶𝑢𝑟𝑟𝑒𝑛𝑡 𝐻𝑒𝑎𝑡 𝐷𝑖𝑠𝑠𝑖𝑝𝑖𝑎𝑡𝑖𝑜𝑛

Unit: Ohms Unit: OC/W

Concept of thermal resistance

1. Conduction thermal resistance

𝑇1 − 𝑇2 𝑇1 − 𝑇2 𝐿
𝑅𝑐𝑜𝑛𝑑 = = 𝑅𝑐𝑜𝑛𝑑 =
𝑄𝑐𝑜𝑛𝑑 𝑇 −𝑇 𝑘𝐴
𝑘𝐴 1 𝐿 2

2. Convective thermal resistance

𝑇1 − 𝑇2 𝑇1 − 𝑇2 1
𝑅𝑐𝑜𝑛𝑣 = = 𝑅𝑐𝑜𝑛𝑣 =
𝑄𝑐𝑜𝑛𝑣 ℎ𝐴(𝑇1 − 𝑇2 ) ℎ𝐴

3. Radiative thermal resistance

𝑇1 − 𝑇2 𝑇1 − 𝑇2 𝑇1 − 𝑇2
𝑅𝑅𝑎𝑑 = = 𝑅𝑟𝑎𝑑 =
𝑄𝑅𝑎𝑑 σε𝐴(𝑇14 − 𝑇24 ) σε𝐴(𝑇14 − 𝑇24 )
Plane Walls in Series
𝐿1 𝐿2
𝑅1 = 𝑅2 =
𝑘1 𝐴 𝑘2 𝐴

A
𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅1 + 𝑅2
T1
T2
1 2
𝑇1 − 𝑇2
𝑄=
𝑅𝑡𝑜𝑡𝑎𝑙

L1 L2 𝑇1 − 𝑇2
𝑄=
𝐿1 𝐿
+ 2
T1 T2 𝑘1 𝐴 𝑘2 𝐴
Q R1 R2
𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅1 + 𝑅2
 Plane Walls in parallel

𝐿 𝐿
𝑅1 = 𝑅2 =
𝑘1 𝐴1 𝑘2 𝐴2

Q
T2 𝑅1 × 𝑅2
T1 2 H2 𝑅𝑡𝑜𝑡𝑎𝑙 =
𝑅1 + 𝑅2
1 H1
L 𝑇1 − 𝑇2
𝑄=
R1 𝑅𝑡𝑜𝑡𝑎𝑙
T1 T2
Q

R2

1 1 1
= +
𝑅𝑡𝑜𝑡𝑎𝑙 𝑅1 𝑅2
Combined Heat Transfer- The Plane Wall
1
Th T1 𝑅1,𝑐𝑜𝑛𝑣 =
ℎ1 𝐴

𝐿
T2 𝑅2,𝑐𝑜𝑛𝑑 =
Tc 𝑘1 𝐴
Hot
fluid, 1
h1, Th 𝑅3,𝑐𝑜𝑛𝑣 =
Cold ℎ2 𝐴
fluid
L h2, Tc 𝑇ℎ − 𝑇𝑐
𝑄=
R2, Cond
𝑅𝑡𝑜𝑡𝑎𝑙
R1, Conv R3, Conv
Th T2 Tc
Q T1

𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅1,𝑐𝑜𝑛𝑣 + 𝑅2,𝑐𝑜𝑛𝑑 + 𝑅3,𝑐𝑜𝑛𝑣

 Combined Heat Transfer- The Composite Wall
1
𝑅1,𝑐𝑜𝑛𝑣 =
ℎ1 𝐴
Th T1
𝐿1
𝑅2,𝑐𝑜𝑛𝑑 =
𝑘1 𝐴
T4
Tc 𝐿2
𝑅3,𝑐𝑜𝑛𝑑 =
Hot 𝑘2 𝐴
fluid, k1 k2 k3
𝐿3
h1, Th L1 L2 L3 𝑅4,𝑐𝑜𝑛𝑑 =
Cold 𝑘3 𝐴
fluid 1
h2, Tc 𝑅5,𝑐𝑜𝑛𝑣 =
ℎ2 𝐴

Th R1, Conv R2, Cond R3, Cond R4, Cond R5, Conv Tc
Q T1 T2 T3 T4 𝑇ℎ − 𝑇𝑐
𝑄=
𝑅𝑡𝑜𝑡𝑎𝑙
𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅1,𝑐𝑜𝑛𝑣 + 𝑅2,𝑐𝑜𝑛𝑑 + 𝑅3,𝑐𝑜𝑛𝑑 + 𝑅4,𝑐𝑜𝑛𝑑 + 𝑅5,𝑐𝑜𝑛𝑣
Combined Heat Transfer- The Composite Wall
Convection and Radiation in Parallel
T1 𝑅5 × 𝑅6
ε
𝑅𝑒𝑞,𝑐𝑜𝑛𝑣, 𝑅𝑎𝑑 =
𝑅5 +𝑅6
T4

Hot
k1 k3
𝑇ℎ − 𝑇𝑐
fluid, k2 𝑄=
h1, Th L2 L3
𝑅𝑡𝑜𝑡𝑎𝑙
L1 Cold
fluid
h2, Tc
R6, Rad
Th R1, Conv R2, Cond R3, Cond R4, Cond Tc
Q T1 T2 T3 T4
R5, Conv

𝑅𝑡𝑜𝑡𝑎𝑙 = 𝑅1,𝑐𝑜𝑛𝑣 + 𝑅2,𝑐𝑜𝑛𝑑 + 𝑅3,𝑐𝑜𝑛𝑑 + 𝑅4,𝑐𝑜𝑛𝑑 + 𝑅𝑒𝑞,𝑐𝑜𝑛𝑣, 𝑅𝑎𝑑

 Example problem #1
Consider the following package configuration with a silicon die attached to a thermal plate with a TIM
(thermal interface material). The die is dissipating power, and the heat is lost from the thermal plate
surface. What is the die temperature (Tj)?

Solution:
Fluid Copper thermal plate
Flow 1 1
h = 400 W/mK 𝑅𝑐𝑜𝑛𝑣 = = = 6.66 𝑂𝐶/𝑊
Ta= 30oC h = 60 W/m2K ℎ𝐴 (60)(50 × 50 × 10−6 )

𝐿 5 × 10−3
𝑅𝐶𝑢,𝑝𝑙𝑎𝑡𝑒 = = −6
= 0.005 𝑂𝐶/𝑊
𝑘1 𝐴 (400)(50 × 50 × 10 )
50 mm X 50 mm X 5 mm TIM, K= 1 W/m-K, BLT=0.05 mm
𝐿 0.05 × 10−3
Q= 10 W
Si die, K= 120 W/m-K 𝑅𝑇𝐼𝑀 = = = 0.22 𝑂𝐶/𝑊
𝑘1 𝐴 (1)(15 × 15 × 10−6 )
15 mm X 15 mm X 0.5 mm

𝐿 0.5 × 10−3
𝑅𝑆𝑖 = = = 0.02 𝑂𝐶/𝑊
𝑘1 𝐴 (120)(15 × 15 × 10−6 )
 …Continued from previous Example problem #1

= 30 oC
𝑇𝑗 − 𝑇𝑎
6.66 𝑂𝐶/𝑊 𝑄=
𝑅𝑡𝑜𝑡𝑎𝑙

0.005 𝑂𝐶/𝑊 𝑇𝑗 − 30
10 =
6.9
0.22 𝑂𝐶/𝑊
𝑇𝑗 = 6.9 × 10 + 30
0.022 𝑂𝐶/𝑊
𝑇𝑗 = 99 𝑂𝐶

𝑅𝑡𝑜𝑡𝑎𝑙 = 6.66 + 0.005 + 0.22 + 0.022 = 6.90 𝑂𝐶/𝑊

 Example problem #2
• Compare the heat transfer from the lid of an electronic package by convection and radiation to an
infinite enclosure, when the lid temperature is uniform at 75°C and the ambient temperature is 25°C.
Assume that lid size is 50 × 50 × 2 mm, the heat transfer coefficient is 100 W/m2K, and the lid
emissivity is 0.8.
Solution:
Area of lid = 50 mm × 50 mm = 2500 mm2 = 2500 × 10−6 m2

QConv = hA(Th − Tc) = (100 W/m2K)(2500 × 10−6 m2)(75°C − 25°C) = 12.5 W`

First, convert the temperatures to Kelvin. Then Stefan–Boltzmann law, from with A1/A2 << 1:
4
𝑄𝑅𝑎𝑑 = 𝜀1 𝐴1 σ(𝑇14 −𝑇2 )
𝑄𝑅𝑎𝑑 = 0.8 2500 × 10−6 5.67 × 10−8 75 + 273.15 4
− 25 + 273.15 4
= 0.77 𝑊

𝑄𝑅𝑎𝑑 0.77
= = 0.0616
𝑄𝐶𝑜𝑛 12.5

Comparing the heat transfer rate by convection to radiation shows that convective heat transfer is over an
order of magnitude greater than radiative heat transfer. In this example, one could ignore radiation without
suffering too great a loss in accuracy.
 …Continued from previous Example problem #2

Incase, h = 10 W/m2K (natural convection), what is Q?

Area of lid, A = 50 mm × 50 mm = 2500 mm2 = 2500 × 10−6 m2

QConv = hA(Th − Tc) = (10)(2500 × 10−6)(75 − 25) = 1.25 W`

First, convert the temperatures to Kelvin. Then Stefan–Boltzmann law, from with A1/A2 << 1:
4
𝑄𝑅𝑎𝑑 = 𝜀1 𝐴1 σ(𝑇14 −𝑇2 )

𝑄𝑅𝑎𝑑 = 0.8 2500 × 10−6 5.67 × 10−8 75 + 273.15 4

− 25 + 273.15 4
= 0.77 𝑊

𝑄𝑅𝑎𝑑 0.77
= = 0.616
𝑄𝐶𝑜𝑛 1.25

Comparison of the heat transfer rates by natural convection and radiation shows that both
are significant. In this case, the heat transfer by radiation cannot be ignored.
 Flip Chip BGA

Heat Sink

TIM 2
TIM 1
Solder Connections Lid/case/IHS

Junction
Substrate Die (Die surface)

PCB
16
Commonly used nomenclature
θxy = X to Y thermal resistance
Package internal resistance(Rint) or junction-to-case(𝜃𝑗𝑐 ):
❑ X and Y could be 𝑇𝑗 − 𝑇𝑎
➢ a: ambient 𝜃𝑗𝑐 =
𝑄
➢ b: PCB board θca θja
➢ c: case θjc System external resistance (Rext) or case-to-ambient(𝜃𝑐𝑎 )
➢ j: junction
➢ l: lid 𝑇𝑐 − 𝑇𝑎
𝜃𝑐𝑎 =
➢ p: thermal plate 𝑄
➢ s: heat sink
Total resistance (Rtotal) or junction-to-ambient(𝜃𝑗𝑎 ):
𝑇𝑗 − 𝑇𝑎
𝜃𝑗𝑎 =
𝑄

Thus, 𝜃𝑗𝑎 = 𝜃𝑗𝑐 + 𝜃𝑐𝑎

 Understanding Heat Transfer Paths

• Unlike electrical current that only travels through electrical

conductive paths - heat goes everywhere!

• Key to good thermal design & experimentation - understand

how & where heat flows and quantify it
 Understanding Heat Transfer Paths

Source: https://semiengineering.com/what-i-learned-about-heatsinks-using-thermal-simulation/
 Thermal Resistance Network: PPGA Example

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing
 Thermal Architectures

Integrated
Underfill heat spreader
(IHS)

Substrate

ARCHITECTURE I - Bare Die ARCHITECTURE II - Integrated Heat

attach Spreader
• Heat sink interfaces with CPU • Heat sink interfaces with IHS
• Useful for mobile applications • Two interfaces

Source: https://doi.org/10.1002/adma.202311335
 Understanding Heat Transfer Paths
• Consider the PPGA package

Cu Heat spreader
Substrate

Kovar Pins
 Understanding Heat Transfer Paths

Source: Jha, C.M. and Sanchez, J.A., 2015. Microprocessor Temperature Sensing and Thermal Management. Thermal Sensors: Principles and Applications for
Semiconductor Industries, pp.57-96.
 Example problem #3
For the electronic package shown in the below Figure, determine the chip temperature Tj.

Source: Rao Tummala 2019

 …Continued from previous Example problem #3
Solution:

𝜃𝑗𝑎,1 = 𝜃𝑗𝑐 + 𝜃𝑐𝑎

1
𝜃𝑗𝑎,2 = 𝜃𝑗𝑏 + 𝜃𝑏𝑎
1 1 1
= +
2 𝜃𝑗𝑎 𝜃𝑗𝑎,1 𝜃𝑗𝑎,2
𝑇𝑗 − 𝑇𝑎
𝑄=
• Comparing the resistance of the upward heat transfer 𝜃𝑗𝑎
path 𝜃𝑗𝑎,1 = 𝜃𝑗𝑐 + 𝜃𝑐𝑎 = 0.3°C/W to the downward
heat transfer path 𝜃𝑗𝑎,2 = 𝜃𝑗𝑏 + 𝜃𝑏𝑎 = 1.5°C/W , 𝑇𝑗 = 𝑄 × 𝜃𝑗𝑎 + 𝑇𝑎
it can be understood that 80 % of the heat escapes
upward.
Use θjc = 0.1°C/W, θca = 0.2°C/W, θjb = 0.5°C/W, θba = 1°C/W,
• If the bottom of the printed circuit board was Q = 100 W, and Ta = 30°C.
insulated such that no heat could be transmitted
through the board, the chip temperature Tj would 𝑇𝑗 = 100 × 0.25 + 30
have increased to 60°C. 𝑇𝑗 = 55 𝑜𝐶
• Other topics will be discussed in the next class
Advanced Heterogeneous Packaging:
Needs and Challenges

Akshay Lakshminarayana,
Ph.D. in Mechanical Engineering,
University of Texas at Arlington
 Moore’s law & Dennard’s Scaling
• Gordon Moore predicted in 1965 that number of transistors per Integrated
Circuit doubles every year
• He later revised this to doubling every two years (in 1975) [1]
• Dennard’s scaling exemplifies Moore’s law by proving when transistors scale,
their power density remains constant as both voltage and current scale down
with transistor length
• Transistor dimensions (scales by a factor of 0.7) and area reduces by 51%
• Capacitance (C), Voltage (V), Current scale down by same factor (0.7)
• Frequency (f) increases by 40% (1.4 scale up) as it is inverse of delay time
• Power consumption of individual transistor decreases by 51% (Active Power =
CV2f)
• Therefore, for double the transistors power remains same [3]

Figure 1: Moore’s law plot from 1965 [2]

Figure 2: transistors Innovations over time at Intel [1]
Sources: [1] https://ourworldindata.org/moores-law
[2] https://www.intel.com/content/www/us/en/newsroom/resources/moores-law.html#gs.d1a79y
[3] Borkar, Shekhar; Chien, Andrew A. (May 2011). "The Future of Microprocessors". Communications of the ACM.
2
Transistors Innovation at Intel

Figure : Transistors Innovations over time at Intel [1]

Sources: [1] https://ourworldindata.org/moores-law
3
 Transistor Density & Process nodes on Apple Chips

• The density of transistors has

increased from 3B to 15B
• Transistor gate length has decreased
from 14nm to 5 nm
• A10 - 125 mm2
• A11 – 89 mm2
• A12 – 83 mm2
• A13 – 98.5 mm2
• A14 – 88 mm2
• A15 – 98 mm2
 Exponentially Increasing Design Cost with Transistor
Scaling

• The design cost

increased to 542$
for 5nm transistors
• It has increased to
more than a billion
dollars for 2 nm
transistor process
nodes
 End of Moore’s law & Dennard’s Scaling

• Moore’s law economics & performance are

plateauing
• Dennard’s scaling stopped following the trend as
voltage scaling stopped and leakage current causes
static power loss in the circuit, in turn leading to
thermal runaway [1]
• 80% increase in cost for a 250 mm2 Die from 45nm
node to 5 nm node
• Dennard’s scaling ends as power density is a
constraint
• New packaging architectures with Heterogenous
Integration
• Alternatives to Silicon (such as GaAs) for efficient Figure 1
energy scaling Figure 1: Transistor density in DRAMs over years [2]
Source: [1] https://cartesianproduct.wordpress.com/2013/04/15/the-end-of-dennard-scaling/
Source: [2] https://eri-summit.darpa.mil/docs/20180724_0805_Hennessy.pdf
6
Heterogeneous Integration of Chiplets

Figure : Improved yield with HI approach

Source: R. Swaminathan, “The next frontier: Enabling Moore’s Law using heterogeneous integration”
7
Yield Improvement with HI Approach

Figure : Improved yield with HI approach

Source: R. Swaminathan, “The next frontier: Enabling Moore’s Law using heterogeneous integration” 8
PPAC (Power, Performance, Area, Cost)

Figure : Improved yield with HI approach

Source: R. Swaminathan, “The next frontier: Enabling Moore’s Law using heterogeneous integration”
9
Heterogeneous Integration over Traditional Packaging Technologies

The key advantages of chiplets heterogeneous integration are:

➢ Yield improvement (lower cost) during manufacturing;
➢ Faster time-to-market;
➢ Cost reduction during design;
➢ Better thermal performance (has its own challenges)

The key disadvantages are:

➢ Additional area for interfaces
➢ Higher packaging costs
➢ More complexity and design effort
➢ Past methodologies are less suitable for chiplets
 System on Chip (SoC)

SoC integrates all components of a

system onto a single silicon chip.
Advantages:
Home gaming consoles like PlayStation
and Xbox ✓ Small and Highly Integrated
✓ Cost-Effective per device
➢ CPU
➢ GPU Disadvantages:
➢ Memory • Lack of Flexibility
➢ USB Controller • High development cost
➢ Power Management Circuits • Complex & limited scope
System on Chip (SoC)
➢ Wireless Transceivers
 Package on Package (PoP)

• PoP stacks multiple semiconductor packages Advantage:

using a standard interface ✓ Space constrained applications
• Generally, memory on top of a processor
• Allows for higher density in smaller footprint & Disadvantages:
quicker communication • Limited Device Integration
• Manufacturing Challenges (Alignment and
• Smartphones use this to save space handling)

Package on Package (PoP)

 System on Module (SoM)
• SoM integrates multiple packaged SoCs on to a single module.
• Includes microprocessor, memory, I/O interfaces
• Combines functional complexity and processing power of
several SoCs
• Allows for higher density in smaller footprint & quicker
communication
• Industrial automation systems use this method

Advantages:
✓ Quick development of a complete compute system
✓ Shorter T-2-M

Disadvantages:
• Higher cost System on Module (SoM)
• Larger size
• Assembly challenges and complexity in designs
 System in Package (SiP)
• Essentially integrating multiple SoCs or chiplets at silicon level
• Incorporates various functions such as digital, analog, mixed
signals, RF in a confined space
• Similar to PoP, but faster chip performance due to shorter
connectivity
• Advanced camera systems in smartphones (require multiple SoCs
for image processing). Stacking, high speed data processing,
reduced form factor

Advantages:
✓ Area reduction
✓ Lower total cost System in Package (SiP)
✓ Standard Assembly
Disadvantage:
• Does not offer flexibility with customization and component selection
 2.5D Integration
• Enables higher density of interconnects
• No wire bonds – uses TSVs and RDLs
• Active and passive interposers
• Interposer is either a full-sized passive Si or die to
die Si bridges (Intel’s EMIB)
• EMIBs are size of a rice grain and a combination
of both substrate and interposer

Silicon Interposer based 2.5D Integration

• Reduced size
• Shorter interconnects results in higher speed and
lower power usage
• Heterogeneous integration
• CTE match between die and interposer reduces stress

• Complex integration scheme

• Need for improved thermal management
• Reliability issues
• Higher costs
Embedded Multi-die Interconnect Bridge (EMIB) based 2.5D Integration by Intel
N. Margalit, C. Xiang, S. Bowers, A. Bjorlin, R. Blum, and J. Bowers , "Perspective on the future of silicon photonics and electronics", Appl. Phys. Lett. 118, 220501 (2021)
Mahajan, Ravi, et al. "Embedded multi-die interconnect bridge (EMIB)--a high density, high bandwidth packaging interconnect." 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). IEEE, 2016. 15
 Interposers in 2.5D
Organic Interposers :

• Poor mechanical properties such as strength and moduli

• Challenge to fabricate finer pitch (below 5 µm)
• Highest CTE mismatch with silicon die
• 2 to 3$ cost of making
Silicon Interposers :
• Higher electrical loss for high-performance applications
• High costs and limited wafer size (100 to 300 mm, largest wafer size 450 mm not in use yet)
• 30$ to 100$ depending on number of chiplets [2]

Glass Interposer :

• Better electrical properties, low loss

• Low cost, panel-based mass production
• High thermal resistance, optical transmission
• Has wafer sizes of about 2400 mm x 2800 mm [3]

Source: [1] https://f450c.org/infographic/

[2] https://semiengineering.com/return-of-the-organic-interposer/ 16
[3] MANUFACTURING OF THREE-DIMENSIONAL PACKAGED SYSTEMS, Chapter 2
 Interposers in 2.5D
• Warpage study on different materials for interposers
• Stress impact from interposers on the solder ball

Warped substrate

HBM die, 4x4x0.5 mm ASIC die, 12.5x12.5x0.5

mm
C2 microbumps
50x50x50 um

Interposer
22.5x22.5x0.3
mm

Source: [1] https://f450c.org/infographic/ Copper Pads Substrate, C4 bumps,

[2] https://semiengineering.com/return-of-the-organic-interposer/ 80 um dia, 20um thick 22.5x22.5x0.25 mm 80 um dia, 120um pitch
[3] MANUFACTURING OF THREE-DIMENSIONAL PACKAGED SYSTEMS, Chapter 2 17
 2.5D Integrated Packages in Industries

The very first 2.5D heterogenous

AMD’s GPU (Fiji), Hynix’s NVIDIA’s P100 with Samsung’s Interposer-
package by Xilinx has 2 million
HBM, UMC’s Interposer TSMC’s CoWoS-2 and Cube-4 2.5D IC
logic cells, 4-layer metal Si
integrated onto one Samsung’s HBM2. Integration
interposer, 4 FPGA sub dies. Source: . G. Lenihan, L. Matthew and E. J.
Source: . G. Lenihan, L. Matthew and E. J. Vardaman, package. Source: . Source: . John Lau, Recent
Vardaman, "Developments in 2.5D: The
"Developments in 2.5D: The role of silicon Source: ., John Lau, Recent Advances and Advances and Trends in Advanced Packaging,
2022 role of silicon interposers," 2013 IEEE
interposers," 2013 IEEE 15th Electronics Packaging Trends in Advanced Packaging 2022 15th Electronics Packaging Technology
Technology Conference (EPTC 2013), Singapore, Conference (EPTC 2013), Singapore,
2013 2013

18
3D IC Packages
 Thermal Challenges in 2.5D/3D IC Chiplets Package

• With transistor scaling, non-

uniform heating temperature
distribution and localized
hotspots is a problem
• Limited space for heat
dissipation as one end is used
for electrical interconnection
Increasing power density with transistor scaling
• High temperature rise due to
high power density of chips in
the same footprint area
• Thermal cross-talk between
dissimilar dies and modules
with different functionalities Increasing delta T with non-uniform heating

Thermal Cross-talk between high power XPU and HBM 20

 Advanced Cooling Solutions for 3D ICs
• Interlayer Cooling to target the heat in the middle and bottom of 3D stack
• Microchannel cavities are glued to the dies using bonding materials such as polyimide, with TSVs running through
microchannel walls
• Integrated microchannel heat sinks can be used with fluid flowing through TSVs to remove heat from the middle dies in
the stack

Microchannel cavities bonded between dies [A] Integrated Microchannel heat sink [B]

A. Sridhar, A. Vincenzi, D. Atienza and T. Brunschwiler, "3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs," in IEEE Transactions on Computers, vol. 63, no. 10, pp. 2576-
2589, Oct. 2014
B. C. R. King, J. Zaveri, M. S. Bakir and J. D. Meindl, "Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," 2010 Proceedings 60th Electronic Components and Technology
Conference (ECTC), Las Vegas, NV, USA, 2010 21
 Reliability Challenges in Advanced HI Packages

• Thermal / Mechanical Induced failure mechanisms

• Overstress and Wearout causes
• Brittle cracking in chips, dielectrics, mold compounds
• Fatigue cracking in interconnects (solders, TSVs)
• Delamination between layers (adhesives, dielectrics,
conductors, mold compounds)
• Excessive warpage – misalignment, loss of contact,
CTE mismatch
• Thermal management – melting, CTE mismatch
• Electrical, Chemical, Radiation and other reliability
concerns

22
 Interconnects
• Interconnects – connects transistors and other components to deliver
signals and power
• Faster power & signal transfer-----> chip performance ↑
• Transistor scaling <===> Interconnect scaling

• Solder ball interconnects are limited to 25um pitch [1]

• Reliability issues due to CTE mismatch, warpage, die shift
• Reduced bump height and surface area is not achievable
• Lower surface area for bonding making manufacturing difficult

• Cu-Cu Hybrid bonding follows TCB (Thermocompression Bonding) ---->

easier to create bonds in small area
• Finer pitch (up to 10 um can be achieved)

Wire bond interconnects and Solder ball

[1]: Microelectronics and Advanced Packaging Technologies Roadmap, Semiconductor
Research Corporation, 2023 interconnects 23
Advanced Bump-less Cu-Cu Hybrid Bonding

Interconnect Scaling over the years

Source: https://www.eetimes.com/the-role-of-interconnection-in-the-evolution-of-advanced-packaging-technology/ 24
 Advantages & Challenges with Hybrid Bonding
Advantages of Cu-Cu Hybrid bonding:
• Solder-Free bonding: lowers resistance
by reducing bonding layer thickness
• Fine Pitch Capability: Increases I/O
density
• Advanced Thermal Capability: enhances
heat dissipation with increased density
• Reduced form factor: smaller package
size

Challenges involved:
• Improve particle control at nanoscale to
ensure robust quality Source: Semiconductor Advanced Packaging, 2021

• Maintain flatness of bonding layer to

J. H. Lau, Chiplet Design and Heterogeneous Integration Packaging.
avoid failures Singapore: Springer Nature Singapore, 2023. doi: 10.1007/978-981-19-9917-8

25
Advantages & Challenges with Hybrid Bonding
 Immersion Cooling Technologies
• Single-phase Immersion fluids are easy to handle, low toxicity and GWP
• Two-phase immersion has higher cooling capacity, but fluids are toxic

Single Phase Immersion Schematic Two Phase Immersion Schematic

27
Source: TMG Core White Paper 1: Approaching the Heat Limit with Liquid Immersion Technology
 Why Substrate Reliability is Important?

• Reliability of substrates are critical at package

level and at board level
• Substrates mechanically support the package and
provides electrical connections between
components and interconnects
• Thermo-mechanical properties like modulus, CTE
plays an important role
• Little to no data available on the mechanical
behavior of substrates in Two-phase Immersion
Cooling environment

28
Material Characterization
 I-Speed Substrates in Fluid-1
I-Speed Substrates in Fluid-1
• 4 Samples each aged in Fluid-1 1.2

and Air at room temperature 1.0

and 45 °C
• Average modulus of 4 samples 0.8

Normalized Modulus
are plotted
0.6
• Complex modulus of samples
aged at RT is 20.2% higher 0.4 Immersed RT
than air Immersed 45°C
• Complex modulus of samples 0.2
Non-Immersed
immersed in Fluid-2 at 45°C is
0.0
24.2% higher than air -50 0 50 100 150 200 250
Temperature (°C)

30
 Reliability of HDI copper Microvia in Printed circuit boards

• Blind microvia insufficient annealing of Copper, reflow

process thermal loading
• Sensitivity analysis using optislang, Equivalent and max
principal stress
• Y CTE and Modulus of Dielectric layer
• Experimental measurement of modulus on Nano
indenter

31
 Key Takeaways

• Heterogeneous Integration > Traditional Packaging

• Thermal and Mechanical Reliability challenges involved with advanced packages
• Hybrid bonded Interconnects is a promising technology in today’s industry
• 2.5D/ 3D chiplets integration is the better for increasing functionality
• Embedded cooling, Integrated Micro-channeled heat sink, microfluidic cooling
are being researched
• Reliability issues can be mitigated by optimization of design and materials
THANK YOU