set search_path
"/synopsys/GPDK/SAED_EDK90nm/Digital_Standard_cell_Library/synopsys/models/"
set link_library "saed90nm_max.db"
set target_library "saed90nm_max.db"
set symbol_library "saed90nm_max.db"
analyze -library WORK -format verilog ./s38584_seq.v
elaborate seq -architecture verilog -library WORK
source ./_con.sdc
check_timing
set_load 1 [all_outputs]
set_scan_configuration -style multiplexed_flip_flop
link
compile_ultra -scan -gate_clock -no_autoungroup
report_timing
set test_default_strobe 1
set test_default_period 60
set_dft_signal -view existing_dft -type ScanClock -timing [list 2 3] -port clk
set_dft_signal -view existing_dft -port reset -type RESET -active_state 1
create_port si -dir IN
set_dft_signal -view spec -port si -type ScanDataIn
create_port so -dir OUT
set_dft_signal -view spec -port so -type ScanDataOUT
create_port se -dir IN
set_dft_signal -view spec -port se -type ScanEnable
create_test_protocol
dft_drc
set_scan_configuration -chain_count 1
preview_dft
insert_dft
dft_drc -coverage_estimate
write_test_protocol -o s38584.spf
report_power > s38584Power.rpt
report_timing > s38584Timing.rpt
write -hierarchy -format verilog -output "s38584_syn.v"
exit
