Double Data Rate 5 Physical layer

(DDR5 PHY)
Supervised by: Dr. Hesham Omran
Sponsored by : Si-Vision
Presentation date: Jul 18, 2022
 DDR5 PHY
OUTLINE
1. Introduction to Memories.
2. Standard Specifications.
3. DDR5 PHY Blocks.
4. System Integration.
5. FPGA flow.

Jul 18, 2022 2

 Memories

• Memory is a device or system that is used to store data in computer or related computer
hardware and digital electronic devices.

• The data is stored as a stream of bits and each bit is either a zero or a one.

• The smallest storing element in the memory can store only 1 bit, it is called “cell”.

• We are interested in Random Access Memory (RAM) .

Jul 18, 2022 3

 Structure of DRAM

Jul 18, 2022 4

 DIMM structure

DIMM structure showing chips, banks and arrays(3)

Jul 18, 2022 5

 SDRAM Types

• SDRAM was first known as SDR SDRAM since data is transferred only once in each clock cycle.

• DDR SDRAM (Double Data Rate) is the advanced version of SDRAM that transfers data on both the rising
and falling edges twice as fast as compared to SDR SDRAM chips.

• After the introduction of DDR new generations were introduced (DDR2 : DDR5), these generations have
different internal structure to achieve higher data rates.

Jul 18, 2022 6

 DDR subsystem

PHY connecting the MC to DRAM(4)

Jul 18, 2022 7

 DDR5 PHY
OUTLINE
1. Introduction to Memories.
2. Standard Specifications.
1. Standards.
2. Frequency ratio
3. Subsystem point of view.
4. Write operation Flow.
3. DDR5 PHY Blocks.
4. System Integration.
5. FPGA flow.

Jul 18, 2022 8

 Standards

• The DDR PHY Interface (DFI) is an interface protocol that defines the signals, timing parameters
and programmable parameters.

• The DFI specify the signals between MC and PHY, these signals is organized to interface groups,
within each interface group are signals and parameters. Some signals are applicable only to
certain DRAM types. All of the DFI signals must use the corresponding parameters.

• Joint Electron Device Engineering Council (JEDEC) standard defines the “DDR5 SDRAM”
specifications

Jul 18, 2022 9

 Frequency ratio

Frequency ratio 1:2 and 1:4 from DFI v5.0 - Frequency Ratio Clock Definition(1)

Jul 18, 2022 10

 CRC Flow

• CRC can be generated by MC or PHY “default MC”

• PHY defines the value of PHY crc_mode and according to this value CRC is handled
o PHY crc_mode = 0 → CRC generation is handled in the MC
o PHY crc_mode = 1 → CRC generation is handled in the PHY

• In BC8 mode, read CRC and write CRC bits are calculated with the inputs to the CRC engine for the
chopped data bursts replaced by all '1's, as shown in figure 16.

Jul 18, 2022 11

 Sub system point of view

• Signal mapping:
o Dfi_address -> CA [13:0].
o Dfi_cs_n -> CS_n.
o Dfi_wrdata -> DQ.
o Dfi_wrdata_mask -> DM.
o Dfi_reset_n -> RESET_n.

Jul 18, 2022 12

 Whole Write operation flow from MC to DRAM

Jul 18, 2022 13

 DDR5 PHY
OUTLINE
1. Introduction to Memories.
2. Standard Specifications.
3. DDR5 PHY Blocks.
1. Frequency Ratio.
2. Command Address.
3. Write Manager.
4. CRC
4. System Integration
5. FPGA flow

Jul 18, 2022 14

 Block Diagram

Jul 18, 2022 15

 Frequency Ratio Block Diagram

Jul 18, 2022 16

 Timing Diagram

Jul 18, 2022 17

 Block Architecture

Jul 18, 2022 18

 Simulation Results

Jul 18, 2022 19

 Command Address Block Diagram

Jul 18, 2022 20

 Timing Diagram

This case is mode register write command to change pre-amble and post-amble followed by
another mode register write command to change the dram CRC enable.

Jul 18, 2022 21

 Block Implementation

• We introduced two approaches to implement this block:

o First approach is to implement this block using finite state machine (FSM), the FSM is
consist of 4 states.

Jul 18, 2022 22

 Block Implementation

o Second approach is implementing the block using a combinational and sequential

elements, e.g. multiplexers and registers.

Jul 18, 2022 23

 Simulation Results

This case is write command followed by mode register write command to change pre-amble and
post-amble after that mode register write command is inserted to change the dram CRC enable.

Jul 18, 2022 24

 Design Optimization

The block is synthesized on Design Compiler (DC) using 130 nm technology.

Design parameter First Approach Second Approach

Number of combinational cells 213 187

Number of sequential cells 51 52

Number of cells 264 239

Total area (um)2 88700 84500

Total dynamic power (mW) 1.68 1.67

Cell leakage power (uW) 2.5 2.2

Total power (mW) 1.689 1.675

Longest path slack (clk period 30 +0.02 +2.95

ns)

Jul 18, 2022 25

 Write Manager Block Diagram

Jul 18, 2022 26

 Write Manager Internal Connections

Jul 18, 2022 27

 Write FSM Module Block Diagram

Jul 18, 2022 28

 Write FSM State Diagram

Jul 18, 2022 29

 Write Shift Block Diagram

Jul 18, 2022 30

 Write Shift block Functionality and Description

• This block is responsible for 3 main operations:

1. Shifting preamble pattern.

Jul 18, 2022 31

 Write Shift block Functionality and Description
2. Calculating gap (no of cycles at which write enable is low):
o When wr_en_i becomes low, counter will start to count, the value of counter will be stored in gap_register.
o After wr_en_i becomes high, we will reset the counter and check the value stored in register to detect the
correct interamble_pattern according to the gap value.
3. Shifting interamble pattern.

Jul 18, 2022 32

 Write Counters Block Diagram

Jul 18, 2022 33

 Write Counters Functionality and Implementation

• Write counters block is responsible for:

o generating done signals which will be used in transitions between different states in write FSM block.
o Determining either if there will be an inter-amble or not.
o Determining whether there will be a CRC code generation to the DRAM or not.

• This block consists of 3 counters:

o Preamble Counter
o Write Data Counter
o Interpost Counter

Jul 18, 2022 34

 Counter 1: Preamble Counter

• Pre-amble counter works simultaneously with write enable signal independent on the state.
• Activating write enable signal means there is a data coming after 6 cycles. So, preamble
counter start counting

Jul 18, 2022 35

 Counter 2: Write Data Counter

• write data counter only counts in data state especially when write enable is de-activated.
• After 5 cycles from de-activating write enable in data state, the full data burst will finish, and a
done signal will be activated high telling the controller to move from data state.

Jul 18, 2022 36

 Counter 3: Interpost Counter

• This counter counts only during inter-amble state and post-amble state.
• Post-amble and inter-amble states cannot occur at same time. This illustrates the reason for
using one counter for them both.

Jul 18, 2022 37

 Simulation Results

This case is burst length 16 (BL16) with PHY CRC generation.

Jul 18, 2022 38

 Simulation Results

This case is burst length 8 (BL8) with PHY CRC generation.

Jul 18, 2022 39

 Simulation Results

This case is burst length 16 (BL16) with Mask operation.

Jul 18, 2022 40

 Optimization

First Approach Second Approach

Number of cells 629 474
Number of combinational cells 515 408
Number of sequential cells 111 63
Combinational area(um)2 6036.47 3427.72
Total cell area(um)2 8291.02 5099
Total area(um)2 197,011.97 170,580.64
Switching Power(mW) 0.48 0.25
leakage Power(uW) 8.20 3.95
Total Dynamic Power(mW) 1.18 0.55
slack 0.00 (MET) 0.8 (MET)

Jul 18, 2022 41

 CRC Block Diagram

Jul 18, 2022 42

 First approach architecture: XOR CRC

Jul 18, 2022 43

 Second approach architecture : Feedback CRC

Jul 18, 2022 44

 Timing diagram

Jul 18, 2022 45

 Online Calculator
pDRAM_SIZE = 8 (x8), burst length = 16 (BL16)

• The input is: 128’b 1010_1011_1001_1000_1100_1101_0111_0110_1110_1111_0101_0100_1010_1011_

0011_0010_1100_1101_ 0001_0000_1110_1111_1001_1000_0111_0110_0101_ 0100_0011_0010_0001_0000
• We divided the CRC 16 bits generation into two 8 bits generation

Jul 18, 2022 46

 Simulation result
pDRAM_SIZE = 8 (x8), burst length = 16 (BL16)

Jul 18, 2022 47

 Optimization

The block is synthesized on Design Compiler (DC) using 130 nm technology.

First approach Second approach

Number of cells 1724 1394
Combinational area(um)2 22539.68 19474.38
Total cell area(um)2 31612.04 21061.75
Total area(um)2 556474.56 454643.93
Cell Internal Power(uW) 3.9411 1.8187
Total Dynamic Power(mW) 5.6164 4.9514
data required time 2.63 2.56
slack -0.26 0.00

Jul 18, 2022 48

 DDR5 PHY
OUTLINE
1. Introduction to Memories.
2. Standard Specifications.
3. DDR5 PHY Blocks.
4. System Integration.
1. Timing Diagram.
2. Parameters value.
3. Simulation Result.
5. FPGA flow.

Jul 18, 2022 49

 Timing Diagram

• Timing diagram of two back to back write operation with frequency ratio of 1:2 and burst
length 16 (BL16) with CRC generated from PHY.

Jul 18, 2022 50

 Timing parameters

Timing parameter Value (clk) Min/Max (clk) Controlled by Description

tctrl_delay 2 0/- a Frequency ratio Each block
block and command registering the
address block outputs.
tphy_wrlat 0 0/- a Command address The block doesn’t
block need this delay to
handle the
command
tphy_wrdata 6 0/- a Write data block We need this delay
to calculate the
inter-amble
correctly

a. The minimum supportable value is 0; the DFI does not specify a maximum value. The range of values
supported is implementation-specific.

Jul 18, 2022 51

 Simulation Result

• Frequency ration 1:2 ,Burst length = 8 ,phy CRC support, with preamble: 3 CLK : “000010” ,
and post-amble : “0000” inter-amble : “10”

Jul 18, 2022 52

 DDR5 PHY
OUTLINE
1. Introduction to Memories.
2. Standard Specifications.
3. DDR5 PHY Blocks.
4. System Integration.
5. FPGA flow.

Jul 18, 2022 53

 FPGA design flow

Design and RTL Simulation synthesis PnR

Post
Testing Programming Timing analysis implementation
simulation

Jul 18, 2022 54

 Post implementation simulation (zoomed)

• The output changes after rising edge by 10 ps.

Jul 18, 2022 55

 Conclusion

• We have studied different versions of DDR and we started reading the standards (DFI and
JEDEC).
• We extracted the required specification to implement the write operation and CRC operation
and proposed a design for the PHY system.
• The RTL of each block was implemented using System Verilog (SV) and each block was tested
using ModelSim and VCS.
• The system was synthesized on DC compiler and the area, power and maximum timing were
reported.
• We have gone through FPGA design flow.

Jul 18, 2022 56

 Future work

• generating verification environment.

• performing design for testability (DFT) for our system.
• going through PnR flow till generating GDSII files.

Jul 18, 2022 57

 References

1. DDR PHY Interface DFI 5.0 Specification.

2. JEDEC STANDARD JESD79-5A.
3. Random Access Memory. Youtube channel “Computer science”. Last accessed 27th June
2022: https://www.youtube.com/playlist?list=PLTd6ceoshpreE_xQfQ-akUMU1sEtthFdB
4. DDR-PHY Interoperability Using DFI. Synopsys. Last accessed 27th June 2022:
https://blogs.synopsys.com/vip-central/2016/09/06/ddr-phy-interoperability-using-dfi/
5. Classification of Memory. JavaTpoint. Last accessed 23th Nov 2021:
https://www.javatpoint.com/classification-of-memory
6. DRAM Operation: how does dynamic RAM work. Electronics notes. Last accessed 11th Nov
2021: https://www.electronics-notes.com/articles/electronic_components/semiconductor-
ic-memory/dynamic-ram-how-does-dram-work-operation.php
7. Linda Rosencrance. DIMM (dual in-line memory module). TechTarget. Last accessed 18th
Nov 2021:https://www.techtarget.com/searchstorage/definition/DIMM

Jul 18, 2022 58

THANK YOU…