LNK33x2-7D

LinkSwitch-TNZ Family
Energy Efficient Off-line Switcher IC with Best-in-Class
Light Load Efficiency and Lossless AC Zero-Cross Detection

Product Highlights
Highest Performance and Design Flexibility
• Lossless zero cross signal generation LinkSwitch-TNZ
• Supports buck, buck-boost and flyback topologies FB BP/M
• Enables ±3% regulation across line and load
D S +
• Selectable device current limit
Z1 Z2
• 66 kHz operation with accurate current limit Zero
• Allows the use of low-cost off-the-shelf inductors Cross DC
Signal Output
• Reduces size and cost of magnetics and output capacitor
• Frequency jittering reduces EMI filter complexity
• X capacitor discharge function (LNK331x only)
Enhanced Safety and Reliability Features Figure 1. Typical Buck Converter Application (See Application Examples
PI-9175-060820
• Soft-start limits system component stress at start-up Section for Flyback and other Circuit Configurations).
• Auto-restart for short-circuit and open loop faults
• Output overvoltage protection (OVP)
• Line input overvoltage protection (OVL)
• Hysteretic over-temperature protection (OTP)
• Extended creepage between DRAIN pin and all other pins improves
field reliability
Figure 2. Package D: SO-8C.
• 725 V MOSFET rating for excellent surge withstand
• Nemko (EN62368-1) and CB (IEC62368-1) certifications
EcoSmart™– Extremely Energy Efficient Output Current in Buck Table1
• IC standby supply current <100 mA
230 VAC ± 15% 85-265 VAC
• On/Off control provides constant efficiency over a wide load range
Product
• Easily meets all global energy efficiency regulations MDCM2 CCM3 MDCM2 CCM3
• No-load consumption <30 mW with external bias
LNK33x2D 63 mA 80 mA 63 mA 80 mA
Applications
• Home and building automation LNK33x4D 120 mA 170 mA 120 mA 170 mA
• Dimmers, switches and sensors with and w/o Neutral wire LNK33x6D 225 mA 360 mA 225 mA 360 mA
• Appliances
• IoT and industrial controls LNK33x7D 360 mA 575 mA 360 mA 575 mA

Description Table 1. Output Power Table.

Notes:
The LinkSwitch™-TNZ family of ICs combine power conversion with 1. Typical output current in a non-isolated buck converter with devices operating
lossless generation of AC zero crossing signal used typically for system at default current limit and adequate heat sinking. Output power capability
depends on respective output voltage and thermal requirements. See Key
clock and timing functions. Designs using the highly integrated Applications Considerations section for complete description of assumptions,
LinkSwitch-TNZ ICs are more flexible than discrete implementations including fully discontinuous conduction mode (DCM) operation.
reducing component count by 40% or higher. Besides enabling 80+ 2. Mostly discontinuous conduction mode.
efficiencies in low power flyback designs, very low consumption at light 3. Continuous conduction mode.
loads enabled by On/Off control allow for more functions (display, wireless
connectivity, sensors etc.) to be active during system standby. The Output Power in Flyback Table6
device family supports buck, buck-boost and flyback converter topologies.
Open Frame4
Each device incorporates a 725 V power MOSFET, oscillator, a Product
high-voltage switched current source for self-biasing, frequency jittering, 230 VAC ± 15% 85-265 VAC
fast (cycle-by-cycle) current limit, hysteretic thermal shutdown, and
output and input overvoltage protection circuitry onto a monolithic IC. LNK33x2D 5W 3W
LinkSwitch-TNZ ICs consume <100 mA current in standby resulting in LNK33x4D 10 W 6W
power supply designs that can meet no-load and standby regulations LNK33x6/7D5 18 W 12 W
worldwide. MOSFET current limit modes can be selected through the
BYPASS pin capacitor value. The high current limit level provides Table 2. Output Power Table.
maximum continuous output current while the low level permits using Notes:
very low-cost and small surface mount inductors. A full suite of 4. Maximum practical continuous power in an open frame design with adequate
heat sinking, measured at 25 °C ambient.
protection features enables safe and reliable power supplies protecting
5. LNK33x6 is recommended in Flyback for highest efficiency.
the device and the system against input and output overvoltage faults, 6. See Key Application Considerations section for complete description of
device over-temperature faults, lost regulation, and power supply assumptions.
output overload or short-circuit faults.
www.power.com June 2021
This Product is Covered by Patents and/or Pending Patent Applications.
 LinkSwitch-TNZ

BYPASS DRAIN
(BP/M) (D)
REGULATOR
5.0 V

IFBSD IFB FAULT

PRESENT BYPASS PIN
ZERO-DETECT 1
(Z1) 5.2 V CAPACITOR
DETECT
AUTO-RESTART BYPASS PIN
ISUPPLY COUNTER UNDERVOLTAGE
OVL + CURRENT LIMIT
CLOCK
5.0 V -
COMPARATOR
RESET 4.5 V
+
Z1, Z2
Control -
& VI
LIMIT
Timer

JITTER
CLOCK THERMAL
SHUTDOWN
ISUPPLY DCMAX

ZERO-DETECT 2 OSCILLATOR
(Z2)
S Q
FEEDBACK
(FB) R Q

2.0 V -VT
LEADING
EDGE
BLANKING
OVP
DETECT

SOURCE
(S)

PI-9174-060820

Figure 3. Functional Block Diagram.

Pin Functional Description FEEDBACK (FB) Pin

During normal operation, switching of the power MOSFET is con-
Z1 and Z2 Pins trolled by the FEEDBACK pin. MOSFET switching is terminated when
• Z1 and Z2 are used in combination for zero cross detect (ZCD) a current greater than IFB (49 mA) is delivered into this pin. Line
signal generation, X capacitor discharge or both. overvoltage protection is detected when a current greater than IFBSD
• For zero crossing, Z1 is connected to one of the input AC lines (670 mA) is delivered into this pin for 2 consecutive switching cycles.
through an external resistor while Z2 forms the ZCD signal output.
• For X capacitor discharge (LNK331x only), Z1 is connected to one SOURCE (S) Pin
AC line input through an external resistor and Z2 is connected to This pin is the power MOSFET source connection. It is also the
the other AC input line input through a separate external resistor. ground reference for the BYPASS and FEEDBACK pins.
• Z1 and Z2 can also be used to combine X capacitor discharge and
ZCD signal generation functions (LNK331x only) – see Application
Section for details.
• Z1 and Z2 can be connected to SOURCE (S) pins if not used.
• Z1 and Z2 are interchangeable.
DRAIN (D) Pin D Package (SO-8C)
Power MOSFET drain connection. Provides internal operating current
for both start-up and steady-state operation.
BYPASS (BP/M) Pin 1 8
Z1 FB
This pin has multiple functions: 2 7
• It is the connection point for an external bypass capacitor for the Z2 BP/M
internally generated 5.0 V supply. 6
S
• It is a mode selector for the current limit value, depending on the
4 5
value of the capacitance added. Use of a 0.1 mF capacitor results D S
in the standard current limit value. Use of a 1 mF capacitor results
in the current limit being reduced, allowing design with lowest cost
surface mount buck chokes.
• It provides a shutdown function. When the current into the
BYPASS pin exceeds IBPSD for a time equal to 2 to 3 cycles of the PI-7842b-060820
internal oscillator (fOSC), the device enters auto-restart. This can be
used to provide an output overvoltage protection function with Figure 4. Pin Configuration.
external circuitry.

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 LinkSwitch-TNZ

LinkSwitch-TNZ Functional Description 600

PI-3660-091018
LinkSwitch-TNZ combines a high-voltage power MOSFET switch with
500 V
a power supply controller in one device. Unlike conventional PWM
DRAIN
(pulse width modulator) controllers, LinkSwitch-TNZ uses a simple
ON/OFF control to regulate the output voltage. The LinkSwitch-TNZ 400
controller consists of an oscillator, feedback (sense and logic) circuit,

Voltage (V)
5.0 V regulator, BYPASS pin undervoltage circuit, over-temperature 300
protection, line and output overvoltage protection, frequency
jittering, current limit circuit, leading edge blanking and a 725 V 200
power MOSFET. The LinkSwitch-TNZ incorporates additional circuitry
for auto-restart. 100
Oscillator
0
The typical oscillator frequency is internally set to an average of fOSC 68 kHz
(66 kHz). Two signals are generated from the oscillator: the
64 kHz
maximum duty cycle signal (DC(MAX)) and the clock signal that
indicates the beginning of each cycle.

The LinkSwitch-TNZ oscillator incorporates circuitry that introduces a 0 10 20

small amount of frequency jitter, typically 4 kHz peak-to-peak, to Time (µs)
minimize EMI emission. The modulation rate of the frequency jitter is
set to 1 kHz to optimize EMI reduction for both average and quasi- Figure 5. Frequency Jitter.
peak emissions. The frequency jitter should be measured with the
oscilloscope triggered at the falling edge of the DRAIN waveform. BYPASS pin. Adding an external Zener diode from the output voltage
The waveform in Figure 5 illustrates the frequency jitter of the to the BYPASS pin allows implementing an hysteretic OVP function in
LinkSwitch-TNZ. a flyback converter (see Figure 6). The current into the BYPASS pin
Soft-Start should be limited to less than 16 mA.
At power-up or during a restart attempt in auto-restart, the device BYPASS Pin Undervoltage
applies a soft-start by temporarily reducing the oscillator frequency to The BYPASS pin undervoltage circuitry disables the power MOSFET
fOSC(SS) (typically 33 kHz). Soft-start terminates either after 256 when the BYPASS pin voltage drops below VBP–VBPH (approximately
switching cycles or if the output voltage reaches regulation. 4.5 V). Once the BYPASS pin voltage drops below this threshold, it
Feedback Input Circuit must rise back to VBP to enable (turn-on) the power MOSFET.
The feedback input circuit at the FEEDBACK pin consists of a low Over-Temperature Protection
impedance source follower output set at VFB (2.0 V). When the The thermal shutdown circuitry senses the die temperature. The
current delivered into this pin exceeds IFB (49 mA), a low logic level threshold is set at TSD (142 °C typical) with a 75 °C (TSDH) hysteresis.
(disable) is generated at the output of the feedback circuit. This When the die temperature rises above TSD the power MOSFET is
output is sampled at the beginning of each cycle on the rising edge disabled and remains disabled until the die temperature falls to
of the clock signal. If high, the power MOSFET is turned on for that TSD –TSDH, at which point it is re-enabled.
cycle (enabled), otherwise the power MOSFET remains off (disabled).
Current Limit
The sampling is done only at the beginning of each cycle. Subse-
The current limit circuit senses the current in the power MOSFET.
quent changes in the FEEDBACK pin voltage or current during the
When this current exceeds the internal threshold (ILIMIT), the power
remainder of the cycle do not impact the MOSFET enable/disable
MOSFET is turned off for the remainder of that cycle. The leading
status. If a current greater than IFBSD is injected into the FEEDBACK
edge blanking circuit inhibits the current limit comparator for a short
pin while the MOSFET is enabled for at least two consecutive cycles
time (tLEB) after the power MOSFET is turned on. This leading edge
the part will stop switching and enter auto-restart off-time. Normal
blanking time has been set so that current spikes caused by capaci-
switching resumes after the auto-restart off-time expires. This
tance and rectifier reverse recovery time will not cause premature
shutdown function allows implementing line overvoltage protection in
termination of the switching pulse. Current limit can be selected
flyback converters (see Figure 6). The current into the FEEDBACK pin
using the BYPASS pin capacitor (0.1 mF for normal current limit / 1 mF
should be limited to less than 1.2 mA.
for reduced current limit). LinkSwitch-TNZ selects between normal
5.0 V Regulator and 5.2 V Shunt Voltage Clamp and reduced current limit at power-up prior to switching.
The 5.0 V regulator charges the bypass capacitor connected to the
Auto-Restart
BYPASS pin to VBP by drawing a current from the voltage on the
In the event of a fault condition such as output overload, output
DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal
short, or an open-loop condition, LinkSwitch-TNZ enters into
supply voltage node for the LinkSwitch-TNZ. When the MOSFET is
auto-restart operation. An internal counter clocked by the oscillator
on, the LinkSwitch-TNZ runs off of the energy stored in the bypass
gets reset every time the FEEDBACK pin is pulled high. If the
capacitor. Extremely low power consumption of the internal circuitry
FEEDBACK pin is not pulled high for t AR(ON) (50 ms), the power
allows the LinkSwitch-TNZ to operate continuously from the current
MOSFET switching is disabled for a time equal to the auto-restart
drawn from the DRAIN pin. A bypass capacitor value of 0.1 mF is
off-time. The first time a fault is asserted the off-time is 150 ms
sufficient for both high frequency decoupling and energy storage.
(t AR(OFF) First Off Period). If the fault condition persists, subsequent
In addition, there is a shunt regulator clamping the BYPASS pin at
off-times are 1500 ms long (t AR(OFF) Subsequent Periods). The
VBP(SHUNT) (5.2 V) when current is provided to the BYPASS pin through
auto-restart alternately enables and disables the switching of the
an external resistor. This facilitates powering of LinkSwitch-TNZ
power MOSFET until the fault condition is removed. The auto-restart
externally through a bias winding to decrease the no-load consump-
counter is gated by the switch oscillator.
tion to about 10 mW (flyback). The device stops switching instantly
and enters auto-restart when a current ≥IBPSD is delivered into the

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 LinkSwitch-TNZ

Hysteretic Output Overvoltage Protection Line Overvoltage Protection

The output overvoltage protection provided by the LinkSwitch-TNZ IC In a flyback converter LinkSwitch-TNZ can sense indirectly the DC bus
uses auto-restart that is triggered by a current >IBPSD into the BYPASS overvoltage condition during the power MOSFET on-time by monitor-
pin. In addition to an internal filter, the BYPASS pin capacitor forms ing the current flowing into the FEEDBACK pin depending on circuit
an external filter providing noise immunity from inadvertent configuration. Figure 7 shows one possible circuit implementation.
triggering. For the bypass capacitor to be effective as a high During the MOSFET on-time, the voltage across the secondary
frequency filter, the capacitor should be located as close as possible winding is proportional to the voltage across the primary winding.
to the SOURCE and BYPASS pins of the device. The current flowing through emitter and base of transistor Q3 is
therefore representing VBUS. Indirect line sensing minimizes power
The OVP function can be realized in a flyback converter by connect- dissipation and is used for line OV protection. The LinkSwitch-TNZ
ing a Zener diode from the output supply to the BYPASS pin. The will go into auto- auto-restart mode if the FEEDBACK pin current
circuit example shown in Figure 6 describes a simple method for exceeds the line overvoltage threshold current IFBSD for at least 2
implementing the output overvoltage protection. Adding additional consecutive switching cycles.
filtering can be achieved by inserting a low value (10 W to 47 W)
resistor in series with the OVP Zener diode. The resistor in series In order to have accurate line OV threshold voltage and also for good
with the OVP Zener diode also limits the maximum current into the efficiency, regulation performance and stability, the transformer
BYPASS pin. The current should be limited to less than 16 mA. leakage inductance should be minimized. Low leakage will minimize
ringing on the secondary winding and provide accurate line OVP
During a fault condition resulting from loss of feedback, the output sampling. In some designs, a RC snubber across the rectifier diode
voltage will rapidly rise above the nominal voltage. A voltage at the may be needed to damp the ringing at the secondary winding when
output that exceeds the sum of the voltage rating of the Zener diode line voltage is sampled.
connected from the output to the BYPASS pin and bypass voltage, will
cause a current in excess of IBPSD injected into the BYPASS pin, which
will trigger the auto-restart and protect the power supply from
overvoltage.

T1
+
VO

+
VBUS
D VOV = VBP + VDOVP
FB
LinkSwitch-TNZ BP
RBP

S CBP
DOVP

PI-8024a-060120

Figure 6. Non-Isolated Flyback Converter with Output Overvoltage Protection (Z1/Z2 Circuitry Not Shown for Clarity).

T1
n:1
+
R3* VO

VR3

+ D3 VOV = (VVR3 + VD3 + VBE(Q3) – VBP + VR3) × n + VDS(ON)

VBUS
*R3 limits the current into the FEEDBACK pin.
R4** A maximum current of 120% of IFBSD is
Q3
D recommended.
FB
LinkSwitch-TNZ **R4 is a pull-up resistor for Q3 to avoid
BP inadvertant triggering. 2 kΩ is a typical starting point
S cBP

PI-8025a-061620

Figure 7. Line-Sensing for Overvoltage Protection by Using FEEDBACK Pin (Z1/Z2 Circuitry Not Shown for Clarity).

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 LinkSwitch-TNZ

ON/OFF Operation with Current Limit State Machine supply output (Figure 9). At medium loads, cycles will be skipped and
the current limit will be reduced (Figure 10). At very light loads, the
The internal clock of the LNK33x7 runs all the time. At the
current limit will be reduced even further (Figure 11). Only a small
beginning of each clock cycle, it samples the FEEDBACK pin to
percentage of cycles will occur to satisfy the power consumption of
decide whether or not to implement a switch cycle, and based on
the power supply.
the sequence of samples over multiple cycles, it determines the
appropriate current limit. At high loads, the state machine sets the The response time of the ON/OFF control scheme is very fast
current limit to its highest value. At lighter loads, the state machine compared to PWM control. This provides tight regulation and
sets the current limit to reduced values. excellent transient response.
At near maximum load, LNK33x7 will conduct during nearly all of
its clock cycles (Figure 8). At slightly lower load, it will “skip”
additional cycles in order to maintain voltage regulation at the power

VFB VFB

CLOCK CLOCK

DCMAX DCMAX

IDRAIN IDRAIN

VDRAIN VDRAIN

PI-2749a-022520 PI-2667a-022520

Figure 8. Operation at Near Maximum Loading (Flyback). Figure 9. Operation at Moderately Heavy Loading (Flyback).

VFB VFB

CLOCK CLOCK

DCMAX DCMAX

IDRAIN IDRAIN

VDRAIN VDRAIN

PI-2377a-022520 PI-2661a-022520

Figure 10. Operation at Medium Loading (Flyback). Figure 11. Operation at Very Light Load (Flyback).

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 LinkSwitch-TNZ

Applications Example

D3
R5 DFLR1600-7
44.2 kΩ 600 V

R3
20.0 kΩ
C3
10 µF
R1 R8 C2 R4 16 V
RF1 18 kΩ 4.7 kΩ 100 nF
8.2 Ω D6 40.2 kΩ
25 V
L 1W SM4007PL-TP FB BP/M 6 V, 80 mA
L2 D S L1
D1 VR1 VOUT
2.2 mH Z1 Z2 2.7 mH
SM4007PL-TP SMAZ10-13-F D4
10 V LinkSwitch-TNZ D2 SM4001PL-TP
R2 U1
1 MΩ SFM18PL-TP
LNK3302 ZCD TP4
R6
100 kΩ C4
90 - 300 RV1 100 µF R7
VAC 300 VAC 16 V 20 kΩ
C6 C1
1.0 µF 1.0 µF C5 D5
450 V 450 V 100 pF C7* SM4001PL-TP
100 V RTN TP6
N RTN

*Optional components PI-9249-122120

Figure 12. Universal Input, 6 V, 80 mA Constant Voltage Power Supply with Zero-Crossing Detector using LinkSwitch-TNZ.

A 0.48 W Universal Input Buck Converter Capacitor C2 with a value of 100 nF sets the current limit to Standard
mode. Resistor R3 provides an external current supply to the BYPASS
The circuit shown in Figure 12 is a typical implementation of a 6 V,
(BP) pin to lower the no-load input power.
80 mA non-isolated power supply used in 2-wire smart switch
applications. To a first order, the forward voltage drops of D2 and D3 are identical.
Therefore, the voltage across C3 tracks the output voltage. The
The input stage comprises of fusible resistor RF1, varistor RV1, diodes
voltage developed across C3 is sensed and regulated via the resistor
D1 and D6, capacitors C1 and C6, inductor L2 with resistor R8, and
divider R4 and R5 connected to U1’s FEEDBACK pin. The values of R4
the R-Z circuit R1 and VR1. Resistor RF1 is a flame-proof, fusible,
and R5 are selected such that, at the desired output voltage, the
wire-wound resistor. It accomplishes several functions:
voltage at the FEEDBACK pin is 2 V.
A. Inrush current limitation to safe levels for rectifiers D1 and D6;
Regulation is maintained by skipping switching cycles. As the output
B. Differential mode noise attenuation;
voltage rises, the current into the FEEDBACK pin will rise. If this
C. Acts as an input fuse in the event any other component fails
exceeds IFB then subsequent cycles will be skipped until the current
short-circuit (component fails safely open-circuit without emitting
reduces below IFB. Thus, as the output load is reduced, more cycles
smoke, fire or incandescent material).
will be skipped and if the load increases, fewer cycles are skipped.
RV1 is added for surge protection. The R-Z circuit minimizes the To provide overload protection if no cycles are skipped during a
no-load input current by putting a large series resistance R1 which 50 ms period, LinkSwitch-TNZ will enter auto-restart, limiting the average
increases the system power factor. The Zener diode clamps the output power to approximately 3% of the maximum overload power.
voltage across R1 during startup and at higher output load.
Z1 and Z2 pins are configured to provide a lossless (<5 mW) zero
D1 and D6 provide rectification as well as protection during ring-wave crossing detection (ZCD) circuit. Z2 is connected to one of the input
surge which is typically tested above 2 kV. In order to avoid a phase AC lines through resistor R2 while Z1 forms the ZCD signal output.
shift during ZCD measurement, it is not recommended to place one of
When the AC voltage is more positive with respect to Neutral, D4 is
the diodes on the Neutral side.
forward-biased and clamps ZCD output to VOUT + 0.7 V. At the
The power processing stage is formed by LinkSwitch-TNZ U1, negative-going phase of the AC input, D5 is forward-biased and
freewheeling diode D2, output choke L1, and output capacitor C4. clamps ZCD output to -0.7 V.
LNK3302 was selected such that the power supply operates in mostly
The passive components comprised of R2, C5, R6, and optional C7
continuous conduction mode (CCM). Diode D2 is an ultrafast diode
provide noise filtering to ensure clean ZCD signal. The values are
with a reverse recovery time (tRR) of 35 ns recommended for CCM
chosen such that the overall ZCD delay is kept below 200 µs. C7 is a
operation. For mostly discontinuous conduction mode (MDCM)
placeholder for the additional filter if needed. D5 has capacitance
designs, a diode with a tRR of 75 ns is acceptable. Inductor L1 is a
that helps avoid adding the extra capacitor. However, care must be
standard off-the-shelf inductor with appropriate RMS current rating.
taken when selecting the diode since too much capacitance will cause
Capacitor C4 is a low-ESR electrolytic capacitor to minimize the
more delay.
output voltage ripple. A small pre-load R7 is required to limit the
output voltage to about 110% of the rated voltage during light load or
no-load condition.

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 LinkSwitch-TNZ

Key Application Considerations Freewheeling Diode D2

Diode D2 should be an ultrafast type. For MDCM, reverse recovery
LinkSwitch-TNZ Design Considerations time tRR ≤75 ns should be used at a temperature of 70 °C or below.
Slower diodes are not acceptable, as continuous mode operation will
Output Current Table (Buck Topology) always occur during startup, causing high leading edge current
Table 1 represents the typical practical continuous output current that spikes, terminating the switching cycle prematurely, and preventing
LinkSwitch-TNZ can deliver under the following assumptions: the output from reaching regulation. If the ambient temperature is
above 70 °C then a diode with tRR ≤35 ns should be used.
1. Buck topology.
2. The minimum DC input voltage is ≥70 V. The value of input For CCM an ultrafast diode with reverse recovery time tRR ≤35 ns
capacitance should be large enough to meet this criterion. should be used. A slower diode may cause excessive leading edge
3. For CCM operation a KRP* of 0.4. current spikes, terminating the switching cycle prematurely and
4. 12 VDC output voltage. preventing full power delivery.
5. 75% efficiency.
6. A catch/freewheeling diode with tRR ≤75 ns is used for MDCM Fast recovery and slow recovery diodes should never be used as the
operation and for CCM operation, a diode with tRR ≤35 ns is used. large reverse recovery currents can cause excessive power dissipation
7. The part is board mounted with SOURCE pins soldered to a in the diode and/or exceed the maximum drain current specification
sufficient area of copper to keep the SOURCE pin temperature at of LinkSwitch-TNZ.
or below 110 °C. Feedback Diode D3
*KRP is the ratio of ripple to peak inductor current. Diode D3 can be a low-cost slow diode such as the 1N400X series,
however it should be specified as a glass passivated type to
Output Power Table (Flyback Topology) guarantee a specified reverse recovery time. To a first order, the
Table 2 represents the maximum practical continuous power that forward drops of D2 and D3 should match.
LinkSwitch-TNZ can deliver under the following assumptions:
Inductor L1
1. Flyback topology. Choose any standard off-the-shelf inductor that meets the design
2. 12 VDC output voltage. requirements. A “drum” or “dog bone” “I” core inductor is
3. 75% efficiency. recommended with a single ferrite element due to its low-cost.
4. CCM operation with KRP of 0.6. Minimize audible noise by varnishing the inductor. The typical
5. Open frame, 25 °C ambient. inductance value and RMS current rating can be obtained from the
6. The part is board-mounted with SOURCE pins soldered to a LinkSwitch-TNZ design spreadsheet available within the PI Expert
sufficient area of copper to keep the SOURCE pin temperature at design suite from Power Integrations. Choose L1 greater than or
or below 110 °C. equal to the typical calculated inductance with RMS current rating
greater than or equal to calculated RMS inductor current.
LinkSwitch-TNZ Selection and Selection Between
MDCM and CCM Operation Output Capacitor C4
The primary function of capacitor C4 is to smooth the inductor
Select the LinkSwitch-TNZ device, freewheeling diode and output
current. The actual output ripple voltage is a function of this
inductor that gives the lowest overall cost. In general, MDCM
capacitor’s ESR. To a first order, the ESR of this capacitor should not
provides the lowest cost and highest efficiency converter. CCM
exceed the rated ripple voltage divided by the typical current limit of
designs require a larger inductor and ultrafast (tRR ≤35 ns) freewheel-
the chosen LinkSwitch-TNZ.
ing diode in all cases. It is lower cost to use a larger LinkSwitch-TNZ
in MDCM than a smaller LinkSwitch-TNZ in CCM because of the Feedback Resistors R4 and R5
additional external component costs of a CCM design. However, if The values of the resistors in the resistor divider formed by R4 and
the highest output current is required, CCM should be employed R5 are selected to maintain 2 V at the FEEDBACK pin.
following the guidelines below. External Bias Resistor R3
Topology Options To reduce the no-load input power of the power supply, resistor R3,
LinkSwitch-TNZ can be used in all common topologies, with or connected from the feedback capacitor C3 to the BYPASS pin, is
without an optocoupler and reference to improve output voltage recommended. This is applicable to the power supply whose output
tolerance and regulation. Table 2 provides a summary of these voltage is higher than VBP(SHUNT). To achieve lowest no-load power
configurations. For more information see the Application Note – consumption, the current fed into the BYPASS pin should be slightly
LinkSwitch-TNZ Design Guide. higher than IS1. For the best full-load efficiency and thermal
performance, the current fed into the BYPASS pin should be slightly
Component Selection higher than the IS2 Max value.
Referring to Figure 12, the following considerations may be helpful in Feedback Capacitor C3
selecting components for a LinkSwitch-TNZ design. Capacitor C3 can be a low-cost general purpose capacitor. It
BYPASS Pin Capacitor C2 provides a “sample and hold” function, charging to the output voltage
Capacitor connected from the BYAPSS pin provides decoupling for the during the off time of LinkSwitch-TNZ. Its typical value is 10 µF.
controller and also selects current limit. A 0.1 mF or 1 mF capacitor Pre-Load Resistor R7
may be used as indicated in the data sheet. Though electrolytic In high-side, direct-feedback, a pre-load resistor is required to
capacitors may be used, surface mount multi-layer ceramic capacitors maintain output regulation at light or no-load. The value of R7 should
are preferred for use as they enable placement of capacitors close to be selected to provide a balance between power loss and output
the IC and design of compact switching power supplies. 16 V, 25 V or regulation.
higher X7R dielectric capacitors are recommended to ensure
minimum capacitance change under DC bias and temperature.

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 LinkSwitch-TNZ

ZCD Circuit X Capacitor Discharge (LNK331x Only)

The ZCD configuration shown in Figure 12 is just one of the various X capacitor discharge function can be implemented by connecting Z1
options that the user can choose based on topology selection. In to one AC line input through an external series resistor and Z2 to the
high-side buck configuration, Z1/Z2 pins are more prone to switching- other AC input line input through a separate external resistor. Nominal
noise coupling especially at high-line, full-load due to floating values of total X capacitance and series resistor range (RC time
SOURCE pin. Unmitigated noise may affect not only the ZCD signal constant is <1 second) is shown in the table below.
but also cause higher conducted emission. Resistor R2 should be
large enough to minimize the impact on EMI while keeping the ZCD
delay to an acceptable level. A network of filters composed of C5, R6 Total X Capacitance Total Series Resistance
and an optional C7 (<100 pF) are needed to ensure clean ZCD signal. 100 nF to 6 mF 7.5 MW to 142 kW
For D5, choose a diode with junction capacitance of <100 pF.

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 LinkSwitch-TNZ

Non-Isolated Configurations

• Output referenced to Neutral

• Positive output voltage relative to Neutral
• Step down – VO < VIN
• Low-cost direct feedback (±5% typ.)
• Requires an output load to maintain
regulation
• ZCD signal toggles every half-line AC cycle
• ZCD logic follows the AC line
• Lowest ZCD component count
LinkSwitch-TNZ • Higher Zener diode capacitance may affect
L FB BP/M VO ZCD delay
D S • ZCD low signal is -0.7 V with respect to
Z1 Z2
system GND
System • X capacitor discharge capable
uC
VIN

VZC

N RTN VIN
PI-9250a-020321

VZC

Figure 13. High-Side Buck, Half-Wave Rectification ZCD with Zener Diode.

• Output referenced to Neutral

• Positive output voltage relative to Neutral
• Step down – VO < VIN
• Low-cost direct feedback (±5% typ.)
• Requires an output load to maintain
regulation
• ZCD signal toggles every half-line AC cycle
• ZCD logic follows the AC line
LinkSwitch-TNZ
FB BP/M VO
• Typically has faster ZCD slew rate due to
L
D S
lower capacitance than Zener
Z1 Z2 • ZCD low signal is -0.7 V with respect to
System
system GND
VIN
uC • Not configured for X capacitor discharge

VZC

N RTN
VIN
PI-9251a-020321

VZC

Figure 14. High-Side Buck, Half-Wave Rectification ZCD with 2 Diodes.

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 LinkSwitch-TNZ

• Output referenced to Neutral

• Positive output voltage relative to Neutral
• Step down – VO < VIN
• Low-cost direct feedback (±5% typ.)
• Requires an output load to maintain
regulation
• ZCD signal toggles every half-line AC cycle
• Inverted ZCD logic with respect to AC line
LinkSwitch-TNZ
FB BP/M VO
• ZCD logic low signal is the same as system
L
D S
GND
Z1 Z2 • X capacitor discharge capable
System
uC
VIN

VIN
VZC

N RTN

PI-9252a-020321

VZC

Figure 15. High-Side Buck, Half-wave Rectification ZCD with MOSFET.

• Positive output voltage relative to Neutral

• Step down – VO < VIN
• Low-cost direct feedback (±5% typ.)
• Requires an output load to maintain
regulation
• Higher power capability than half-wave
rectifier
LinkSwitch-TNZ • ZCD signal toggles every half-line AC cycle
FB BP/M VO
• Inverted ZCD logic with respect to AC line
D S
Z1 Z2 • ZCD low signal is the same as system GND
• ZCD signal probing requires special setup
System in order to prevent signal disruption
L uC
• Not configured for X capacitor discharge
VIN VZC
N
VIN
RTN

PI-9253a-020421

VZC

Figure 16. High-Side Buck, Bridge Rectifier, ZCD with MOSFET.

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 LinkSwitch-TNZ

• Negative output voltage relative to Neutral

• Step up/down – VO > VIN or VO < VIN
• Low-cost direct feedback (±5 % typ.)
• Fail-safe – output is not subjected to input
voltage if the internal power MOSFET fails
• Requires an output load to maintain
regulation
LinkSwitch-TNZ
L FB BP/M RTN
• ZCD signal toggles every half-line AC cycle
D S
• Inverted ZCD logic with respect to AC line
Z1 Z2 • X capacitor discharge capable
VZC

VIN System
uC VIN

N -VO

PI-9254a-020421

VZC

Figure 17. High-Side Buck-Boost with Direct Feedback.

• Step up/down – VO > VIN or VO < VIN

• Opto-coupler feedback
VO • Does not require a pre-load
• ZCD signal toggles every half-line AC cycle
• Inverted ZCD logic with respect to AC line
• ZCD signal referenced to Secondary
• Not configured for X capacitor discharge
L

U1A
VIN System
uC
N LinkSwitch-TNZ
Z2
D
FB VIN
BP/M VZC
Z1
S U1B

RTN

PI-9255a-020321

VZC

Figure 18. Isolated Flyback with AUX Winding for IC Bias.

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 LinkSwitch-TNZ

• Step up/down – VO > VIN or VO < VIN

• Opto-coupler feedback
• Does not require a pre-load
VO • ZCD signal toggles every half-line AC cycle
• Inverted ZCD logic with respect to AC line
U1A
• ZCD signal referenced to Secondary
• Requires additional bias winding referenced
to Neutral
L
• X capacitor discharge capable

VIN System
uC
N LinkSwitch-TNZ
D
Z2 FB
BP/M VZC
VIN
Z1
S U1B

RTN

PI-9258a-020321

VZC

Figure 19. Isolated Flyback with Dedicated Winding for ZCD Optocoupler Bias.

• Step up/down – VO > VIN or VO < VIN

• Opto-coupler feedback
• Does not require a pre-load
VO
• ZCD signal triggers every AC line period
• Inverted ZCD logic with respect to AC line
• ZCD signal referenced to Secondary
L • X capacitor discharge capable
VIN
U1A
N

System
uC VIN
LinkSwitch-TNZ
D
Z2 FB
BP/M VZC
Z1
S U1B

RTN

PI-9259a-020321
VZC

Figure 20. Isolated Flyback with Self-Biased ZCD Optocoupler.

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 LinkSwitch-TNZ

LinkSwitch-TNZ Layout Considerations Figure 21 is printed circuit board layout design examples for the
circuit schematic shown in Figure 12. The loop formed between the
In the buck or buck-boost converter configuration, since the SOURCE LinkSwitch-TNZ U1, freewheeling diode D2, and input capacitor C1
pins in LinkSwitch-TNZ are switching nodes, the copper area should be kept as small as possible. The BYPASS pin capacitor C2
connected to SOURCE should be minimized to minimize EMI within should be located physically close to the SOURCE (S) and BYPASS
the thermal constraints of the design. (BP) pins. To minimize direct coupling from switching nodes, the
In the boost configuration, since the SOURCE pins are tied to DC LinkSwitch-TNZ should be placed away from AC input lines.
return, the copper area connected to SOURCE can be maximized to
improve heat sinking.

Figure 21. Example Printed Circuit Layout for LinkSwitch-TNZ High-Side Buck Configuration.

Safety Considerations For designs operating in continuous conduction mode (CCM) and/
or higher ambients, then a diode with a reverse recovery time of
Based on UL/IEC 60950 safety standard, functional insulation can be 35 ns or better, such as the BYV26C, is recommended.
met by satisfying any of these conditions: 3. Maximum Drain Current – Verify that the peak drain current is
1. Creepage and clearance requirements for functional insulation. below the data sheet peak drain specification under worst-case
2. Withstand electric strength tests for functional insulation. conditions of highest line voltage, maximum overload (just prior
3. Short-circuited and there is no overheating of any material to auto-restart) and highest ambient temperature.
creating a risk of fire, no emission of molten material, no opening 4. Thermal check – At maximum output power, minimum input
of PCB trace, and the temperature is within limits. voltage and maximum ambient temperature, verify that the
LinkSwitch-TN2 SOURCE pin temperature is 100 °C or below. This
Z1 and Z2 pins functional safety compliance falls under condition ensures adequate margin due to variations in RDS(ON) from part to
3 - i.e., even if the pins are shorted, there will be no risk of Safety part. If the device temperature of the IC exceeds 85 °C with
violation as long as the external components (resistors, capacitors) ambient temperature of 25 °C, it is recommended the next bigger
are rated properly. device in the family should be selected for the application. A
Quick Design Checklist battery powered thermocouple meter is recommended to make
measurements when the SOURCE pins are a switching node.
As with any power supply design, all LinkSwitch-TNZ designs should Alternatively, the ambient temperature may be raised to indicate
be verified for proper functionality on the bench. The following margin to thermal shutdown.
minimum tests are recommended:
In a LinkSwitch-TNZ design using a buck or buck-boost converter
1. Adequate DC Rail Voltage – Check that the minimum DC input topology, the SOURCE pin is a switching node. Oscilloscope
voltage does not fall below 70 VDC at maximum load, minimum measurements should therefore be made with probe grounded to a
input voltage. DC voltage, such as primary return or DC input rail, and not to the
2. Correct Diode Selection – UF400x series diodes with reverse SOURCE pins. The power supply input must always be supplied from
recovery time of 75 ns or better are recommended only for an isolated source when doing measurements (e.g. via an isolation
designs that operate in MDCM at an ambient of 70 °C or below. transformer).

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 LinkSwitch-TNZ

Absolute Maximum Ratings1,5

DRAIN Pin Voltage: LNK33xx..................................... -0.3 V to 725 V NOTES:
DRAIN Pin Peak Current: LNK33x2 ......................................600 mA2
1. All voltages referenced to SOURCE, TA = 25 °C.
LNK33x4 .................................... 1230 mA2
2. See Figure 15 and Figure 25 for VDS > 400 V.
LNK33x6/7 ................................. 3750 mA2
3. Normally limited by internal circuitry.
Z1/Z2 Pin Voltage6: LNK33xx ................................................ 1000 V
4. 1/16 in. from case for 5 seconds.
Z1/Z2 Pin Current7: LNK33xx ...................................................5 mA
5. Maximum ratings specified may be applied one at a time without
FEEDBACK Pin Current.......................................................... 100 mA
causing permanent damage to the product. Exposure to Absolute
FEEDBACK Pin Voltage...................................................-0.3 V to 7 V
Maximum Ratings conditions for extended periods of time may
BYPASS Pin Voltage .......................................................-0.3 V to 7 V
affect product reliability.
Storage Temperature....................................................-65 to 150 °C
6. Voltage of Z1 pin relative to Z2 pin in either polarity.
Operating Junction Temperature3 ................................. -40 to 150 °C
7. The peak current is allowed while the Z1/Z2 voltage is
Lead Temperature4................................................................ 260 °C
simultaneously less than 400 V.

Thermal Resistance
Thermal Resistance: Notes:
(qJA)................................... 100 °C/W2, 90 °C/W3 1. Measured on pin 8 (SOURCE) close to plastic interface.
(qJC)1.................................................... 30 °C/W 2. Soldered to 0.36 sq. inch (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad.

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Control Functions
Average 62 66 70
Output Frequency fOSC TJ = 25 °C kHz
Peak-Peak Jitter 4

Maximum Duty Cycle DCMAX TJ = 25 °C 66 69 73 %

FEEDBACK Pin Turnoff VBPP = 5.0 V to 5.5 V

IFB 44 49 54 µA
Threshold Current TJ = 25 °C

FEEDBACK Pin Voltage VBPP = 5.0 V to 5.5 V

VFB 1.97 2.00 2.03 V
at Turnoff Threshold TJ = 25 °C

FEEDBACK Pin Instant

IFB(SD) TJ = 25 °C 520 675 800 µA
Shutdown Current

FEEDBACK Pin Instant Switch

TJ = 25 °C 2
Shutdown Delay Cycles

FEEDBACK Pin Voltage VBPP = 5.0 V to 5.5 V

VFB(SD) 3.0 V
at Shutdown Current TJ = 25 °C

VFB = 2.1 V
IS1 (MOSFET Not Switching) 75 µA
See Note A

DRAIN Pin LNK33x2 98 160

Supply Current FEEDBACK Open
LNK33x4 113 180
(MOSFET
IS2 µA
Switching) LNK33x6 165 250
See Notes A, B
LNK33x7 190 290

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 LinkSwitch-TNZ

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Control Functions (cont.)
VBP = 0 V
ICH1 -11 -7 -3
BYPASS Pin TJ = 25 °C
mA
Charge Current VBP = 4 V
ICH2 -7.5 -5 -2.5
TJ = 25 °C

BYPASS Pin Voltage VBP 4.7 5.0 5.2 V

BYPASS Pin Shutdown

IBP(SD) TJ = 25 °C 6 8 mA
Threshold Current

BYPASS Pin
VBP(SHUNT) IBP = 2 mA 4.9 5.2 5.5 V
Shunt Voltage

BYPASS Pin
VBP(H) 0.37 0.47 0.57 V
Voltage Hysteresis

BYPASS Pin
IBP(SC) See Note C 55 µA
Supply Current
Circuit Protection
di/dt = 55 mA/ms
126 136 146
TJ = 25 °C
LNK33x2
di/dt = 250 mA/ms
149 170 191
TJ = 25 °C

di/dt = 65 mA/ms
240 257 275
TJ = 25 °C
LNK33x4
di/dt = 415 mA/ms
Standard Current Limit 278 317 356
TJ = 25 °C
(CBP) = 0.1 mF ILIMIT mA
See Note D, H di/dt = 95 mA/ms
450 482 515
TJ = 25 °C
LNK33x6
di/dt = 610 mA/ms
510 580 650
TJ = 25 °C

di/dt = 95 mA/ms
725 780 835
TJ = 25 °C
LNK33x7
di/dt = 610 mA/ms
893 1015 1137
TJ = 25 °C

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 LinkSwitch-TNZ

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Circuit Protection
di/dt = 28 mA/ms
70 80 90
TJ = 25 °C
LNK33x2
di/dt = 170 mA/ms
104 119 134
TJ = 25 °C

di/dt = 65 mA/ms
180 205 230
TJ = 25 °C
LNK33x4
di/dt = 415 mA/ms
Reduced Current Limit 227 258 289
TJ = 25 °C
(CBP) = 1 mF ILIMIT(RED) mA
See Note D, H di/dt = 95 mA/ms
325 370 415
TJ = 25 °C
LNK33x6
di/dt = 610 mA/ms
408 464 520
TJ = 25 °C

di/dt = 95 mA/ms
545 620 695
TJ = 25 °C
LNK33x7
di/dt = 610 mA/ms
730 830 930
TJ = 25 °C

LNK33x2
373 534 687
See Note I

LNK33x4
356 475 594
See Note I
Minimum On-Time tON(MIN) ns
LNK33x6
442 591 734
See Note I

LNK33x7
656 875 1094
See Note I

Leading Edge TJ = 25 °C
tLEB 300 450 ns
Blanking Time See Note E

Thermal Shutdown
TSD See Note F 135 142 150 °C
Temperature

Thermal Shutdown
TSDH See Note F 75 °C
Hysteresis

Soft-Start Period, See Note E 256 Cycles

Internal Soft-Start fOSC(CC) LNK33xx
Soft-Start Frequency 33 kHz

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 LinkSwitch-TNZ

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Output
TJ = 25 °C 48 55.2
LNK33x2
ID = 13 mA TJ = 100 °C 76 88.4

TJ = 25 °C 24 27.6
LNK33x4
ID = 25 mA TJ = 100 °C 38 44.2
On-State Resistance RDS(ON) W
TJ = 25 °C 7 8.1
LNK33x6
ID = 45 mA TJ = 100 °C 11 12.9

TJ = 25 °C 7 8.1
LNK33x7
ID = 45 mA TJ = 100 °C 11 12.9

VBP = 5.4 V
VFB ≥2.1 V
IDSS1 200
VDS = 80% BVDSS
Off-State Drain TJ = 125 °C mA
Leakage Current
VBPP = 5.4 V
IDSS2 VDSS = 325 V 15
TJ = 25 °C

VBP = 5.4 V
Breakdown Voltage BVDSS VFB ≥2.1 V LNK33xx 725 V
TJ = 25 °C

DRAIN Pin
TJ = 25 °C 18 V
Supply Voltage

Auto-Restart TJ = 25 °C
t AR(ON) 50 ms
ON-Time See Note G

First Off Periods 150

Auto-Restart TJ = 25 °C
t AR(OFF) ms
OFF-Time See Note G Subsequent Periods 1500

Auto-Restart
DC AR Subsequent Periods 3 %
Duty Cycle

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 LinkSwitch-TNZ

Conditions
SOURCE = 0 V
Parameter Symbol Min Typ Max Units
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Z1/Z2 Function
Supply Current ISUPPLY TJ = 25 °C 22 mA

Saturation Current
IDSAT LNK331x only 2.5 mA
(See Note E, J)

AC Removal Line Cycle Frequency 47-63 Hz

tDET 22 34 ms
Detection Time LNK331x only

NOTES:
A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is = 2.1 V (MOSFET not switching) and the sum of IS2 and
IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).
B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to
measure the BYPASS pin current at 5.1 V.
C. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK pins and not any other
external circuitry.
D. For current limit at other di/dt values, refer to Figures 21 and 22.
E. This parameter is guaranteed by design.
F. This parameter is derived from characterization.
G. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).
H. The BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target
application.
I. Measured using circuit in Figure 12 with 50 W drain pull-up. The width of the drain pulse is measured as the time from VFALL = 42 V to
VRISE = 40 V (VDR = 50 V), for LNK33x6/x5/x4 and as the time from VFALL = 32 V to VRISE = 30 V on rising edge (VDR = 35 V), for LNK33x2.
J. Saturation current specifications ensure a natural RC discharge characteristic at all voltages up to 265 VAC peak with total external series
resistor values 7.5 MW to 142 kW

Tolerance Relative to Minimal

Nominal BP/M Pin Capacitor Value
Capacitor Value
Minimum Maximum

0.1 mF -60% +100%

1 mF -50% +100%

Recommended to use at least 10 V / 0805 / X7R SMD MLCC.

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 LinkSwitch-TNZ

470 kΩ
470 Ω
5W
S2
S1

FB
BP/M
50 V 0.1 µF 50 V

Z2

Z1

S
S
PI-9176-060820

Figure 22. LinkSwitch-TNZ General Test Circuit.

t2
t1
50 Ω FB BP/M
HV 90% 90%
D S
Z1 Z2 0.1 µF
VDR
DRAIN t
D= 1
VOLTAGE t2

10%
0V
PI-9177-060920

PI-2048-050798

Figure 23. LinkSwitch-TNZ Duty Cycle Measurement. Figure 24. LinkSwitch-TNZ Minimum On-Time Test Circuit.

T1 T2

VDR
VFALL VRISE

TON_MIN = T2 - T1

0V

PI-7898-031716

Figure 25. LinkSwitch-TNZ Minimum On-Time Measurement.

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 LinkSwitch-TNZ

SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC

A 4
D
8 5

GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D

1.35 (0.053) 1.25 - 1.65

1.75 (0.069) DETAIL A
(0.049 - 0.065)

0.10 (0.004) 0.10 (0.004) C H

0.25 (0.010) 7X
SEATING PLANE

C 0.17 (0.007)
0.25 (0.010)

Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-012315

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 LinkSwitch-TNZ

SO-8C (D) PACKAGE MARKING

A
1630
LNK3307D C
4D426E D

A. Power Integrations Registered Trademark

B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code

PI-8116c-060220

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 LinkSwitch-TNZ

MSL Table

Part Number MSL Rating

LNK33x2D 3

LNK33x4D 3

LNK33x6D 3

LNK33x7D 3

ESD and Latch-Up Table

Test Conditions Results

Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins
> ±2 kV on all pins, except DRAIN pin for
Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014
LNK33x2 ±1.5 kV
Charge Device Model ESD ANSI/ESDA/JEDEC JS-002-2014 > ±200 V on all pins

Part Ordering Information

• LinkSwitch Product Family
• TNZ Series Number
• Package Identifier
D Plastic SO-8C
• Tape & Reel and Other Options
LNK 33x4 D - TL TL Tape and Reel, 2.5 k pcs for D Package.

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 LinkSwitch-TNZ

Notes

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www.power.com Rev. D 06/21
 Revision Notes Date
B Code A release. 12/20
C Added Family part numbers and size 7 parameter updates. 03/21
C Corrected Diode references in Feedback Diode D3 section on page 7. 05/21
D Added EN/IEC 62368-1 certification bullet point on page 1. 06/21

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

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HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert,
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their respective companies. ©2021, Power Integrations, Inc.

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