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12V
J20
JTAG
J17
Zynq 7000 SoC

Digital System Design Power

SW8

CS 431 UART
J14 Configuration
Mode Pins

MIO[0]
Introduction to Zynq SoC JP6

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System-on-a-Board (PCB) System-on-a-Chip (SoC)

• Higher performance
• Lower power use
• Small form factor
• Reduced cost
• flexibility

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Zynq – All Programmable SoC Simple Anatomy of an Embedded SoC

The hardware system architecture of an embedded SoC (simplified)

A simplified model of the Zynq architecture

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Relationship of the software system, hardware Raising the Abstraction Level

system, and Zynq architecture

Level of abstraction in FPGA design

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Design Reuse Basic Design Flow for Zynq SoC

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Expanded Design Flow for Zynq SoC

The Zynq Device

(“What is it?”)

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How were FPGAs used in the Past? How were FPGAs used in the Past?

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Processing System PS and PL

• PS: Processing system, hard silicon core
– Dual ARM Cortex-A9 processor
– Multiple peripherals
• PL: Programmable logic
– Shares the same 7 series programmable logic as
• Artix-based devices: Z-7010 and Z-7020
• Kintex-based devices: Z-7030 and Z-7045

Locations of hard (ARM Cortex-A9) and soft (MicroBlaze) processors on a Zynq device

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The Zynq Processing System PS Components

• Application processing unit (APU)
• I/O peripherals
– Multiplexed I/O (MIO),
– extended multiplexed I/O (EMIO)
• Memory interfaces
• PS interconnect
• DMA
• Timers
• General interrupt controller (GIC)
• On-chip memory (OCM)
• Debug controller: ARM CoreSight
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Application Processing Unit (APU) Architecture – NEON

Block diagram of the application processing unit (simplified) Single Instruction Multiple Data (SIMD) processing in the NEON MPE
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PS External Interfaces: MIO Peripheral Interfaces

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PS Components Programmable Logic (PL) CLBs and IOBs

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PL: Special Resources PL: Special Resources

Arithmetic capabilities of DSP48E1 Slice

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PS – PL Interface AXI Interface

AMB
A

AMBA 3.0
APB AHB AXI (2003)

Older Performance Newer

AMBA: Advanced Microcontroller Bus Architecture

AXI: Advanced Extensible Interface

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Basic AXI Protocol Full AXI4 Protocol

Sometimes called “Full AXI” or “AXI

1. Read Address Channel Memory Mapped”
AXI4 Read
2. Read Data Channel

Single address multiple data

– Burst up to 256 data beats

3. Write Address Channel

Data Width parameterizable
4. Write Data Channel – 1024 bits AXI4 Write
5. Write Response Channel

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AXI4—Lite Protocol AXI4—Stream Protocol

No burst
No address channel, no read and write,
always just master to slave
Data width 32 or 64 only AXI4-Lite Read AXI4-Stream Transfer
– Effectively an AXI4 “write data” channel
– Xilinx IP only supports 32-bits
Unlimited burst length
– AXI4 max 256
Very small footprint
– AXI4-Lite does not burst
Virtually same signaling as AXI Data
Bridging to AXI4 handled Channels
automatically by AXI4-Lite Write – Protocol allows merging, packing, width
AXI_Interconnect (if needed) conversion
– Supports sparse, continuous, aligned,
unaligned streams

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AXI Interconnects and Interfaces PS – PL Interface

9 AXI interfaces
between PS and
PL.

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Advantages of Zynq Zynq SoC Ecosystem

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Academic Subjects to which Zynq is Relevant

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