UNIT – 4: CENTRAL PROCESSING UNIT

GENERAL REGISTER ORGANIZATION

A set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU. They
include combinational circuits that implement data processing. The information is always defined in a
register before processing. The registers speed up the implementation of programs. Registers
implement two important functions in the CPU operation are as follows −
➢ It can support a temporary storage location for data. This supports the directly implementing
programs to have fast access to the data if required.
➢ It can save the status of the CPU and data about the directly implementing program.

Address of the next program instruction, signals get from the external devices and error messages,
and including different data is saved in the registers. If a CPU includes some registers, therefore a
common bus can link these registers. A general organization of seven CPU registers is displayed in
the figure.

The CPU bus system is managed by the control unit. The control unit explicit the data flow through
the ALU by choosing the function of the ALU and components of the system. Consider R1 ← R2 +
R3, the following are the functions implemented within the CPU −
MUX A Selector (SELA) − It can place R2 into bus A.
MUX B Selector (SELB) − It can place R3 into bus B.
ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).
Decoder Destination Selector (SELD) − It can transfer the result into R1.
The multiplexers of 3-state gates are performed with the buses. The state of 14 binary selection inputs
determines the control word. The 14-bit control word defines a micro-operation.

Encoding of Register Selection Field

Binary Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

There are several micro-operations are implemented by the ALU. Few of the operations implemented
by the ALU are displayed in the table.

Encoding of ALU Operations

OPR Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 ADD A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

ALU Micro-operations
Micro-operation SELA SELB SELD OPR Control Word
R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101
R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010
R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001
R7 ← R1 R1 - R7 TSFA 001 000 111 00000
Output ← R2 R2 – None TSFA 010 000 000 00000
Output ← Input Input - None TSFA 000 000 000 00000
R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000
R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

STACK ORGANIZATION
A stack is a storage device in which the information or item stored last is retrieved first. Basically, a
computer system follows a memory stack organization, and here we will look at how it works.

A portion of memory is assigned to a stack operation to implement the stack in the CPU. Here the
processor register is used as a Stack Pointer (SP). The above figure shows the portion of computer
memory divided into three segments: Program Instructions, Data, and Stack.
 ➢ Program Counter (PC): It is a register that points to the address of the next instruction that is
going to be executed in the program.
➢ Address Register (AR): This register points at the collection of data and is used during the
execute phase to read an operand.
➢ Stack Pointer (SP): It points at the top of the stack and is used to push or pop the data items
in or from the stack.

Stack Pointer is first going to point at the address 3001, and then the stack will grow with the
decreasing addresses. It means that the first item is going to be stored at address 3001, the second
item at address 3000, and the items can keep getting stored in the stack until it reaches the last
address 2000 where the last item will be held.

Here the data which is getting inserted into the Stack is obtained from the Data Register and the data
retrieved from the Stack is also read by the Data Register.

PUSH: This operation is used to insert a new data item into the top of the Stack. The new item can be
inserted as follows: -
SP ←SP-1
M[SP]← DR

POP: This operation is used to delete a data item from the top of the Stack. Data item can be deleted
as follows: -
DR←M[SP]
SP←SP+1

INSTRUCTION FORMAT
In computer organization, instruction formats refer to the way instructions are encoded and
represented in machine language. There are several types of instruction formats, including zero, one,
two, and three-address instructions.

Each type of instruction format has its own advantages and disadvantages in terms of code size,
execution time, and flexibility. Modern computer architectures typically use a combination of these
formats to provide a balance between simplicity and power.
1. Zero Address Instructions: These instructions do not specify any operands or addresses. Instead,
they operate on data stored in registers or memory locations implicitly defined by the instruction. For
example, a zero-address instruction might simply add the contents of two registers together without
specifying the register names.

A stack-based computer does not use the address field in the instruction. To evaluate an expression, it
is first converted to reverse Polish Notation i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed: X = AB+CD+*
TOP means top of stack
M[X] is any memory location
PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
ADD TOP = C+D
MUL TOP = (C+D)*(A+B)
POP X M[X] = TOP

2. One Address Instructions: These instructions specify one operand or address, which typically
refers to a memory location or register. The instruction operates on the contents of that operand, and
the result may be stored in the same or a different location. For example, a one-address instruction
might load the contents of a memory location into a register.

This uses an implied ACCUMULATOR register for data manipulation. One operand is in the
accumulator and the other is in the register or memory location. Implied means that the CPU already
knows that one operand is in the accumulator so there is no need to specify it.
Opcode Operand/Address of operand Mode
Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location
LOAD A AC = M[A]
ADD B AC = AC + M[B]
STORE T M[T] = AC
LOAD C AC = M[C]
ADD D AC = AC + M[D]
MUL T AC = AC * M[T]
STORE X M[X] = AC
3. Two Address Instructions: These instructions specify two operands or addresses, which may be
memory locations or registers. The instruction operates on the contents of both operands, and the
result may be stored in the same or a different location. For example, a two-address instruction might
add the contents of two registers together and store the result in one of the registers.

This is common in commercial computers. Here two addresses can be specified in the instruction.
Unlike earlier in one address instruction, the result was stored in the accumulator, here the result can
be stored at different locations rather than just accumulators, but require a greater number of bits to
represent the address.

Opcode Destination Address Source Address Mode

Here destination address can also contain an operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]
MOV R2, C R2 = M[C]
ADD R2, D R2 = R2 + M[D]
MUL R1, R2 R1 = R1 * R2
MOV X, R1 M[X] = R1

4. Three Address Instructions: These instructions specify three operands or addresses, which may
be memory locations or registers. The instruction operates on the contents of all three operands, and
the result may be stored in the same or a different location. For example, a three-address instruction
might multiply the contents of two registers together and add the contents of a third register, storing
the result in a fourth register.

This has three address fields to specify a register or a memory location. Programs created are much
short in size but number of bits per instruction increases. These instructions make the creation of the
program much easier but it does not mean that program will run much faster because now instructions
only contain more information but each micro-operation (changing the content of the register, loading
address in the address bus etc.) will be performed in one cycle only.

Opcode Destination Address Source Address Source Address Mode

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]
MUL X, R1, R2 M[X] = R1 * R2
ADDRESSING MODES
Addressing Modes– The term addressing modes refers to the way in which the operand of an
instruction is specified. The addressing mode specifies a rule for interpreting or modifying the
address field of the instruction before the operand is actually executed. Addressing modes for 8086
instructions are divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch

The 8086 memory addressing modes provide flexible access to memory, allowing you to easily
access variables, arrays, records, pointers, and other complex data types. The key to good assembly
language programming is the proper use of memory addressing modes. An assembly language
program instruction consists of two parts

Addressing modes used by 8086 microprocessors are discussed below:

1. Implied mode: In implied addressing the operand is specified in the instruction itself. In this mode
the data is 8 bits or 16 bits long and data is the part of instruction. Zero address instruction are
designed with implied addressing mode.

Example: CLC (used to reset Carry flag to 0)

2. Immediate addressing mode (symbol #): In this mode data is present in address field of
instruction. Designed like one address instruction format.
Note: Limitation in the immediate mode is that the range of constants are restricted by size of address
field.

Example: MOV AL, 35H (move the data 35H into AL register)

3. Register mode: In register addressing the operand is placed in one of 8 bit or 16-bit general
purpose registers. The data is in the register that is specified by the instruction.
Here one register reference is required to access the data.

Example: MOV AX, CX (move the contents of CX register to AX register)

4. Register Indirect mode: In this addressing the operand’s offset is placed in any one of the
registers BX, BP, SI, DI as specified in the instruction. The effective address of the data is in the base
register or an index register that is specified by the instruction. Here two register reference is required
to access the data.
MOV AX, [BX](move the contents of memory location s
addressed by the register BX to the register AX)

5. Auto Indexed (increment mode): Effective address of the operand is the contents of a register
specified in the instruction. After accessing the operand, the contents of this register are automatically
incremented to point to the next consecutive memory location. (R1)+. Here one register reference,
one memory reference and one ALU operation is required to access the data.
Example:
Add R1, (R2)+ // OR
R1 = R1 +M[R2]
R2 = R2 + d

6. Auto indexed (decrement mode): Effective address of the operand is the contents of a register
specified in the instruction. Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive memory location. –(R1) Here one
register reference, one memory reference and one ALU operation is required to access the data.
Example:
Add R1,-(R2) //OR
R2 = R2-d
R1 = R1 + M[R2]

7. Direct addressing/ Absolute addressing Mode (symbol [ ]): The operand’s offset is given in the
instruction as an 8 bit or 16 bit displacement element. In this addressing mode the 16-bit effective
address of the data is the part of the instruction. Here only one memory reference operation is
required to access the data.
Example: ADD AL,[0301] //add the contents of offset address 0301 to AL

8. Indirect addressing Mode (symbol @ or () ): In this mode address field of instruction contains
the address of effective address. Here two references are required.
➢ 1st reference to get effective address.
➢ 2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two kinds:
(i) Register Indirect: In this mode effective address is in the register, and corresponding register
name will be maintained in the address field of an instruction. Here one register reference, one
memory reference is required to access the data.
(ii) Memory Indirect: In this mode effective address is in the memory, and corresponding memory
address will be maintained in the address field of an instruction.
Here two memory reference is required to access the data.

9. Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI
or DI and an 8 bit or 16-bit displacement.
Example: MOV AX, [SI +05]

10. Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or
BP and an index register SI or DI.
Example: ADD AX, [BX+SI]
DATA TRANSFER AND MANIPULATION
Data Transfer Instructions: Data transfer instructions move data from one place in the computer to
another without changing the data content. The most common transfers are between memory and
processor registers, between processor registers and input or output, and between the processor
registers themselves.

The load instruction is used to transfer for memory to a processor register, usually an accumulator.
The store instruction is used to transfer data to memory. The move instruction is used to transfer data
from one register to other. It has also been used for data transfers between CPU registers and memory
or between two memory words.

The exchange instruction swaps information between two registers or a register and a memory word.
The input and output instructions transfer data among processor registers and input or output
terminals. The push and pop instructions transfer data between processor registers and a memory
stack.

Data Manipulation Instructions: Data manipulation instructions perform operations on data and
provide the computational capabilities for the computer. The data manipulation instructions in a
typical computer are usually divided into three basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
1. Arithmetic Instructions: The four basic arithmetic operations are addition, subtraction,
multiplication, and division. Most computers provide instructions for all four operations. Some small
computers have only addition and possibly subtraction instructions. The multiplication and division
must then be generated by means of software subroutines. The increment instruction adds 1 to the
value stored in a register or memory word. The decrement instruction subtracts 1 from a value stored
in a register or memory word.
The instruction "add with carry" performs the addition on two operands plus the value of the carry
from the previous computation. Similarly, the "subtract with borrow" instruction subtracts two words
and a borrow which may have resulted from a previous subtract operation. The negate instruction
forms the 2' s complement of a number, effectively reversing the sign of an integer when represented
in the signed-2's complement form.

2. Logical and Bit Manipulation Instructions: Logical instructions perform binary operations on
strings of bits stored in registers. They are useful for manipulating individual bits or a group of bits
that represent binary-coded information. The AND instruction is used to clear a bit or a selected
group of bits of an operand. The OR instruction is used to set a bit or a selected group of bits of an
operand. Similarly, the XOR instruction is used to selectively complement bits of an operand.
Individual bits such as a carry can be cleared, set, or complemented with appropriate instructions.

3. Shift Instructions: Instructions to shift the content of an operand are quite useful and are often
provided in several variations. Shifts are operations in which the bits of a word are moved to the left
or right. The bit shifted in at the end of the word determines the type of shift used. Shift instructions
may specify either logical shifts, arithmetic shifts, or rotate-type operations. In either case the shift
may be to the right or to the left.

The logical shift inserts 0 to the end bit position. The end position is the leftmost bit for shift right and
the rightmost bit position for the shift left.

The arithmetic shift-right instruction must preserve the sign bit in the leftmost position. The sign bit is
shifted to the right together with the rest of the number, but the sign bit itself remains unchanged.
This is a shift-right operation with the end bit remaining the same. The arithmetic shift-left instruction
inserts 0 to the end position and is identical to the logical shift-left instruction.

The rotate instructions produce a circular shift. Bits shifted out at one end of the word are not lost as
in a logical shift but are circulated back into the other end.
PROGRAM CONTROL
Program Control Instructions are the machine code instructions which are used to control the flow of
execution of instructions in the processor domain. These are important in instilling on the processor
how to execute a certain task, access different programs and control the decision making on the basis
of some conditions. They are commonly used in assembly language and generated by high level
language which is compiled into machine code form to enable the processor act in the desired
manner.

Types of Program Control Instructions

1. Compare Instruction: Compare instruction is specifically provided, which is similar to a subtract
instruction except the result is not stored anywhere, but flags are set according to the result.
Example:
CMP R1, R2;

2. Unconditional Branch Instruction: It causes an unconditional change of execution sequence to a

new location.
Example:
JUMP L2
Mov R3, R1 goto L2

3. Conditional Branch Instruction: A conditional branch instruction is used to examine the values
stored in the condition code register to determine whether the specific condition exists and to branch
if it does.
Example:
Assembly Code: BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
High Level Code: if (x==y) goto L1;

4. Subroutines: A subroutine is a program fragment that lives in user space, performs a well-defined
task. It is invoked by another user program and returns control to the calling program when finished.
Example:
CALL and RET

5. Halting Instructions
➢ NOP Instruction – NOP is no operation. It causes no change in the processor state other than
an advancement of the program counter. It can be used to synchronize timing.
➢ HALT – It brings the processor to an orderly halt, remaining in an idle state until restarted by
interrupt, trace, reset or external action.

6. Interrupt Instructions: Interrupt is a mechanism by which an I/O or an instruction can suspend

the normal execution of processor and get itself serviced.
➢ RESET – It reset the processor. This may include any or all setting registers to an initial value
or setting program counter to standard starting location.
➢ TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the highest priority
and vectored interrupt.
➢ INTR – It is level triggered and maskable interrupt. It has the lowest priority. It can be
disabled by resetting the processor.
REDUCED INSTRUCTION SET COMPUTER (RISC)
RISC stands for Reduced Instruction Set Computer Processor, a microprocessor architecture with a
simple collection and highly customized set of instructions. It is built to minimize the instruction
execution time by optimizing and limiting the number of instructions. It means each instruction cycle
requires only one clock cycle, and each cycle contains three parameters: fetch, decode and execute.

The RISC processor is also used to perform various complex instructions by combining them into
simpler ones. RISC chips require several transistors, making it cheaper to design and reduce the
execution time for instruction. Examples of RISC processors are SUN's SPARC, PowerPC,
Microchip PIC processors, RISC-V.

RISC Architecture: It is a highly customized set of instructions used in portable devices due to
system reliability such as Apple iPod, mobiles/smartphones, Nintendo DS,

Features of RISC Processor: Some important features of RISC processors are:

➢ One cycle execution time: For executing each instruction in a computer, the RISC processors
require one CPI (Clock per cycle). And each CPI includes the fetch, decode and execute
method applied in computer instruction.
➢ Pipelining technique: The pipelining technique is used in the RISC processors to execute
multiple parts or stages of instructions to perform more efficiently.
➢ A large number of registers: RISC processors are optimized with multiple registers that can
be used to store instruction and quickly respond to the computer and minimize interaction
with computer memory.
➢ It supports a simple addressing mode and fixed length of instruction for executing the
pipeline.
➢ It uses LOAD and STORE instruction to access the memory location.
➢ Simple and limited instruction reduces the execution time of a process in a RISC.

Advantages of RISC Processor

➢ The RISC processor's performance is better due to the simple and limited number of the
instruction set.
➢ It requires several transistors that make it cheaper to design.
➢ RISC allows the instruction to use free space on a microprocessor because of its simplicity.
➢ RISC processor is simpler than a CISC processor because of its simple and quick design, and
it can complete its work in one clock cycle.
Disadvantages of RISC Processor
➢ The RISC processor's performance may vary according to the code executed because
subsequent instructions may depend on the previous instruction for their execution in a cycle.
➢ Programmers and compilers often use complex instructions.
➢ RISC processors require very fast memory to save various instructions that require a large
collection of cache memory to respond to the instruction in a short time.

COMPLEX INSTRUCTION SET COMPUTER (CISC)

The CISC Stands for Complex Instruction Set Computer, developed by the Intel. It has a large
collection of complex instructions that range from simple to very complex and specialized in the
assembly language level, which takes a long time to execute the instructions. So, CISC approaches
reducing the number of instructions on each program and ignoring the number of cycles per
instruction.

It emphasizes to build complex instructions directly in the hardware because the hardware is always
faster than software. However, CISC chips are relatively slower as compared to RISC chips but use
little instruction than RISC. Examples of CISC processors are VAX, AMD, Intel x86 and the
System/360.

CISC Processors Architecture: The CISC architecture helps reduce program code by embedding
multiple operations on each program instruction, which makes the CISC processor more complex.
The CISC architecture-based computer is designed to decrease memory costs because large programs
or instruction required large memory space to store the data, thus increasing the memory requirement,
and a large collection of memory increases the memory cost, which makes them more expensive.

Characteristics of CISC Processor: Following are the main characteristics of the RISC processor:
➢ The length of the code is shorts, so it requires very little RAM.
➢ CISC or complex instructions may take longer than a single clock cycle to execute the code.
➢ Less instruction is needed to write an application.
➢ It provides easier programming in assembly language.
➢ Support for complex data structure and easy compilation of high-level languages.
➢ It is composed of fewer registers and more addressing nodes, typically 5 to 20.
➢ Instructions can be larger than a single word.
➢ It emphasizes the building of instruction on hardware because it is faster to create than the
software.
Advantages of CISC Processors
➢ The compiler requires little effort to translate high-level programs or statement languages into
assembly or machine language in CISC processors.
➢ The code length is quite short, which minimizes the memory requirement.
➢ To store the instruction on each CISC, it requires very less RAM.
➢ Execution of a single instruction requires several low-level tasks.
➢ CISC creates a process to manage power usage that adjusts clock speed and voltage.
➢ It uses fewer instructions set to perform the same instruction as the RISC.

Disadvantages of CISC Processors

➢ CISC chips are slower than RSIC chips to execute per instruction cycle on each program.
➢ The performance of the machine decreases due to the slowness of the clock speed.
➢ Executing the pipeline in the CISC processor makes it complicated to use.
➢ The CISC chips require more transistors as compared to RISC design.
➢ In CISC it uses only 20% of existing instructions in a programming event.

Difference between the RISC and CISC processors

RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.
It emphasizes on software to optimize the It emphasizes on hardware to optimize the
instruction set. instruction set.
It is a hard-wired unit of programming in the
Microprogramming unit in CISC Processor.
RISC Processor.
It requires multiple register sets to store the It requires a single register set to store the
instruction. instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction.
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
It uses a limited number of instructions that It uses a large number of instructions that
requires less time to execute the instructions. requires more time to execute the instructions.
It uses LOAD and STORE that are independent
It uses LOAD and STORE instruction in the
instructions in the register-to-register a
memory-to-memory interaction of a program.
program's interaction.
CISC has transistors to store complex
RISC has more transistors on memory registers.
instructions.
The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end CISC architecture can be used with low-end
applications like telecommunication, image applications like home automation, security
processing, video processing, etc. system, etc.
It has fixed format instruction. It has variable format instruction.
The program written for RISC architecture Program written for CISC architecture tends to
needs to take more space in memory. take less space in memory.
Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the family, System/360, AMD and the Intel x86
SPARC. CPUs.