Proceedings of the 10th

World Congress on Intelligent Control and Automation

July 6-8, 2012, Beijing, China

A Single Chip Multi-functional DDS Waveform Generator

based on FPGA with SOPC Design Flow
Ruan Yue, Tang Ying, Yao Wen-ji, Wang Zhang-quan and Xu Sen
Zhejiang Shuren University
Hangzhou, Zhejiang Province, China
andyruan729@gmail.com; 600971@zjsru.edu.cn; 25428878@qq.com

Abstract—This work presents a highly integrated single chip an FPGA chip. These methods can change traditional design
multi-functional, multi-waveform signal generator which can flow in electronic systems by reducing separation of modules,
generate various waveforms, with digital controller inside to improve speed, accuracy and reconfiguration. But there still
adapt embedded and low power applications. The proposed have inconvenient and inflexible problems when adding
system is composed by Nios II, DDS (Direct Digital Synthesis) peripheral devices such as MCUs or DDS chip, which make
and other peripherals. Nios II is a reconfigurable, programmable
and optimizable soft-core embedded CPU. DDS is used to
the system heterogeneous. [1][2]
generate required waveforms. Together with modern EDA tools, In order to design the fully digital multi-functional
the system HW/SW co-design and FPGA implementation is generator as a true SOPC system, we choose the solution using
accomplished, using typical SOPC design flow. Utilizing Nios II soft processor and Quartus II by Altera. In the
characteristics of Nios II, the core and peripheral logical units
that system need are put together and implanted into a single proposed design, modules necessary to the system, such as
FPGA chip. The Avalon bus is used to connect peripheral DDS, memory, keyboard and display controller are all
modules (such as function switch buttons and 7-segment LED embedded to an FPGA chip by HDL design. Nios II’s Avalon
display units) to Nios II's Avalon bus main port (instruction and bus main port (instruction and data control port) is then
data control port). The realized system is flexible to reduce, connected with peripherals such as high-speed D/A convertor,
extend, with low power consumption, and has System on function choose button and LCD display module. This
Programmable Chip (SOPC) function which means the system’s connection is via Avalon bus. In this way, the system realized
software and hardware is online programmable. is flexible, scalable, extensible, upgradable and has online
Index Terms - SOPC, Nios II, DDS, signal generator, FPGA programmable function.

I. INTRODUCTION II. OVERALL SYSTEM ARCHITECTURE

A multi-functional signal generator is a device that can The proposed system of multi-functional multi-waveform
output various types of signal waveforms, such as sine wave, signal generator can output various waveforms, such as sine
saw tooth wave, square wave, triangle wave, trapezoidal wave wave, saw tooth wave, square wave, triangle wave and
and so on. It can also control the slope, gradient, width of the trapezoidal wave, with frequency ranging from 1Hz to 20MHz.
waveform digitally and numerically, with FM & PM functions. The system is composed by two parts: FPGA hardware design
As modern electronic devices become smaller and smaller, and software design based on hardware. The whole digital part
while their functions more and more complex, the multi- of the design is implemented by an FPGA chip. The buttons,
functional multi-waveform signal generator is designed LED display and high-speed D/A convertors are peripherals
toward the directions of high integration, high reliability and and are ready-made on FPGA development board.
lower power consumptions. These trends in signal generator Figure 1 below shows the overall architecture of the
design are to cope with applications in rapid developing proposed system.
communication fields such as wireless sensor networks
(WSN), software-defined radio (SDR) and ultra-wideband
(UWB), where smart and flexible signal/pulse generators are
needed. [3]
Nowadays, there are two different approaches to
implement such kind of signal generator: one approach is
using Direct Digital Synthesizer (DDS) ASIC in market (such
as AD9850 and AD9852) and FPGA for system control, plus
high-speed D/A convertors. This method is expensive,
although with good performance. The other one is using DDS
designed by Hardware Description Language (HDL) or related
soft IP core, plus waveform data storage memory and MCU to
realize control function. In this approach, the DDS is
implemented by downloading the synthesized HDL design to

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 toolkit is also used to accomplish the FPGA hardware system
and software based on FPGA.

A. Nios II System Hardware Development Process

The basic software tools used in SOPC system design are
Quartus II, SOPC Builder, Modelsim, Matlab/DSP Builder
and GNU Pro. Quartus II, an IDE provided by Altera, is used
for synthesis, hardware optimization, fitting, programming
download and hardware tests of Nios II system. SOPC Builder,
a Nios II embedded processor development toolkit provided
by Altera, is used to realize and generate the configuration,
monitoring and software debugging platform of Nios II system.
Modelsim is used in system functional simulation for the HDL
description of Nios II generated by SOPC Builder.
Matlab/DSP Builder can be used to design customized
hardware accelerator for Nios II. And GNU Pro is used in
software debugging.
In the development of traditional embedded system, the
hardware architecture of CPU is unchangeable. As a result, the
alterations of peripheral devices are limited by CPU, which
Fig. 1 Proposed System Architecture may lead to a wholly fixed embedded system. When we need
Inside the FPGA, Nios II soft-core CPU performs as to add new peripheral modules, we would either add
controlling core, and DDS IP module as achievement core for corresponding peripheral chips or switch to higher level CPUs,
waveform generation functions. At the same time, other IP which is inconvenient. The development of Nios II system is
cores are added, such as debug module, UART (Universal different. Nios II is a flexible customized soft-core CPU, its
Asynchronous Receiver & Transmitter) module used to peripheral devices are optional IP core or self-customized
communicate with PC, seven-segment LED display decoding logic. Users can customize appropriate SOPC system using
and I/O module, and button control module. These IP cores SOPC Builder’s wizard-style interface, according to system
can be designed into a single FPGA, making the system highly design requirements. As a result, In SOPC design, we can add
integrated. [3][4] corresponding peripheral modules outside the CPU core while
In this design, FPGA hardware system is realized by still inside FPGA chip. The connection between peripheral and
VHDL language, parameterized macro-functional module Nios II core is via Avalon bus, thus do not need to modify on
provided by Altera, LPM functions and IP cores in DSP PCB level. The detailed Nios II hardware design process is
Builder. Subsystem blocks such as DDS module can also be presented in Figure 2. This development process is used to
designed and synthesized by the above methods. According to customize proper CPU and peripheral device, and realize them
Avalon bus connection specification, OPB (On chip Peripheral via SOPC Builder in Quartus II.
Bus) is added outside the DDS module, which are packaged Figure 2 below shows the complete design process of
together into a customized IP core. This IP core is added in the Nios II application system using SOPC design methodology.
FPGA hardware system and generates digital control signals. The design process has two main lines: hardware development
The peripheral circuit contains keyboard, LCD display and and software development, which are combined into Nios II
high-speed D/A convertor DAC5651. The peripheral circuit is using SOPC Builder.
used to accomplish control input and I/O display, transform
waveform data to analog waveform. Thus realizes a complete
SOPC signal generator.
The software design based on Nios II is similar to
traditional embedded software development process. First,
write program codes according to CPU’s instruction set and
compilation environment. After compiling, programming the
code into FPGA and debug it.

III. HARDWARE DESIGN

The hardware design adopts the methodology of SOPC,
with the whole SOPC system divided into 3 parts: FPGA,
memory and external interfaces. In the design process, we use
Altera’s Cyclone® EP1C3TC144 FPGA chip. Quartus II IDE
(Integrated Development Environment) with SOPC Builder

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 +DUGZDUH'HYHORSPHQW 6RIWZDUH'HYHORSPHQW
Develop drivers or
Customized peripheral,
subroutines for
instructions
customized hardware
(Using SOPC Builder and module
Quartus II) ( Using SOPC Builder )
Customize
Define Nios II system SDK OS Transplant
module
(SOPC (SOPC Builder)
( SOPC Builder )
Builder)
Generate Nios II Write Application
system module programs
( SOPCBuilder ˅ (SOPC Builder)

Lock pins, hardware Compile, connect,

compilation debug
Quartus II Downloading (SOPC Builder)

FPGA Hardware Software Prototype Fig. 3 Specific Programmable Hardware System

Prototype Design Design
( Nios Development ( Nios Development In this proposed system, Nios II core is 32-bit embedded
Board ) Board ) soft-core. Boot ROM is made up by embedded RAM block
M4K in FPGA and is used in system boot. GERMS Monitor
program can be used to debug this module. Button_PIO is
used as PIO interfaces of buttons. 7-segment LED PIO is used
SOPC System as LED display interface. UART is a common serial port, and
Implementation
based on Nios II
SOPC system can use it to communicate with PC or other
devices. UART can also be used in Nios II system simulation
and debugging. The program memory is implemented using
SRAMs inside FPGA, and connects to Nios II CPU via LMB
(Local Memory Bus), which realizes Read/Write access from
Fig. 2 Nios II System Development Flowchart
CPU.
B. Specific Hardware System Design The system is also scalable. In case the RAM inside
FPGA is not enough, we can use Avalon tri-state Bus Bridge
The proposed system in this work is a SOPC system
to connect external SRAM and Flash into the Nios II system.
based on Nios II soft-core. Nios II works as the embedded Here, the SRAM in the system is similar to memory in PC,
CPU which controls peripheral modules and devices of the while Flash memory similar to HDD. The DDS module is a
system. The peripheral includes 1 UART port, 8 LEDs with self-written IP core. All IP cores used in proposed system can
seven segments, 9 buttons, customized DDS IP core and be customized using SOPC Builder, which means the
memory used to store waveform data. parameters of IP cores such as characteristics, storage capacity
and I/O mode can be determined in the options of SOPC
Figure 3 below shows the programmable hardware Builder’s software menu. All peripheral IP cores can be
system composed by various IP cores on FPGA. These IP connected to Nios II core through on-chip Avalon Bus.
cores are connected by Avalon Bus, a simple bus architecture
In the system, DDS module is designed by SOPC Builder
designed for connecting on-chip processors and peripherals
and Matlab / DSP Builder. After finishing the detailed design
together into SOPC system. The Avalon bus is an interface
of DDS module in Matlab/Simulink, DSP builder will
that specifies the port connections between master and slave automatically convert DDS block diagram to VHDL code.
components, and specifies the timing by which these Figure 4 shows the detailed model diagram of DDS module.
components communicate. The modeling of DDS module is realized using Simulink with
Altera’s DSP Builder toolbox installed.

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 JTAG port. At this point, the hardware development process
of SOPC system based on Nios II is finished. The next work is
to design software and debug it in the Nios II embedded
system established in FPGA.

IV. SOFTWARE DESIGN

After the proposed hardware system is compiled in SOPC
Builder and software pack SDK generated, we can then
conduct software design of the system.
The software architecture is designed as button-
centralized. Operations to LEDs, buttons, D/A convertors are
all treated as operations to PIO (button_pio) port registers. The
connections to these peripherals all use PIO way. LED and
Fig. 4 DDS Design Diagram DAC use PIO output mode, while button uses input mode. A
In Figure 4 above, there are 3 input ports. Port 1 is the key interrupt is set in button PIO. The main program flow
amplitude control word input; port 2 is phase control word diagram is shown in the following figure.
input, and port 3 frequency control word input. These 3 inputs
can control the amplitude, phase and frequency of the output
waveform. The DDS module outputs the controllable Start
waveform by changing the control words in corresponding
input registers. In the peripheral sphere, I/O interface files are
generated through SOPC Builder. After that, the bus interface, Initialization
which works as a custom IP, is added outside DDS module
and successfully mounted to the system bus. The interface can
realize communications between DDS module and Nios II,
while doing Read/Write operations easily. Figure 5 in the
following presents the implementation process between user
logic and DDS IP. Read and decide
whether button
state changes N
DDS IP Core
DDS Function IP Interface Files Y
Logic Module
Button
process
program
PIO

IP Interface Files Output signal

UART
and display
DDS Module
DDS IP Core
Fig. 6 Main Program Flow Diagram

Mounted on Avalon Bus

In the main program flow diagram shown in Figure 6, the

Fig. 5 DDS IP Implementation Process program is first initialized, which means all the instructions,
status, variables and memory units are reset to initial state.
After the construction of hardware system using SOPC After initialization, the program begins key scanning process.
Builder, we choose generating SDK development program, This process is used to determine whether any key or button is
VHDL system description and simulation files through pressed. If no key is pressed, the program repeats detecting
operations in SOPC Builder. Click “Generate” button, SOPC key pressing event, after a certain time. If any key is pressed,
Builder will automatically generate customized SOPC system. the program turns to button processing subroutine and do
At the same time, HDL files used in Quartus II compilation relevant operations. The output signal waveform is sent to
are also generated. After that, the generated SOPC system is display circuits.
transferred as a component in block diagram. The system is The button processing subroutine is an important block in
compiled in Quartus II after its pins added and locked. Finally, system software design. Almost all functions are realized
the compiled SOF file is programmed into FPGA chip via using it. There are a number of buttons used to choose

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 waveform types generated. In this system, the button number In this system, Nios II processor works as core, with
is 6. This subroutine is used to detect which button is pressed customized DDS IP and necessary peripheral modules. The
and then accomplishes the responses from buttons, generates main advantage of the proposed system over traditional one is
the desired signal waveform by calling for DDS module. The its hardware and software co-design using SOPC design
output signal waveforms can be sine wave, saw tooth wave, methodology. The core components of signal generator, such
square wave, triangle wave, trapezoidal wave and so on, as DDS and memory (waveform storage) are designed using
depending on the button pressed. After that, the program block VHDL or IP cores, and implemented on FPGA. Other
orders DDS module to send waveform data to high speed D/A functions such as the control of external devices (such as
converters. Figure 7 below presents the flow diagram of the button, display, DACs), choosing of output waveform types
button processing subroutine. and calculation of waveform parameters are implemented via
C programming. The program runs on Nios II CPU inside
FPGA and do not need MCUs to control FPGA.
Button
Processing The proposed fully digital signal generator based on
SOPC has advantages of hardware reconfigurable and flexible,
which makes the system design easy to modify and
Read Key
consummate. The SOPC design methodology used in this
Value N work also provides a novel approach to modern electronic
system design.
Choose
according to N VI. ACKNOWLEDGEMENT
This work was financially supported by the natural
science foundation of Zhejiang Province (ZJNSF), with
N=1 N=2 N=6 project number: Y105346.

Sine Sawtooth Trapezoidal

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