Ordering number : ENN*5190A

CMOS IC

LC651204N/F/L,LC651202N/F/L
4-Bit Single-Chip Microcontroller for
Small-Scale Control Applications
Preliminary
Overview
The LC651204N/F/L and LC651202N/F/L are small-scale application microcontroller products in Sanyo’s LC6500 series
of 4-bit single-chip CMOS microcontrollers, and as such they fully support the basic architecture and instruction set of that
series. These microcontrollers are provided in a 30-pin package and include 2 kilobytes (KB) and 4 KB of on-chip ROM.
These products are appropriate for use in a wide range of applications, from applications that use a small number of controls
and circuits that were previously implemented in standard logic to larger scale applications including audio equipment such
as decks and players, office equipment, communications equipment, automotive equipment, and home appliances. Except
for the lack of an A/D converter, these microcontrollers provide the same functionality as the LC651104, 02N/F/L.

Features
(1) Fabricated in a CMOS process for low power (An instruction-controlled standby function is provided.)
(2) ROM/RAM LC651204N/F/L - ROM: 4K × 8 bits, RAM: 256 × 4 bits
LC651202N/F/L - ROM: 2K × 8 bits, RAM: 256 × 4 bits
(3) Instruction set: The 80-instruction set provided by all members of the LC6500 series.
(4) Wide operating power-supply voltage range of 2.5 to 5.5 volts (L version)
(5) Instruction cycle time: 0.92µs (F version)
(6) On-chip serial I/O circuit
(7) Highly flexible I/O ports
- Number of ports: 6 ports with a total of 22 pins
- All ports: Can be used for both input and output
I/O voltage: 15V maximum (Only for C, D, E, and F ports with open-drain output specifications)
Output current: 20mA maximum sink current (Capable of directly driving LEDs.)
- Options that allow specifications to be customized to match those of the application system.
Specification of open-drain output or built-in pull-up resistor: Can be specified for all ports in bit units.
Specification of the output level at reset: Can be specified to be high or low for ports C and D in port units.
(8) Interrupt functions
- Timer overflow vector interrupt (The interrupt state can be tested by the CPU.)
- Vector interrupts initiated by the INT pin or full/empty states of the serial I/O circuit. (The interrupt state can be
tested by the CPU.)
(9) Stack levels: 8 levels (shared with interrupts)
(10) Timers: 4-bit prescaler plus 8-bit programmable timers
(11) Clock oscillator options to match application system specifications.
- Oscillator circuit options: 2-pin ceramic oscillator (N, F and L versions)
- Divider circuit option: No divider, built-in divide-by-three circuit, built-in divide-by-four circuit (N and L versions)
(12) Supports continuous output of a square wave signal (with a period 64 times the cycle time)
(13) Watchdog timer
- RC time constant scheme
- A watchdog timer function can be allocated to one of the external pins as an option.
(14) EP version: LC65E1104, OTP version: LC65P1104

Ver.1.00 D2700 RM (IM) IT No.5190-1/38

11996
 LC651204N/F/L,LC651202N/F/L

Package Dimensions
(unit : mm) (unit : mm)
3073A 3196A
[LC651204N/F/L, 651202N/F/L] [LC651204N/F/L, 651202N/F/L]

SANYO : MFP-30S SANYO : DIP-30SD

[Notes]
The package drawings shown above are provided without error tolerances and are for reference purposes only. Contact
Sanyo for official package drawings.

Function Overview
Item LC651204N/1202N LC651204F/1202F LC651204L/1202L
Memory ROM 4096×8 bits(1204N) 4096×8 bits(1204F) 4096×8 bits(1204L)
2048×8bits(1202N) 2048×8 bits(1202F) 2048×8 bits(1202L)
RAM 256×4 bits(1204/1202N) 256×4 bits(1204/1202F) 256×4 bits(1204/1202L)
Instruction Instruction set 80 80 80
Table reference Supported Supported Supported
Built-in functions Interrupts 1 external, 1 internal 1 external, 1 internal 1 external, 1 internal
Timers 4-bit prescaler+8-bit timer 4-bit prescaler+8-bit timer 4-bit prescaler+8-bit timer
Stack levels 8 8 8
Standby function Supports standby mode entered by the Supports standby mode entered by the Supports standby mode entered by the
HALT instruction HALT instruction HALT instruction
I/O ports Number of ports 22 I/O pins 22 I/O pins 22 I/O pins
Serial ports 4-bit or 8-bit I/O 4-bit or 8-bit I/O 4-bit or 8-bit I/O
I/O voltage 15V max. 15V max. 15V max.
Output current 10mA typ. 20mA max. 10mA typ. 20mA max. 10mA typ. 20mA max.
I/O circuit types Open drain (n-channel) or built -in pull-up resistor output selectable on a per-bit basis.
Output levels at reset High or low can be selected in port units. (ports C and D only)
Square wave output Supported Supported Supported
Characteristics Minimum cycle time 2.77µs (VDD≥3V) 0.92µs (VDD≥3V) 3.84µs (VDD≥2.5V)
Power-supply voltage 3 to 5.5V 3 to 5.5V 2.5 to 5.5V
Power-supply current 1.5mA typ. 2mA typ. 1.5mA typ.
Oscillator Oscillator Ceramic (800K, 1MHz, 4MHz) Ceramic (4MHz) Ceramic (800K, 1MHz, 4MHz)
Divider circuit option 1/1, 1/3, 1/4 1/1 1/1, 1/3, 1/4
Other functions Package DIP30S-D MFP30S DIP30S-D MFP30S DIP30S-D MFP30S
[Notes]
Sanyo will announce details on oscillator elements and oscillator circuit constants as recommended application circuits are
developed. Customers should check with Sanyo for the latest information as the development process progresses.

No.5190-2/38
 LC651204N/F/L,LC651202N/F/L

Pin Assignment

Common assignments for the DIP and MFP packages

26 PE1/WDR

16 PF3/INT
30 PA3

29 PA2

28 PA1

27 PA0

24 PD3

23 PD2

22 PD1

21 PD0

20 PC3

19 PC2

18 PC1

17 PC0
25 PE0
LC651432N/F/L
LC651431N/F/L

VDD 10

RES 11

TEST 12

PF0/SI 13

PF1/SO 14

PF2/SCK 15
1

9
VSS
PG0

PG1

PG2

PG3

OSC1

OSC2
NC

NC

[Notes]
NC pins must be connected to VSS. Top view

Pin Functions

Pin Function
OSC1, OSC2 Connections for a ceramic oscillator element
RES Reset
PA0 to 3 I/O dual-function port A0 to A3
PC0 to 3 I/O dual-function port C0 to C3
PD0 to 3 I/O dual-function port D0 to D3
PE0 to 1 I/O dual-function port E0 to E1
PF0 to 3 I/O dual-function port F0 to F3
PG0 to 3 I/O dual-function port G0 to G3
TEST Test
INT Interrupt request
SI Serial input
SO Serial output
SCK Serial clock input and output
NC No connection
WDR Watchdog reset

[Notes]
The SI, SO, SCK and INT pins are shared function pins that are also used as PF0 to PF3.

No.5190-3/38
 LC651204N/F/L,LC651202N/F/L

System Block Diagram

LC651204N/F/L, LC651202N/F/L

PA0-3 Port A RAM PC ROM

F WR

I/O Buffer
STACK 1
to
DP
STACK 8
IR I.DEC
PG0-3 Port G

PC0-3 Port C System Bus

PD0-3 Port D E AC STS

CF ZF EXTF TMF
TM CTL
ALU CSF ZSF F
Serial INT
PF1/SO shift Serial Serial
4/8 bit register mode mode
register register OSC1
Shared with port F

OSC
lower digit OSC2

I/O Bus RES

Serial TEST
4 bit shift
register VDD
Port E Port F VSS
higher digit
PF0/SI 4/8 bit
PF2/SCK PE0-1 WDR PF0-3
PF3/INT

RAM : Data memory ROM : Program memory

F : Flag PC : Program counter
WR : Working register INT : Interrupt control
AC : Accumulator IR : Instruction register
ALU : Arithmetic and logic unit I.DEC : Instruction decoder
DP : Data pointer CF, CSF : Carry flag, carry save flag
E : E register ZF, ZSF : Zero flag, zero save flag
CTL : Control register EXTF : External interrupt request flag
OSC : Oscillator circuit TMF : Internal interrupt request flag
TM : Timer
STS : Status register

No.5190-4/38
 LC651204N/F/L,LC651202N/F/L

Development Support
Sanyo provides the following items to support application development using the LC651204 and LC651202.

1. User’s manual
The “LC651104/1102 User’s Manual” is used with these microcontrollers.
2. Development tool manual
See the “EVA800-LC651104/1102 Development Tool Manual” for details on use of the EVA-800 system.
3. Development tool
• Program development (using the EVA-800 system)
- MS-DOS host computer system *1
- Cross assembler ... MS-DOS-based cross assembler: LC65S.EXE
- Evaluation chip: LC6595
- Emulator: The EVA-800 main unit plus the evaluation chip
• Program development (using the EVA-800 system): Use the EVA86K-ECB651100.
• Program evaluation
The <LC65E1104> on-chip EPROM microcontroller

Development Support System

EVA-800 System

• Host control program

• LC65S cross assembler

MS-DOS host computer

Emulator (Note 2)
EVA-800 or EVA-850

CN1,CN2

LC6595

CN4
Evaluation chip board
EVA800-TB6529/01XX/11XX/12XX
NFP50A

CABLE8

TB43S

Application product PCB

[Notes]
1. MS-DOS is a registered trademark of Microsoft Corporation
2. Here, “EVA-800” is a generic tem for several emulators. Suffixes (A, B, etc.) will be attached to the name as new
versions are developed. Note that the EVA-800 emulator (i.e., the model with no suffix) is an old version and cannot be
used.

No.5190-5/38
 LC651204N/F/L,LC651202N/F/L

Pin Functions

Handling when
Pin Pin no. I/O Function Option State at reset
unused
VDD 1 - Power supply - - -
VSS 1 -
OSC1 1 Input • System clock oscillator (1) External clock - -
OSC2 1 Output Connect an external ceramic (2) Two-pin ceramic oscillator
oscillator element to these pins (3) Divider circuit option
• Leave OSC2 open if an external 1. No divider circuit
clock is supplied. 2. Divide-by-three circuit
3. Divide-by-four circuit
PA0 4 I/O • I/O port A0 to A3 (1) Output open drain High-level output Open drain output
to Input in 4-bit units using the IP (2) Built-in pull-up resistor (i.e., the output select the options,
PA3 instruction • Options (1) and (2) can be n-channel transistor will connect to VSS
Output in 4-biit units using the OP specified in bit units. be off.)
instruction
Port bits can be tested in bit units
using the BP and BNP
instructions.
Port bits can be set or cleared in bit
units using the SPB and RPB
instructions.
• PA3 is used for standby control.
• Applications must be designed so
that no chattering (e.g. switch
bounce) occurs on the PA3 pin
during a HALT instruction
execution cycle.
PC0 4 I/O • I/O port C0 to C3 (1) Output open drain • High-level output The same as PA0 to
to The PC0 to PC3 pin functions (2) Built-in pull-up resistor • Low-level output PA3.
PC3 are identical to those of the (3) High-Level output at reset (Depending on the option
PA0 to PA3 pins. * (4) Low-Level output at reset specified.)
• High or low can be specified as the • Options (1) and (2) can be
output at reset as an option. specified in bit units
Note: These pins do not have • Options (3) and (4) are specified
a standby control function. in 4-bit units
PD0 4 I/O • I/O port D0 to D3 The same as PC0 to PC3. The same as PC0 to PC3. The same as PA0 to
to The PD0 to PD3 pin functions and PA3.
PD3 options are identical to those of the
PC0 to PC3 pins.
Continued on next page.

No.5190-6/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Handling when
Pin Pin no. I/O Function Option State at reset
unused
PE0 2 I/O • I/O port E0 to E1 (1) Output open drain High-level output The same as PA0 to
to Input in 4-bit units using the IP (2) Built-in pull-up resistor (i.e., the output PA3.
PE1 instruction • Options (1) and (2) can be (ii.n-channel transistor
/WDR Output in 4-biit units using the OP specified in bit units. will be off.)
instruction (3) Normal port PE1
Port bits can be set or cleared in bit (4) Watchdog timer reset WDR
units using the SPB and RPB (5) (3) or (4) can be specified.
instructions.
Port bits can be tested in bit units
using the BP and BNP instructions.
• The PE0 pin also has a
continuous pulse (64-Tcyc) output
function.
• The PE1 pin can be set to
function as the WOR
watchdog timer reset pin as an option.
PF0/SI 4 I/O • I/O port F0 to F3 The same as PA0 to PA3. The same as PA0 to The same as PA0 to
PF1/SO This port has the same functions and PA3. PA3.
PF2/ SCK options as PE0 to PE1. * The serial port
PF3/ INT • The pins PF0 to PF3 are also used as function is disabled.
the serial interface and the INT pin. The interrupt source
The function used can be selected is INT .
under program control.
SI Serial input port
SO Serial input port
SCK Serial clock input or
output
INT Interrupt request input
Serial I/O can be switched between
4-bit and 8-bit operation under
program control.
Note: This port does not
provide a continuous
pulse output function.
PG0 4 I/O • I/O port G0 to G3 The same as PA0 to PA3. The same as PA0 to The same as PA0 to
to This port has the same functions and PA3. PA3.
PG3 options as PE0 to PE1. *
Note: This port does not
provide a continuous
pulse output function.
NC 2 • NC pin. This pin must be connected - - Connect to VSS.
to VSS in the EP and OTP versions.
RES 1 Input • System reset input - - -
• Connect an external capacitor for
the power up reset.
• A low level must be applied for at
least four clock cycles for the reset
startup sequence to operate correctly.
TEST 1 Input • LSI test pin - - Must be connected to
Must be connected to VSS. VSS.

No.5190-7/38
 LC651204N/F/L,LC651202N/F/L

Oscillator Circuit Options

Option Circuit Conditions and notes

External clock The OSC2 pin must be left open.
OSC1

Ceramic oscillator
C1 OSC1

Ceramic oscillator OSC2

element
C2 R

Divider Options

Option Circuit Conditions and notes

No divider (1/1) • Supports both oscillator options.
• The oscillator frequency or the external clock
frequency must not exceed 1444 kHz (LC651204N
circuit

Timing generator

and LC651202N)
fOSC • The oscillator frequency or the external clock
Oscillator

frequency must not exceed 4330 kHz (LC651204F

and LC651202F)
• The oscillator frequency or the external clock
frequency must not exceed 1040 kHz (LC651204L
and LC651202L)
Built-in divide-by-three circuit • Supports both oscillator options.
• The oscillator frequency or the external clock
circuit

Timing generator

fOSC frequency must not exceed 4330 kHz

3
Divide-by-three-circuit
Oscillator

Built-in divide-by-four circuit • Supports both oscillator options.

circuit

• The oscillator frequency or the external clock

Timing generator

fOSC
frequency must not exceed 4330 kHz
4
Oscillator

Divide-by-four-circuit

[Caution]
The oscillator and divider options are summarized in the following tables. The information presented in those tables is
crucial when using these products.

No.5190-8/38
 LC651204N/F/L,LC651202N/F/L
Divider Options for the LC651204N/1202N, LC651204F/1202F and LC651204L/1202L

LC651204N/1202N
Circuit type Frequency Divider option (cycle time) VDD range Notes
Ceramic oscillator 800kHz 1/1 (5µs) 3 to 5.5V
1MHz 1/1 (4µs) 3 to 5.5V
4MHz 1/3 (3µs) 3 to 5.5V This frequency cannot be used with the 1/1
1/4 (4µs) 3 to 5.5V divider (i.e., no divider circuit) option.
External clock generated by a 670k to 1444kHz 1/1 (6 to 2.77µs) 3 to 5.5V
two-terminal RC oscillator circuit 2000k to 4330kHz 1/3 (6 to 2.77µs) 3 to 5.5V
2600k to 4330kHz 1/4 (6 to 3.70µs) 3 to 5.5V
Use of external clock with the Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator
ceramic oscillator option selected option.

LC651204F/1202F
Circuit type Frequency Divider option (cycle time) VDD range Notes
Ceramic oscillator 4MHz 1/1 (1µs) 3 to 5.5V
External clock generated by a 670k to 4330kHz 1/1 (6 to 0.92µs) 3 to 5.5V
two-terminal RC oscillator circuit
Use of external clock with the Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator
ceramic oscillator option selected option.

LC651204L/1202L
Circuit type Frequency Divider option (cycle time) VDD range Notes
Ceramic oscillator 800kHz 1/1 (5µs) 2.5 to 5.5V
1MHz 1/1 (4µs) 2.5 to 5.5V
4MHz 1/4 (4µs) 2.5 to 5.5V This frequency cannot be used with the 1/1, 1/3
divider (i.e., no divider circuit) option.
External clock generated by a 670k to 1040kHz 1/1 (6 to 3.84µs) 2.5 to 5.5V
two-terminal RC oscillator circuit 2000k to 3120kHz 1/3 (6 to 3.84µs) 2.5 to 5.5V
2600k to 4160kHz 1/4 (6 to 3.84µs) 2.5 to 5.5V
Use of external clock with the Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator
ceramic oscillator option selected option.

No.5190-9/38
 LC651204N/F/L,LC651202N/F/L

Port C and D Output State at Reset Options

The output levels at reset of the I/O ports C and D can be selected form the following two options, which are specified in 4-bit
units.

Option Conditions and notes

High-level output at reset Ports C and D in 4-bit units
Low-level output at reset Ports C and D in 4-bit units

Port Output Circuit Type Option

The output circuit types of the I/O ports can be selected form the following two options in bit units.

Option Circuit Conditions and notes

Open drain output Ports A, C, D, E, F and G

Pull-up resistor output

Watchdog Timer Reset Option

Whether the PE1/WDR pin functions as the normal port PE1 or as the WDR watchdog timer reset pin can be selected as an
option.

No.5190-10/38
 LC651204N/F/L,LC651202N/F/L
LC651204N, LC651202N
Absolute Maximum Ratings at VSS=0V and Ta=25°C

Parameter Symbol Applicable pins/notes Conditions Ratings unit

Maximum supply voltage VDD max VDD -30 to +7.0 V
Output voltage VO OSC2 Voltages up to any
generated voltage are
allowed.
Input voltage VI (1) OSC1 *1 -0.3 to VDD +0.3
VI (2) TEST, RES -0.3 to VDD +0.3
I/O voltage VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 OD specification ports -0.3 to +15
VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PU specification ports -0.3 to VDD +0.3
VIO (3) PA0 to 3, PG0 to 3 -0.3 to VDD +0.3
Peak output current IOP I/O ports -2 to +20 mA
Average output current IOA Average value per pin over a 100-ms I/O ports -2 to +20
period
Σ IOA (1) Total current for pins PC0 to 3, PD0 to 3, PC0 to PC3 -15 to +100
and PE0 to 1*2 PD0 to PD3
PE0 to PE1
Σ IOA (2) Total current for pins PF0 to 3, PG0 to 3, PF0 to PF3 -15 to +100
and PA0 to 3*2 PG0 to PG3
PA0 to PA3
Allowable power dissipation Pd max(1) Ta = -40 to +85°C (DIP package) 250 mW
Pd max(2) Ta = -40 to +85°C (MFP package) 150
Operation temperature Topr -40 to +85 °C
Storage temperature Tstg -55 to +125

Allowable Operating Range at Ta=-40°C to +85°C, VSS=0V, VDD=3.5 to 5.5V

(unless otherwise specified)
Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Operating VDD VDD 3.0 5.5 V
power-Supply
voltage
Standby VST RAM and register values retained *3 VDD 1.8 5.5
power-Supply
voltage
Input high-level VIH(1) Output n-channel transistors off OD specification ports C, D, E, and F 0.7VDD 13.5
voltage

VIH(2) Output n-channel transistors off PU specification ports C, D, E, and F 0.7VDD VDD
VIH(3) Output n-channel transistors off Port A, G 0.7VDD VDD
VIH(4) Output n-channel transistors off The INT , SCK , and SI pins with OD 0.8VDD 13.5
specifications
VIH(5) Output n-channel transistors off The INT , SCK , and SI pins with PU 0.8VDD VDD
specifications
VIH(6) VDD = 1.8 to 5.5V RES 0.8VDD VDD
VIH(7) External clock specifications OSC1 0.8VDD VDD
Continued on next page.

No.5190-11/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Applicable Ratings
Parameter Symbol Conditions unit
pins/notes min. typ. max.
Input low-level VIL(1) Output n-channel transistors off VDD = 4 to 5.5V Port VSS 0.2VDD V
voltage VIL(2) Output n-channel transistors off VDD = 3 to 5.5V Port VSS 0.2VDD
VIL(3) Output n-channel transistors off VDD = 4 to 5.5V INT , SCK ,SI VSS 0.2VDD
VIL(4) Output n-channel transistors off VDD = 3 to 5.5V INT , SCK ,SI VSS 0.2VDD
VIL(5) External clock specifications VDD = 4 to 5.5V OSC1 VSS 0.2VDD
VIL(6) External clock specifications VDD = 3 to 5.5V OSC1 VSS 0.2VDD
VIL(7) VDD = 4 to 5.5V TEST VSS 0.2VDD
VIL(8) VDD = 3 to 5.5V TEST VSS 0.2VDD
VIL(9) VDD = 4 to 5.5V RES VSS 0.2VDD
VIL(10) VDD = 3 to 5.5V RES VSS 0.2VDD
Operating fop Frequencies up to 4.33MHz are supported VDD = 3 to 5.5V 670 1444 kHz
frequency (Tcyc) if the divide-by-three or divide-by-four (6) (2.77) (µs)
(cycle time) divider circuit option is used.
External clock text Figure 1. The divide-by-three or VDD = 3 to 5.5V OSC1 670 4330 kHz
conditions divide-by-four divider circuit option
Frequency must be used if the clock frequency
Pulse width textH, exceeds 1.444MHz. VDD = 3 to 5.5V OSC1 69 ns
Rise and fall textL
times textR, VDD = 3 to 5.5V OSC1 50
textF
Guaranteed Figure 2 See
oscillator Table 1.
constants
Ceramic
oscillator

No.5190-12/38
 LC651204N/F/L,LC651202N/F/L

Electrical Characteristics at Ta=-40°C to +85°C, VSS=0V, VDD=3.0 to 5.5V

(unless otherwise specified)
Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Input high-level IIH(1) Output n-channel transistors off Ports C, D, E, and F with 5.0 µA
current (Includes the n-channel transistors off leakage open-drain
current.) VIN= 13.5V specifications
IIH(2) Output n-channel transistors off Ports A and G with 1.0
(Includes the n-channel transistors off leakage open-drain
current.) VIN= VDD specifications
IIH(3) External clock mode, VIN= VDD OSC1 1.0
Input low-level current IIL(1) Output n-channel transistors off Ports with open-drain -1.0
VIN= VSS specifications
IIL(2) Output n-channel transistors off Ports with pull-up -1.3 -0.35 mA
VIN= VSS resistor specifications
IIL(3) VIN= VSS RES -45 -10 µA
IIL(4) External clock mode, VIN= VSS OSC1 -1.0
Output high-level VOH(1) IOH= -50µA Ports with pull-up VDD-1.2 V
voltage VDD= 4.0 to 5.5V resistor specifications
VOH(2) IOH= -10µA Ports with pull-up VDD-0.5
VDD= 3.0 to 5.5V resistor specifications
Output low-level VOL(1) IOL= 10mA Port 1.5
voltage VDD= 4.0 to 5.5V
VOL(2) IOL= 1 mA, with the IOL for all ports no more than 1 Port 0.5
mA. VDD= 3.0 to 5.5V
Hysteresis voltage VHIS RES , INT , SCK and SI 0.1VDD
characteristics

OSC1 with Schmitt

Schmitt

High-level VtH specifications *4 0.4VDD 0.8VDD

threshold voltage
Low-level VtL 0.2VDD 0.6VDD
threshold voltage
Current drain IDDOP(1) Operating, output n-channel transistors off, VDD 1.5 5 mA
Ports = VDD
Figure 2, 4 MHz, divide-by-three circuit
Ceramic oscillator IDDOP(2) Figure 2, 4 MHz, divide-by-four circuit VDD 1.5 4
IDDOP(3) Figure 2, 800 kHz VDD 1.5 4
External clock IDDOP(4) 670 to 1444 kHz, no divider circuit VDD 1.5 5
Standby mode 2000 to 4330 kHz, divide-by-three circuit
2600 to 4330 kHz, divide-by-four circuit
IDDst Output n-channel transistors off, VDD = 5.5V VDD 0.05 10 µA
Ports = VDD, VDD = 3V VDD 0.025 5
Continued on next page.

No.5190-13/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Oscillator fCFOSC *5 Figure 2, fo = 800 kHz OSC1, OSC2 768 800 832 kHz
characteristics Figure 2, fo = 1 MHz
Ceramic oscillator Figure 2, fo = 4 MHz, divide-by-three or OSC1, OSC2 960 1000 1040
Oscillator frequency divide-by-four circuit
Oscillator OSC1, OSC2 3840 4000 1460
stabilization time
tCFS Figure 3, fo = 800 kHz, 1 MHz, 4 MHz 5 ms
Divide-by-three or divide-by-four circuit
Pull-up resistors I/O Rpp Output n-channel transistors off Ports with pull-up resistor 8 14 30 kΩ
ports VIN = VSS, VDD = 5V specifications
RES Ru VIN = VSS, VDD = 5V RES 100 250 400
External reset tRST See
characteristics Figure 4.
Reset time
Pin capacitance Cp f = 1MHz 10 pF
With all pins other than the pin being measured at
VIN = VSS
Serial clock tCKCY (1) Figure 5 SCK 3.0 µs
Input clock cycle
tCKCY (2) Figure 5 SCK 64×Tcyc
time *6
Output clock cycle tCKL (1) Figure 5 1.0
SCK
time
Input clock low-level tCKL (2) Figure 5 SCK 32×Tcyc
pulse width tCKH (1) Figure 5 1.0
SCK
Output clock
low-level pulse width tCKH (2) Figure 5 SCK 32×Tcyc
Input clock high-level
pulse width
Output clock
high-level pulse
width
Continued on next page.

No.5190-14/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Applicable Ratings
Parameter Symbol Conditions unit
VDD[V] pins/notes min. typ. max.
Serial input Stipulated with respect to the rising edge of SI 0.4 µs
Data setup time tICK SCK .
Data hold time tCKI Figure 5 SI 0.4
Serial output tCKO Stipulated with respect to the falling edge of SO 0.6
Output delay time SCK .
For n-channel open-drain outputs only:
External resistance: 1 kΩ, external
capacitance: 50 pF
Figure 5
Pulse output Figure 6
Period tPCY TCYC = 4 × the system clock period PE0 64×TCYC

High-level pulse width tPH For n-channel open-drain outputs only: PE0 32×TCYC
External resistance: 1 kΩ, external ± 10%
Low-level pulse width
tPL capacitance: 50 pF PE0 32×TCYC
± 10%
Guaranteed constants *7 CW When PE1 has open-drain output 3 to 5.5 WDR 0.1±5% µF
specifications
RW When PE1 has open-drain output WDR 680±1% kΩ
specifications
RI When PE1 has open-drain output WDR 100±1% Ω
specifications
Watchdog timer

Clear time (discharge) tWCT See Figure 7. WDR 100 µs

Clear period (charge) tWCCY See Figure 7. WDR 29 ms
Guaranteed constants *7 CW When PE1 has open-drain output 4 to 5.5 WDR 0.047±5% µF
specifications
RW When PE1 has open-drain output WDR 680±1% kΩ
specifications
RI When PE1 has open-drain output WDR 100±1% Ω
specifications
Clear time (discharge) tWCT See Figure 7. WDR 40 µs
Clear period (charge) tWCCY See Figure 7. WDR 15 ms

[Notes]
1. When driven internally using the oscillator circuit shown in Figure 3 with guaranteed constants, values up to the
amplitude of the generated oscillation are allowed.
2. The average over a 100-ms period
3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until
the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering
(e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle.
4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics.
5. The values shown for fCFOSC are the frequencies for which oscillation is possible. The center frequency when a ceramic
oscillator is used may differ by about 1% from the nominal value listed by the manufacturer of the ceramic oscillator
element. See the specifications of the ceramic oscillator element for details.
6. TCYC = 4 × the system clock period
7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1
and adjacent pins and leakage associated with external capacitors.

No.5190-15/38
 LC651204N/F/L,LC651202N/F/L

OSC1 (OSC2)

OPEN
External clock

VDD

0.8VDD

0.2VDD

textL textH VSS

textF textR
text

Figure 1 External Clock Input Waveform

OSC1 OSC2

C1 C2
Ceramic oscillator
eiement

Figure 2 Ceramic Oscillator Circuit

No.5190-16/38
 LC651204N/F/L,LC651202N/F/L

VDD
Operating VDD lower limit

0V

OSC

Stable oscillation

Oscillator instability
period tCFS

Figure 3 Oscillator Stabilization Period

Table 1 : Guaranteed Ceramic Oscillator Constants

4MHz (Murata Mfg. Co., Ltd.) C1 33 pF±10 %
CSA4.00MG C2 33 pF±10 %
CST4.00MGW (built-in capacitor version) R 0Ω
4MHZ (Kyocera Corporation) C1 33 pF±10 % RES
KBR4.0MSA C2 33 pF±10 %
KBR4.0MKS (built-in capacitor version) R 0Ω CRES(=0.1µF)
1MHz (Murata Mfg. Co., Ltd.) C1 100 pF±10 %
CSB1000J C2 100 pF±10 %
R 2.2 kΩ
1MHz (Kyocera Corporation) C1 100 pF±10 % Figure 4 Reset Circuit
KBR1000F C2 100p F±10 %
R 0Ω
800kHz (Murata Mfg. Co., Ltd.) C1 100 pF±10 % Note: When the power supply rise time is zero, the
CSB800J C2 100 pF±10 % reset time with CRES = 0.1 µF will be
R 2.2 kΩ between 5 and 50 ms.
800kHz (Kyocera Corporation) C1 220 pF±10 % If the power supply rise time is comparatively
KBR800F C2 220 pF±10 % long, increase the value of CRES so that the
R 0Ω reset time is over 5 ms.

No.5190-17/38
 LC651204N/F/L,LC651202N/F/L

tCKCY
0.8VDD
tCKL tCKH
SCK 0.2VDD

tICK tCKI VDD

SI Input data Load circuit 1kΩ

tCKO

SO 50pF
Putput data

Figure 5 Serial I/O Timing

tPCY

tPH
With load conditions identical to those shown in Figure 5
0.7VDD
0.2VDD
tPL

Figure 6 Port PE0 Pulse Output Timing

Rw
RI
PE1/WDR

Cw

tWCCY tWCT
TWCCY : Charge time due to the external components Cw, Rw and Rl.
TWCT : Discharge time due to program processing

Figure 7 Watchdog Timer Waveform

No.5190-18/38
 LC651204N/F/L,LC651202N/F/L
LC651204F, LC651202F
Absolute Maximum Ratings at VSS=0V and Ta=25°C

Parameter Symbol Applicable pins/notes Conditions Ratings unit

Maximum supply voltage VDD max VDD -30 to +7.0 V
Output voltage VO OSC2 Voltages up to any
generated voltage
are allowed.
Input voltage VI (1) OSC1 *1 -0.3 to VDD +0.3
VI (2) TEST, RES -0.3 to VDD +0.3
I/O voltage VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 OD specification ports -0.3 to +15
VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PU specification ports -0.3 to VDD +0.3
VIO (3) PA0 to 3, PG0 to 3 -0.3 to VDD +0.3
Peak output current IOP I/O ports -2 to +20 mA
Average output current IOA Average value per pin over a 100-ms period I/O ports -2 to +20
Σ IOA (1) Total current for pins PC0 to 3, PD0 to 3, and PE0 PC0 to 3 -15 to +100
to 1*2 PD0 to 3
PE0 to 1
Σ IOA (2) Total current for pins PF0 to 3, PG0 to 3, and PA0 PF0 to 3 -15 to +100
to 3*2 PG0 to 3
PA0 to 3
Allowable power dissipation Pd max(1) Ta = -40 to +85°C (DIP package) 250 mW
Pd max(2) Ta = -40 to +85°C (MFP package) 150
Operation temperature Topr -40 to +85 °C
Storage temperature Tstg -55 to +125

Allowable Operating Range at Ta=-40°C to +85°C, VSS=0V, VDD=3.0 to 5.5V

(unless otherwise specified)
Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Operating VDD VDD 3.0 5.5 V
power-Supply voltage
Standby VST RAM and register values retained *3 VDD 1.8 5.5
power-Supply voltage
Input high-level VIH(1) Output n-channel transistors off OD specification ports C, D, E and F 0.7VDD 13.5
voltage VIH(2) Output n-channel transistors off PU specification ports C, D, E and F 0.7VDD VDD
VIH(3) Output n-channel transistors off Port A, G 0.7VDD VDD
VIH(4) Output n-channel transistors off The INT , SCK and SI pins with OD 0.8VDD 13.5
specifications
VIH(5) Output n-channel transistors off The INT , SCK and SI pins with PU 0.8VDD VDD
specifications
VIH(6) VDD = 1.8 to 5.5V RES 0.8VDD VDD
VIH(7) External clock specifications OSC1 0.8VDD VDD
Input low-level VIL(1) Output n-channel transistors off Port VSS 0.2VDD
voltage VIL(2) Output n-channel transistors off INT , SCK , SI VSS 0.2VDD
VIL(3) External clock specifications OSC1 VSS 0.2VDD
VIL(4) TEST VSS 0.2VDD
VIL(5) RES VSS 0.2VDD
Continued on next page.

No.5190-19/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.
Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Operating
frequency fop 670 4330 kHz
(cycle time) (Tcyc) (6) (0.97) (µs)
External clock
conditions text Figure 1 OSC1 670 4330 kHz
Frequency
textH, OSC1 69 ns
Pulse width
textL
Rise and fall times
textR, OSC1 50
textF
Guaranteed Figure 2 See Table 1.
oscillator
constants
Ceramic oscillator

Electrical Characteristics at Ta=-40°C to +85°C, VSS=0V, VDD=3.0 to 5.5V

(unless otherwise specified)
Applicable Ratings
Parameter Symbol Conditions unit
pins/notes min. typ. max.
Input high-level IIH(1) Output n-channel transistors off Ports C, D, E and F 5.0 µA
current (Includes the n-channel transistors off leakage current.) with open-drain
VIN= 13.5V specifications
IIH(2) Output n-channel transistors off Ports A and G with 1.0
(Includes the n-channel transistors off leakage current.) open-drain
VIN= VDD specifications
IIH(3) External clock mode, VIN= VDD OSC1 1.0
Input low-level IIL(1) Output n-channel transistors off Ports with open-drain -1.0
current VIN= VSS specifications
IIL(2) Output n-channel transistors off Ports with pull-up -1.3 -0.35 mA
VIN= VSS resistor specifications
IIL(3) VIN= VSS RES -45 -10 µA
IIL(4) External clock mode, VIN= VSS OSC1 -1.0
Output high-level VOH(1) IOH= -50µA Ports with pull-up VDD-1.2 V
voltage resistor specifications
VOH(2) IOH= -10µA Ports with pull-up VDD-0.5
resistor specifications
Output low-level VOL(1) IOL= 10mA Port 1.5
voltage
VOL(2) IOL= 1mA, with the IOL for all ports no more than 1mA. Port 0.5
Continued on next page.

No.5190-20/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.
Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Hysteresis VHIS 0.1VDD V
Schmitt characteristics

RES , INT , SCK and SI

voltage OSC1 with Schmitt
High-level VtH specifications *4 0.4VDD 0.8VDD
threshold
voltage
Low-level VtL 0.25VDD 0.6VDD
threshold
voltage
Current drain IDDOP(1) Figure 2, 4 MHz VDD 2 6 mA
Ceramic oscillator 670 to 1444 kHz
External clock IDDOP(2) *1 Operating, output n-channel transistors off, VDD 2 6
Ports = VDD
Standby mode IDDst Output n-channel transistors off, VDD = 5.5V VDD 0.05 10 µA
Ports = VDD VDD = 3V VDD 0.025 5
Oscillator fCFOSC Figure 2, fo = 4 MHz *5 OSC1, OSC2 3840 4000 1460 kHz
characteristics
Ceramic oscillator
Oscillator frequency
Oscillator stabilization tCFS Figure 3, fo = 4 MHz 5 ms
time
Pull-up resistors I/O Rpp Output n-channel transistors off Ports with pull-up 8 14 30 kΩ
ports VIN = VSS, VDD = 5V resistor specifications
RES Ru VIN = VSS, VDD = 5V RES 100 250 400
External reset tRST See
characteristics Figure 4.
Reset time
Pin capacitance Cp f = 1MHz 10 pF
With all pins other than the pin being measured at
VIN = VSS
Serial clock tCKCY (1) Figure 5 SCK 2.0 µs
Input clock cycle time
Output clock cycle
tCKCY (2) Figure 5 SCK 64×Tcyc
time *6
Input clock low-level
pulse width
tCKL (1) Figure 5 SCK 0.6
Output clock low-level
pulse width
Input clock high-level
tCKL (2) Figure 5 SCK 32×Tcyc
pulse width
Output clock
high-level pulse width
tCKH (1) Figure 5 SCK 0.6

tCKH (2) Figure 5 SCK 32×Tcyc

Continued on next page.

No.5190-21/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Applicable Ratings
Parameter Symbol Conditions unit
VDD[V] pins/notes min. typ. max.
Serial input Stipulated with respect to the rising edge of SI 0.2 µs
Data setup time tICK SCK .
Data hold time tCKI Figure 5 SI 0.2
Serial output tCKO Stipulated with respect to the rising edge of SO 0.4
Output delay time SCK .
For n-channel open-drain outputs only.
External resistance: 1 kΩ, external
capacitance: 50 pF
Figure 5
Pulse output Figure 6
Period tPCY TCYC = 4 × the system clock period PE0 64×TCYC

High-level pulse width tPH For n-channel open-drain outputs only. PE0 32×TCYC
External resistance: 1 kΩ, external ± 10%
Low-level pulse width
tPL capacitance: 50 pF PE0 32×TCYC
± 10%
Guaranteed constants CW When PE1 has open-drain output 3 to 5.5 WDR 0.01±5% µF
*7 specifications
RW When PE1 has open-drain output WDR 680±1% kΩ
specifications
RI When PE1 has open-drain output WDR 100±1% Ω
specifications
Watchdog timer

Clear time (discharge) tWCT See Figure 7. WDR 10 µs

Clear period (charge) tWCCY See Figure 7. WDR 3.0 ms
Guaranteed constants CW When PE1 has open-drain output 4.5 to 5.5 WDR 0.01±5% µF
*7 specifications
RW When PE1 has open-drain output WDR 680±1% kΩ
specifications
RI When PE1 has open-drain output WDR 100±1% Ω
specifications
Clear time (discharge) tWCT See Figure 7. WDR 10 µs
Clear period (charge) tWCCY See Figure 7. WDR 3.3 ms

[Notes]
1. When driven internally using the oscillator circuit shown in Figure 2 with guaranteed constants, values up to the
amplitude of the generated oscillation are allowed.
2. The average over a 100-ms period
3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until
the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering
(e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle.
4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics.
5. The values shown for fCFOSC are the frequencies for which oscillation is possible.
6. TCYC = 4 × the system clock period
7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1
and adjacent pins and leakage associated with external capacitors.

No.5190-22/38
 LC651204N/F/L,LC651202N/F/L

OSC1 (OSC2)

OPEN
External clock

VDD

0.8VDD

0.2VDD

textL textH VSS

textF textR
text

Figure 1 External Clock Input Waveform

OSC1 OSC2

C1 C2
Ceramic oscillator
eiement

Figure 2 Ceramic Oscillator Circuit

No.5190-23/38
 LC651204N/F/L,LC651202N/F/L

VDD
Operating VDD lower limit

0V

OSC

Stable oscillation

Oscillator instability
period tCFS

Figure 3 Oscillator Stabilization Period

Table 1 : Guaranteed Ceramic Oscillator Constants

4MHz (Murata Mfg. Co., Ltd.) C1 33 pF±10 %
CSA4.00MG C2 33 pF±10 %
CST4.00MGW (built-in capacitor version) R 0Ω
4MHZ (Kyocera Corporation) C1 33p F±10 % RES
KBR4.0MSA C2 33p F±10 %
KBR4.0MKS (built-in capacitor version) R 0Ω CRES(=0.1µF)

Figure 4 Reset Circuit

Note: When the power supply rise time is zero,

the reset time with CRES = 0.1µF will be
between 5 and 50 ms.
If the power supply rise time is
comparatively long, increase the value of
CRES so that the reset time is over 5 ms.

No.5190-24/38
 LC651204N/F/L,LC651202N/F/L

tCKCY
0.8VDD
tCKL tCKH
SCK 0.2VDD

tICK tCKI VDD

SI Input data Load circuit 1kΩ

tCKO

SO 50pF
Putput data

Figure 5 Serial I/O Timing

tPCY

tPH
With load conditions identical to those shown in Figure 5
0.7VDD 0.2VDD
tPL

Figure 6 Port PE0 Pulse Output Timing

Rw
RI
PE1/WDR

Cw

tWCCY tWCT
TWCCY : Charge time due to the external components Cw, Rw and Rl.
TWCT : Discharge time due to program processing

Figure 7 Watchdog Timer Waveform

No.5190-25/38
 LC651204N/F/L,LC651202N/F/L
LC651204L, LC651202L
Absolute Maximum Ratings at VSS=0V and Ta=25°C

Parameter Symbol Applicable pins/notes Conditions Ratings unit

Maximum supply voltage VDD max VDD -30 to +7.0 V
Output voltage VO OSC2 Voltages up to any
generated voltage are
allowed.
Input voltage VI (1) OSC1 *1 -0.3 to VDD +0.3
VI (2) TEST, RES -0.3 to VDD +0.3
I/O voltage VIO (1) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 OD specification ports -0.3 to +15
VIO (2) PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PU specification ports -0.3 to VDD +0.3
VIO (3) PA0 to 3, PG0 to 3 -0.3 to VDD +0.3
Peak output current IOP I/O ports -2 to +20 mA
Average output current IOA Average value per pin over a 100-ms period I/O ports -2 to +20
Σ IOA (1) Total current for pins PC0 to 3, PD0 to 3, and PE0 PC0 to 3 -15 to +100
to 1*2 PD0 to 3
PE0 to 1
Σ IOA (2) Total current for pins PF0 to 3, PG0 to 3, and PA0 PF0 to 3 -15 to +100
to 3*2 PG0 to 3
PA0 to 3
Allowable power dissipation Pd max(1) Ta = -40 to +85°C (DIP package) 250 mW
Pd max(2) Ta = -40 to +85°C (MFP package) 150
Operation temperature Topr -40 to +85 °C
Storage temperature Tstg -55 to +125

Allowable Operating Range at Ta=-40°C to +85°C, VSS=0V, VDD=2.5 to 5.5V

(unless otherwise specified)
Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Operating VDD VDD 2.5 5.5 V
power-Supply
voltage
Standby VST RAM and register values retained *3 VDD 1.8 5.5
power-Supply
voltage
Input high-level VIH(1) Output n-channel transistors off OD specification ports C, D, E and F 0.7VDD 13.5
voltage VIH(2) Output n-channel transistors off PU specification ports C, D, E and F 0.7VDD VDD
VIH(3) Output n-channel transistors off Port A, G 0.7VDD VDD
VIH(4) Output n-channel transistors off The INT , SCK and SI pins with OD 0.8VDD 13.5
specifications
VIH(5) Output n-channel transistors off The INT , SCK and SI pins with PU 0.8VDD VDD
specifications
VIH(6) VDD = 1.8 to 5.5V RES 0.8VDD VDD
VIH(7) External clock specifications OSC1 0.8VDD VDD
Input low-level VIL(1) Output n-channel transistors off Port VSS 0.2VDD
voltage VIL(2) Output n-channel transistors off INT , SCK ,SI VSS 0.15VDD

VIL(3) External clock specifications OSC1 VSS 0.15VDD

VIL(4) TEST VSS 0.2VDD
VIL(5) VSS 0.15VDD
RES
Continued on next page.

No.5190-26/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Operating Frequencies up to 4.16MHz are supported
frequency fop if the divide-by-four divider circuit option 670 1040 kHz
(cycle time) (Tcyc) is used. (6) (3.84) (µs)
External clock Figure 1. The divide-by-three or
conditions text divide-by-four divider circuit option OSC1 670 4160 kHz
Frequency must be used if the clock frequency
Pulse width textH, exceeds 1.040MHz. OSC1 150 ns
Rise and fall times textL
textR, OSC1 100
textF
Guaranteed Figure 2 See Table 1.
oscillator
constants
Ceramic oscillator

Electrical Characteristics at Ta=-40°C to +85°C, VSS=0V, VDD=2.5 to 5.5V

(unless otherwise specified)
Applicable Ratings
Parameter Symbol Conditions unit
pins/notes min. typ. max.
Input high-level IIH(1) Output n-channel transistors off Ports C, D, E and F 5.0 µA
current (Includes the n-channel transistors off leakage current.) with open-drain
VIN= 13.5V specifications
IIH(2) Output n-channel transistors off Ports A and G with 1.0
(Includes the n-channel transistors off leakage current.) open-drain
VIN= VDD specifications
IIH(3) External clock mode, VIN= VDD OSC1 1.0
Input low-level IIL(1) Output n-channel transistors off Ports with open-drain -1.0
current VIN= VSS specifications
IIL(2) Output n-channel transistors off Ports with pull-up -1.3 -0.35 mA
VIN= VSS resistor specifications
IIL(3) VIN= VSS RES -45 -10 µA
IIL(4) External clock mode, VIN= VSS OSC1 -1.0
Output high-level VOH(1) IOH= -10µA Ports with pull-up VDD-0.5 V
voltage resistor specifications
Output low-level VOL(1) IOL= 3mA Port 1.5
voltage
VOL(2) IOL= 1 mA, with the IOL for all ports no more than Port 0.4
1 mA.
Continued on next page.

No.5190-27/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Ratings
Parameter Symbol Conditions Applicable pins/notes unit
min. typ. max.
Hysteresis voltage VHIS RES , INT , SCK and SI 0.1VDD V
characteristics

OSC1 with schmitt

Schmitt

High-level VtH specifications *4 0.4VDD 0.8VDD

threshold voltage
Low-level VtL 0.2VDD 0.6VDD
threshold voltage
Current drain IDDOP(1) Operating, output n-channel transistors off, VDD 1.5 4 mA
Ceramic oscillator Ports = VDD
Figure 2, 4 MHz, divide-by-three circuit
IDDOP(2) Figure 2, 4 MHz, divide-by-three circuit VDD 0.5 1
VDD = 2.5V
IDDOP(3) Figure 2, 800 kHz VDD 1.5 4.0
External clock IDDOP(4) 670 to 1024 kHz, no divider circuit VDD 1.5 4
2000 to 3120 kHz, divide-by-three circuit
2600 to 4160 kHz, divide-by-four circuit
Standby mode IDDst Output n-channel transistors off, Ports VDD = 5.5V VDD 0.05 10 µA
= VDD VDD = 2.5V VDD 0.020 4
Oscillator characteristics fCFOSC Figure 2, fo = 800 kHz OSC1, OSC2 768 800 832 kHz
Ceramic oscillator *5 Figure 2, fo = 1 MHz
Oscillator frequency Figure 2, fo = 4 MHz, divide-by-four circuit OSC1, OSC2 960 1000 1040
Oscillator stabilization
time OSC1, OSC2 3840 4000 4160

tCFS Figure 3, fo = 800 kHz, 1 MHz, 4 MHz, 5 ms

divide-by-four circuit
Pull-up resistors I/O Rpp Output n-channel transistors off Ports with pull-up resistor 8 14 30 kΩ
ports VIN = VSS, VDD = 5V specifications
RES Ru VIN = VSS, VDD = 5V RES 100 250 400
External reset tRST See
characteristics Figure 4.
Reset time
Pin capacitance Cp f = 1MHz 10 pF
With all pins other than the pin being measured at
VIN = VSS
Serial clock tCKCY (1) Figure 5 SCK 6.0 µs
Input clock cycle time
Output clock cycle time
tCKCY (2) Figure 5 SCK 64×Tcyc
Input clock low-level *6
pulse width
Output clock low-level
tCKL (1) Figure 5 SCK 2.0
pulse width
Input clock high-level
pulse width
tCKL (2) Figure 5 SCK 32×Tcyc
Output clock high-level
pulse width

tCKH (1) Figure 5 SCK 2.0

tCKH (2) Figure 5 SCK 32×Tcyc

Continued on next page.

No.5190-28/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.

Applicable Ratings
Parameter Symbol Conditions unit
VDD[V] pins/notes min. typ. max.
Serial input Stipulated with respect to the rising edge SI 0.5 µs
Data setup time tICK of SCK .
Data hold time tCKI Figure 5 SI 0.5
Serial output tCKO Stipulated with respect to the rising edge SO 1.0
Output delay time of SCK .
For n-channel open-drain outputs only:
External resistance: 1 kΩ, external
capacitance: 50 pF
Figure 5
Pulse output period Figure 6
tPCY TCYC = 4 × the system clock period PE0 64×TCYC

High-level pulse width tPH For n-channel open-drain outputs only: PE0 32×TCYC
External resistance: 1 kΩ, external ± 10%

Low-level pulse width tPL capacitance: 50 pF PE0 32×TCYC

± 10%
Guaranteed constants *7 CW When PE1 has open-drain output 2.5 to 5.5 WDR 0.1±5% µF
specifications
RW When PE1 has open-drain output WDR 680±1% kΩ
specifications
RI When PE1 has open-drain output WDR 100±1% Ω
specifications
Watchdog timer

Clear time (discharge) tWCT See Figure 7. WDR 100 µs

Clear period (charge) tWCCY See Figure 7. WDR 26 ms
Guaranteed constants *7 CW When PE1 has open-drain output 2.5 to 5.5 WDR 0.047±5% µF
specifications
RW When PE1 has open-drain output WDR 680±1% kΩ
specifications
RI When PE1 has open-drain output WDR 100±1% Ω
specifications
Clear time (discharge) tWCT See Figure 7. WDR 40 µs
Clear period (charge) tWCCY See Figure 7. WDR 12 ms

[Notes]
1. When driven internally using the oscillator circuit shown in Figure 2 with guaranteed constants, values up to the
amplitude of the generated oscillation are allowed.
2. The average over a 100-ms period
3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until
the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering
(e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle.
4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics.
5. The values shown for fCFOSC are the frequencies for which oscillation is possible.
6. TCYC = 4 × the system clock period
7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1
and adjacent pins and leakage associated with external capacitors.

No.5190-29/38
 LC651204N/F/L,LC651202N/F/L

OSC1 (OSC2)

OPEN
External clock

VDD

0.8VDD

0.15VDD

textL textH VSS

textF textR
text

Figure 1 External Clock Input Waveform

OSC1 OSC2

C1 Ceramic oscillator C2
eiement

Figure 2 Ceramic Oscillator Circuit

No.5190-30/38
 LC651204N/F/L,LC651202N/F/L

VDD
Operating VDD lower limit

0V

OSC

Stable oscillation

Oscillator instability
period tCFS

Figure 3 Oscillator Stabilization Period

Table 1 : Guaranteed Ceramic Oscillator Constants

4MHz Murata Mfg. Co., Ltd.) C1 33 pF±10 %
CSA4.00MGU C2 33 pF±10 %
CST4.00MGWU (built-in capacitor version) R 0Ω
1MHz (Murata Mfg. Co., Ltd.) C1 100 pF±10 % RES
CSB1000J C2 100 pF±10 %
R 2.2 kΩ CRES(=0.1µF)
1MHz (Kyocera Corporation) C1 100 pF±10 %
KBR1000F C2 100 pF±10 %
R 0Ω
800kHz (Murata Mfg. Co., Ltd.) C1 100 pF±10 % Figure 4 Reset Circuit
CSB800J C2 100 pF±10 %
R 2.2kΩ
800kHz (Kyocera Corporation) C1 220 pF±10 % Note: When the power supply rise time is zero,
KBR800F C2 220 pF±10 % the reset time with CRES = 0.1µF will be
R 0Ω between 5 and 50 ms.
If the power supply rise time is
comparatively long, increase the value of
CRES so that the reset time is over 5 ms.

No.5190-31/38
 LC651204N/F/L,LC651202N/F/L

tCKCY
0.8VDD
tCKL tCKH
SCK 0.15VDD

tICK tCKI VDD

SI Input data Load circuit 1kΩ

tCKO

SO 50pF
Putput data

Figure 5 Serial I/O Timing

tPCY

tPH
With load conditions identical to those shown in Figure 5
0.7VDD
0.2VDD
tPL

Figure 6 Port PE0 Pulse Output Timing

Rw
RI
PE1/WDR

Cw

tWCCY tWCT

TWCCY : Charge time due to the external components Cw, Rw and Rl.
TWCT : Discharge time due to program processing

Figure 7 Watchdog Timer Waveform

No.5190-32/38
 LC651204N/F/L,LC651202N/F/L
LC651204/1202 Instruction Set (by function)
Abbreviations

AC : Accumulator M : Memory ZF : Zero flag

ACt : Accumulator bit t M(DP) : Memory addressed by DP ()[] : Indicates the contents of
CF : Carry flag P(DPL) : I/O port specified by DPL the item enclosed.
CTL : Control register PC : Program counter ← : Transfer and direction
DP : Data pointer STACK : Stack pointer + : Addition
E : E register TM : Timer - : Subtraction
EXTF : External interrupt request flag TMF : Timer (internal) interrupt request flag ∧ : Logical AND
Fn : Flag bit n At, Ha, La : Working registers ∨ : Logical OR
∀ : Logical exclusive OR
Instruction group

Number of bytes

Number of bytes
Instruction code Modified
status
Mnemonic Operation Description Notes
flags
D7 D6 D5 D4 D3 D2 D1 D0

CLA Clear AC 1 1 0 0 0 0 0 0
1 1 AC ← 0 Clears AC. ZF *1
Accumulator manipulation instruction

CIC Clear CF 1 1 1 0 0 0 0 1
1 1 CF ← 0 Clears CF. CF
STC Set CF 1 1 1 1 0 0 0 1
1 1 CF ← 1 Sets CF. CF
1 1 1 0 1 0 1 1 Sets AC to the one’s
CMA Complement AC 1 1 AC ← ( AC ) ZF
INC Increment AC 0 0 0 0 1 1 1 0
1 1 AC ← (AC) + 1 Increments AC. ZF CF
DEC Decrement AC 0 0 0 0 1 1 1 1
1 1 AC ← (AC) - 1 Decrements AC. ZF CF
RAL Rotate AC left 0 0 0 0 0 0 0 1
1 1 AC ← (CF), CAn+1← Shifts AC together with CF ZF CF
through CF (ACn), CF ← (AC3) left.
TAE Transfer AC to E 0 0 0 0 0 0 1 1
1 1 E ← (AC) Moves the contents of AC
to E.
XAE Exchange AC with E 0 0 0 0 1 1 0 1
1 1 (AC) ↔ (E) Exchanges the contents of
AC and E.
Memory manipulation

INM Increment M 0 0 1 0 1 1 1 0
1 1 M(DP) ← [M(DP)] + 1 Increments M(DP). ZF CF
DEm Decrement M 0 0 1 0 1 1 1 1
1 1 M(DP) ← [M(DP)] - 1 Decrements M(DP). ZF CF
instructions

SmB bit Set M data bit 0 0 0 0 1 0 B1 B0

1 1 M(DP, B1 B0) ← 1 Sets the bit in M(DP)
specified by B1 B0 to 1.
RMB bit Reset M data bit 0 0 1 0 1 0 B1 B0
1 1 M(DP, B1 B0) ← 0 Clears the bit in M(DP)
specified by B1 B0 to 0.
AD Add M to AC 0 1 1 0 0 0 0 0
1 1 AC ← (AC) + [M(DP)] Adds the contents of AC ZF CF
and M(DP) as two’s
complement quantities and
stores the result in AC.
ADC Add M to AC with CF 0 0 1 0 0 0 0 0
1 1 AC ← (AC) + [M(DP)] + Adds the contents of AC, ZF CF
(CF) CF and M(DP) as two’s
complement
Arithmetic and comparison instructions

quantities and stores the

result in AC.
DAA Decimal adjust AC in 1 1 1 0 0 1 1 0
1 1 AC ← (AC) + 3 Adds 6 to AC. ZF
addition
DAS Decimal adjust AC in 1 1 1 0 1 0 1 0
1 1 AC ← (AC) + 10 Adds 10 to AC. ZF
subtraction
EXL Exclusive or M to AC 1 1 1 1 0 1 0 1
1 1 AC ← (AC) ∀ [M(DP)] Takes the logical exclusive ZF
OR of AC and M(DP) and
stores the result in AC.
AND And M to AC 1 1 1 0 0 1 1 1
1 1 AC ← (AC) ∧ [M(DP)] Takes the logical AND ZF
of AC and M(DP) and
stores the result in AC.
OR Or M to AC 1 1 1 0 0 1 0 1
1 1 AC ← (AC) ∨ [M(DP)] Takes the logical OR of ZF
AC and M(DP) and stores
the result in AC.
[ M(DP) ] + (AC) + 1 Compares the contents of ZF CF
AC and M(DP) and sets or
clears CF and ZF
CM Compare AC with M 1 1 1 1 1 0 1 1 1 1 accordingly.
Magnitude relationship CF ZF
[M(DP)] > (AC) 0 0
[M(DP)] = (AC) 1 1
[M(DP)] < (AC) 1 0

Continued on next page.

No.5190-33/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.
Instruction group

Number of bytes

Number of bytes
Instruction code Modified
status
Mnemonic Operation Description Notes
flags
D7 D6 D5 D4 D3 D2 D1 D0

Compares the contents of ZF CF

Arithmetic and comparison

AC and the immediate data

CI data Compare AC with 0 0 1 0 1 1 0 0
2 2 I3 I2 I1 I0 and sets or clears
0 1 0 0 I3 I2 I1 I3 I2 I1 I0 + (AC) + 1 CF and ZF accordingly.
instructions

immediate data I0 Magnitude relationship CF ZF

I3 I2 I1 I0 > (AC) 0 0
I3 I2 I1 I0 = (AC) 1 1
I3 I2 I1 I0 < (AC) 1 0
CLI data Compare DPL with 0 0 1 0 1 1 0 0
2 2 (DPL) ∨ I3 I2 I1 I0 Compares the contents of ZF
0 1 0 1 I3 I2 I1
immediate data I0 DPL and the immediate
data.
LI data Load AC with 1 1 0 0 I3 I2 I1
1 1 AC ← I3 I2 I1 I0 Loads AC with the ZF *1
I0
immediate data immediate data I3 I2 I1 I0.
S Store AC to M 0 0 0 0 0 0 1 0
1 1 M(DP) ← (AC) Stores the contents of AC at
M(DP).
L Load AC from M 0 0 1 0 0 0 0 1
1 1 AC ← [M(DP)] Loads the contents of ZF
M(DP) into AC.
XM data Exchange AC with M 1 0 1 0 0 M2 M1 M0
1 2 (AC) ↔ [M(DP)] Exchanges the contents of ZF ZF is set to
indicate the result
then modify DPH with DPH ← (DPH) ∀ 0 M2 M1 AC and M(DP). Then, of the (DPH) ∀ 0
immediate data M0 replaces the contents of M2 M1 M0
Load and store instructions

DPH with (DPH) ∀ 0 M2 operation.

M1 M0.
X Exchange AC with M 1 0 1 0 0 0 0 0
1 2 (AC) ↔ [M(DP)] Exchanges the contents of ZF ZF is set
according to the
AC and M(DP). contents of DPH at
the point the
instruction was
executed.
XI Exchange AC with M 1 1 1 1 1 1 1 0
1 2 (AC) ↔ [M(DP)] Exchanges the contents of ZF ZF is set to
indicate the
then increment DPL DPL ← (DPL) + 1 AC and M(DP). Then, result of the DPL
increments the contents of + 1 operation.
DPL
XD Exchange AC with M 1 1 1 1 1 1 1 1
1 2 (AC) ↔ [M(DP)] Exchanges the contents of ZF ZF is set to
indicate the
then increment DPL DPL ← (DPL) - 1 AC and M(DP). Then, result of the DPL
Decrements the contents + 1 operation.
of DPL.
RTBI Read table data from 0 1 1 0 0 0 1 1
1 2 AC, E ↔ ROM Loads into AC and E the
program ROM (PCh, E, AC) ROM data stored at the
location given by the
lower 8 bits of the PC, E
and AC.
LDZ data Load DPH with Zero and 1 0 0 0 I3 I2 I1
1 1 DPH ← 0 Loads 0 into DPH and the
Data pointer manipulation instructions

I0
DPL with immediate data DPL ← I3 I2 I1 I0 immediate data I3 I2 I1 I0
respectively into DPL.
LHI data Load DPH with 0 1 0 0 I3 I2 I1
1 1 DPH ← I3 I2 I1 I0 Loads the immediate data I3
I0
immediate data I2 I1 I0 into DPH.

IND Increment DPL 1 1 1 0 1 1 1 0

1 1 DPL ← (DPL) + 1 Increments the ZF
contents of DPL.
DED Decrement DPL 1 1 1 0 1 1 1 1
1 1 DPL ← (DPL) - 1 Decrements the ZF
contents of DPL.
TAL Transfer AC to DPL 1 1 1 1 0 1 1 1
1 1 DPL ← (AC) Moves the contents of AC
to DPL.
TLA Transfer DPL to AC 1 1 1 0 1 0 0 1
1 1 AC ← (DPL) Moves the contents of ZF
DPL to AC.
XAH Exchange AC with DPH 0 0 1 0 0 0 1 1
1 1 (AC) ↔ (DPH) Exchanges the contents of
AC and DPH.
Continued on next page.

No.5190-34/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.
Instruction group

Number of bytes

Number of bytes
Instruction code Modified
status
Mnemonic Operation Description Notes
flags
D7 D6 D5 D4 D3 D2 D1 D0
Memory manipulation Working register manipulation instructions

t1 t0 Exchanges the contents of

XAt Exchange AC with 1 1 1 0 0 1 0 0
XA0 working register At 1 1 1 0 0 1 0 0 1 1 (AC) ↔ (A0) AC and the working register
XA1 1 1 1 0 0 1 0 0
1 1 (AC) ↔ (A1) A0, A1, A2 or A3 specified by
1 1 1 0 0 1 0 0
(AC) ↔ (A2) t1 t0.
XA2 1 1
(AC) ↔ (A3)
XA3 1 1
a Exchanges the contents of
XHa Exchange DPH with 1 1 1 1 1 0 0 0
XH0 working register Ha 1 1 1 1 1 1 0 0 1 1 (DPH) ↔ (H0) DPH and the working
XH1 1 1 (DPH) ↔ (H1) register H0 or H1 specified
by a.
a Exchanges the contents of
XLa Exchange DPH with 1 1 1 1 1 0 0 0
XL0 working register Ha 1 1 1 1 1 1 0 0 1 1 (DPL) ↔ (L0) DPL and the working
XL1 1 1 (DPL) ↔ (L1) register L0 or L1 specified
by a.
SFB flag Set flag bit 0 1 0 1 B3 B2 B1 B0
1 1 Fn ← 1 Sets the flag specified by B3,
B2, B1, B0 to 1.
instructions

RFB flag Reset flag bit 0 0 0 1 B3 B2 B1 B0

1 1 Fn ← 0 Clears the flag specified by ZF The flags are divided
into four groups, F0 to
B3, B2, B1, B0 to 0. F3, F4 to F7, F8 to F12
to F15. ZF is set or
cleared according to
the 4 bits included in
the specified flags.
JMP addr Jumping in the current 0 1 1 0 1 P10 P9 P8
2 2 PC ← P10 P9 P8 P7 P6 Jumps to the location
P7 P6 P5 P4 P3 P2 P1 P0
P5 P4 P3 P2 P1 P0 specified by the immediate
bank
data P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
Jump and subroutine instructions

P0 .

JPEA Jumping current page 1 1 1 1 1 0 1 0

1 1 PC0 to 7 ← (E, AC) Jumps to the location given
modified by E and AC by replacing the lower 8 bits
of the PC with E and AC.
CZP addr Call subroutine in the zero 1 0 1 1 P3 P2 P1 P0
1 1 STACK ← (PC) + 1 Calls a subroutine on page 0.
page PC10 to 6, PC1 to 0 ← 0
PC5 to 2 ← P3 P2 P1 P0
CAL addr Call subroutine 1 0 1 0 1 P10 P9 P8
2 2 STACK ← (PC) + 2 Calls a subroutine.
RT Return from subroutine 0 1 1 0 0 0 1 0
1 1 PC ← (STACK) Returns from a subroutine.
RTI Return from interrupt 0 0 1 0 0 0 1 0
1 1 PC ← (STACK) Returns from an interrupt ZF CF
routine CF, ZF ← CSF, ZSF handling routine.
1 1 1 1 1 1 0 1 Specifies a pseudo I/O port Only valid for the
BANK Change bank 1 1 immediately
and changes the bank. following JMP, I/O,
or branch
instruction.

Continued on next page.

No.5190-35/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.
Instruction group

Number of bytes

Number of bytes
Instruction code Modified
status
Mnemonic Operation Description Notes
flags
D7 D6 D5 D4 D3 D2 D1 D0

BAt addr Change bank 0 1 1 1 0 0 t1 t0

2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
BA0 to BA3,
P7 P6 P5 P4 P3 P2 P1 P0 P3 P2 P1 P0 the same page specified by reflecting the value
if ACt = 1 P7 to P0 if the bit in AC of t.
specified by the immediate
data t1 t0 is 1.
BNAt addr Branch on no AC bit 0 0 1 1 0 0 t1 t0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BNA0 to BNA3,
P3 P2 P1 P0 the same page specified by reflecting the value
if ACt = 0 P7 to P0 if the bit in AC of t.
specified by the immediate
data t1 t0 is 0.
BMt addr Branch on M bit 0 1 1 1 0 1 t1 t0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BM0 to BM3,
P3 P2 P1 P0 the same page specified by reflecting the value
if [M(DP, t1 t0)] = 1 P7 to P0 if the bit in M(DP) of t.
specified by the immediate
data t1 t0 is 1.
BNMt addr Branch on no M bit 0 0 1 1 0 1 t1 t0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BNM0 to BNM3,
P3 P2 P1 P0 the same page specified by reflecting the value of
if [M(DP, t1 t0)] = 0 P7 to P0 if the bit in M(DP) t.
specified by the immediate
data t1 t0 is 0.
Branch instructions

BPt addr Branch on Port bit 0 1 1 1 1 0 t1 t0

2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BP0 to BP3
P3 P2 P1 P0 the same page specified by , reflecting the value
if [P(DPL, t1 t0)] = 1 P7 to P0 if the bit in P(DPL) of t.
specified by the immediate
data t1 t0 is 1.
BNPt addr Branch on no Port bit 0 0 1 1 1 0 t1 t0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BNP0 to BNP3
P3 P2 P1 P0 the same page specified by , reflecting the value
if [P(DPL, t1 t0)] = 0 P7 to P0 if the bit in P(DPL) of t.
specified by the immediate
data t1 t0 is 0.
BTM addr Branch on timer 0 1 1 1 1 0 0 0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on TMF
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
if TMF = 0 P7 to P0 if TMF is 1. Also
then TMF ← 0 clears TMF.
BNTM Branch on no timer 0 0 1 1 1 1 0 0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on TMF
P7 P6 P5 P4 the same page specified by
addr P7 P6 P5 P4 P3 P2 P1 P0
if TMF = 0 P7 to P0 if TMF is 0. Also
then TMF ← 0 clears TMF.
BI addr Branch on interrupt 0 1 1 1 1 1 0 1
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on EXTF
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
if EXTF = 1 P7 to P0 if EXTF is 1. Also
then EXTF ← 0 clears EXTF.
BNI addr Branch on no interrupt 0 0 1 1 1 1 0 1
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on EXTF
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
if EXTF = 0 P7 to P0 if EXTF is 0. Also
then EXTF ← 0 clears EXTF.
Continued on next page.

No.5190-36/38
 LC651204N/F/L,LC651202N/F/L
Continued from preceding page.
Instruction group

Number of bytes

Number of bytes
Instruction code Modified
status
Mnemonic Operation Description Notes
flags
D7 D6 D5 D4 D3 D2 D1 D0

BC addr Branch on CF 0 1 1 1 1 1 1 1
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
if EXTF = 0 P7 to P0 if CF is 1.
BNC addr Branch on no CF 0 0 1 1 1 1 1 1
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
if CF = 0 P7 to P0 if CF is 0.
BZ addr Branch on ZF 0 1 1 1 1 1 1 0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
Branch instructions

if ZF = 1 P7 to P0 if ZF is 1.
BNZ addr Branch on no ZF 0 0 1 1 1 1 1 0
2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 the same page specified by
if ZF = 0 P7 to P0 if ZF is 0.
BFn addr Branch on flag bit 1 1 0 1 n3 n2 n1 n0 2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BF0 to BF15,
P7 P6 P5 P4 the same page specified by reflecting the value
if Fn = 1 P7 to P0 if the bit in the 16 of n.
flags specified by n3 n2 n1 n0
is 1.
BNFn addr Branch on no flag bit 1 0 0 1 n3 n2 n1 n0 2 2 PC7 to 0 ← P7 P6 P5 P4 Branches to the location on The mnemonics are
P7 P6 P5 P4 P3 P2 P1 P0 BFN0 to BFN15,
P7 P6 P5 P4 the same page specified by reflecting the value
if Fn = 0 P7 to P0 if the bit in the 16 of n.
flags specified by n3 n2 n1 n0
is 0.
IP Input port to AC 0 0 0 0 1 1 0 0
1 1 AC ← [P(DPL)] Inputs the contents of port ZF
P(DPL) to AC.
OP Output port to AC 0 1 1 0 0 0 0 1
1 1 P(DPL, B1 B0 ) ← (AC) Outputs the contents of
I/O instructions

AC to port P(DPL).
SPB bit Set port bit 0 0 0 0 0 1 B1 B0
1 2 P(DPL, B1 B0 ) ← 1 Sets to 1 the bit in port Executing this
instruction destroys
P(DPL) specified by the the
immediate data B1 B0. contents of the E
register.
RPB bit Reset port bit 0 0 1 0 0 1 B1 B0
1 2 P(DPL, B1 B0 ) ← 1 Clears to 0 the bit in port ZF Executing this
instruction destroys
P(DPL) specified by the the
immediate data B1 B0. contents of the E
register.
SCTL bit Set control register bit 0 0 1 0 1 1 0 0
2 2 CTL ← (CTL) ∨ Sets the bit (or bits) in the
(S) B3 B2 B1 B0 control register specified by
B3 B2 B1 B0.

RCTL bit Reset control register bit 0 0 1 0 1 1 0 0

2 2 CTL ← (CTL) ∨ Clears the bit (or bits) in the ZF
1 0 0 1 B3 B2 B1 B0
Other instructions

(S) B3 B2 B1 B0 control register specified by

B3 B2 B1 B0.

WTTM Write timer 1 1 1 1 1 0 1 1

1 1 TM ← (E), (AC) Loads the contents of E and TMF
TMF ← 0 AC into the timer. Also
clears TMF.
1 1 1 1 0 1 1 0 Halt Stops all operations. This instruction is
HALT Halt 1 1 disabled only when
all bits in port PA are
0.
0 0 0 0 0 0 0 0 No operation Consumes one machine
NOP No operation 1 1
cycle while performing no
operation.

No.5190-37/38
 LC651204N/F/L,LC651202N/F/L

memo :

PS No.5190-38/38