Department of Electrical Engineering

Faculty Member: Dr Abdullah Mughees Dated: 05 September, 2024

Semester: 3rd Section: BEE-15-D

Group No

EE-221: Digital Logic Design

Lab No # 3: Design of Simple Practical Circuits

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

Name Reg. No Viva / Lab Analysis of Modern Tool Ethics and Individual Total
Performance data in Lab Usage Safety and Team marks
Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

Shaheer Asghar 456020

Huzyepha Javaid 467746

Bahram Jamal khan 476406

Saad Rabbani 463533

EE-221: Digital Logic Design Page 1

 Lab No 2 : Digital Design of Simple Practical Circuits

Prelab:

1. Design the practical circuits given in Task 1 and Task 2 by giving the truth table of the problems and
then giving the circuit (logic diagram) for the designs

2. Provide only Truth Table of Task 3.

0V
Lab Tasks:

Task No 1 (4)

As part of an aircraft’s functional monitoring system, a circuit is required to indicate

Green LED the status of the
landing gear priorRight
to landing.
Wing gear Asensor
green LED (Light Emitting Diode) display turns on if all three gears are
properly extendedNosewhen thesensor
gear “gear down” switch has been activated in preparation for landing. A red LED
display turns on ifLeft
anyWing
of the gear
gear fails to extent properly prior to landing. When landing gear is extended, its
sensor
sensor produces a HIGH voltage. When a landing gear is retracted its sensor produces a LOW voltage. Write
the truth table for the aircraft landing system. Implement with basic logic gates. Red LED

5V

Logic Circuit

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 Truth Table

Input 1 Input 2 Input 3 Green LED Red LED

0 0 0 0 1

0 0 1 0 1

0 1 0 0 1

0 1 1 0 1

1 0 0 0 1

1 0 1 0 1

1 1 0 0 1

1 1 1 1 0

Verilog Code

module task1(out1, out2, in1, in2, in3);

input in1, in2, in3;

output out1, out2;

assign out1 = in1 & in2 & in3;

assign out2 = ~(in1 & in2 & in3);

endmodule

module testAND3;

reg a, b, c;

wire out11, out22;

task1 testAnd3(out11, out22, a, b, c);

initial

begin

#100 a = 1'b0; b = 1'b0; c = 1'b0;

#100 a = 1'b0; b = 1'b0; c = 1'b1;

#100 a = 1'b0; b = 1'b1; c = 1'b0;

#100 a = 1'b0; b = 1'b1; c = 1'b1;

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 #100 a = 1'b1; b = 1'b0; c = 1'b0;

#100 a = 1'b1; b = 1'b0; c = 1'b1;

#100 a = 1'b1; b = 1'b1; c = 1'b0;

#100 a = 1'b1; b = 1'b1; c = 1'b1;

end

endmodule

Simulation:

Proteus SS

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 Hardware Implementation

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EE-221: Digital Logic Design Page 6
Task No 2 (4)

Design a three-way switch for lighting a bulb. Suppose the Switch A is installed at the entrance of the room,
switch B is installed to the bedside table, Switch C is installed outside the room. Now three way switching
can facilitate the switching ON/OFF from any location. The mechanism is such that if a single switch is on
the bulb should be ON. Now if the second switch is turned on the bulb if switched on earlier is switched off.
If two switches are already on and third switch is turned on then it should switch on the bulb. Implement
with basic gates.

Truth Table

Input 1 Input 2 Input 3 BULB

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Proteus SS

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 Verilog Code

module

task1(out1,

in1, in2, in3);

input in1, in2,

in3;

output out1;

assign out1 = in1 ^ in2 ^ in3;

EE-221: Digital Logic Design Page 8

 endmodule

mod

ule

test

XO

R3;

reg

a, b,

c;

wire out11;

task1 testXOR3(out11, a, b, c);

initial

begin

#100 a = 1'b0; b = 1'b0; c = 1'b0;

#100 a = 1'b0; b = 1'b0; c = 1'b1;

#100 a = 1'b0; b = 1'b1; c = 1'b0;

#100 a = 1'b0; b = 1'b1; c = 1'b1;

#100 a = 1'b1; b = 1'b0; c = 1'b0;

#100 a = 1'b1; b = 1'b0; c = 1'b1;

#100 a = 1'b1; b = 1'b1; c = 1'b0;

#100 a = 1'b1; b = 1'b1; c = 1'b1;

end

endmodule

Hardware Implementation

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Simulation:

Task No 3 (2)
The system is a speed warning device. It receives, on two lines, an indication of the speed limit on the
highway. There are three possible values 45, 55, or 65 MPH. It receives from the automobile, on two other
lines, an indication of speed of the vehicle. There are four possible values under 45, between 46 and 55,
between 56 and 65, and over 65 MPH. It produces two outputs. The first f, indicates whether the car is going
above the speed limit. The second g, indicates that the car is driving at “dangerous speed” – defined as either
over 65 MPH or more than 10 MPH above the speed limit. Show how each of the inputs and outputs are
coded (in terms of binary values) and complete the truth table for the system.

Solution:

Speed limits:

45  00, 5501, 6510

Speed Ranges:

Below 45  00, 46-5501, 56-6510, 65+11

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 Truth Table

F(above speed limit), G(dangerous speed)

Speed Limits Range of car F G

00 00 0 0

00 01 1 0

00 10 1 1

00 11 1 1

01 00 0 0

01 01 0 0

01 10 1 0

01 11 1 1

10 00 0 0

10 01 0 0

10 10 0 0

10 11 1 1

Conclusion:
We learned the practical uses of GATES in this lab and implemented them on hardware as well as simulated
them on software. We also wrote the verilog codes and made truth tables in all cases.

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