Experiments-1
Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same using basic gates.
//4-variable logic expression solving
module ise_exp_1(
input A,B,C,D,
output F
);
assign F = (~A) | (B & C & D) | (A & ~B & ~C) | (A & C & ~D);
endmodule
// Test bench for above 4-variable logic expression
module ise_exp_1_tb;
// Inputs
reg A;
reg B;
reg C;
reg D;
// Outputs
wire F;
// Instantiate the Unit Under Test (UUT)
ise_exp_1 uut (
.A(A),
.B(B),
.C(C),
.D(D),
.F(F)
);
initial begin
// Initialize Inputs
D = 0; C = 0; B = 0; A = 0; #100;
D = 0; C = 0; B = 0; A = 1; #100;
D = 0; C = 0; B = 1; A = 0; #100;
D = 0; C = 0; B = 1; A = 1; #100;
D = 0; C = 1; B = 0; A = 0; #100;
D = 0; C = 1; B = 0; A = 1; #100;
D = 0; C = 1; B = 1; A = 0; #100;
D = 0; C = 1; B = 1; A = 1; #100;
D = 1; C = 0; B = 0; A = 0; #100;
D = 1; C = 0; B = 0; A = 1; #100;
D = 1; C = 0; B = 1; A = 0; #100;
D = 1; C = 0; B = 1; A = 1; #100;
D = 1; C = 1; B = 0; A = 0; #100;
D = 1; C = 1; B = 0; A = 1; #100;
D = 1; C = 1; B = 1; A = 0; #100;
D = 1; C = 1; B = 1; A = 1; #100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
Experiments-2A
Design a 4 bit full adder and subtractor and simulate the same using basic gates. (For 4-Bit Full Adder)
//2A: VERILOG CODE FOR 4-BIT FULL ADDER (THIS IS MAIN MODULE)
module FA_4bit_main(
input a,b,cin,
output s,cout
);
assign s = a ^ b ^ cin;
assign cout = (a&b) | (b&cin) | (cin&a);
endmodule
//VERILOG CODE OF 4-BIT FULL ADDER (THIS IS SUB MODULE UNDER MAIN MODULE)
module FA_4bit(
input [3:0] a,b,
output [3:0] sum,
output cout
);
wire c1,c2,c3,c4;
FA_4bit_main ad0( .a(a[0]), .b(b[0]),.cin(0), .s(sum[0]), .cout(c1));
FA_4bit_main ad1( .a(a[1]), .b(b[1]),.cin(c1), .s(sum[1]), .cout(c2));
FA_4bit_main ad2( .a(a[2]), .b(b[2]),.cin(c2), .s(sum[2]), .cout(c3));
FA_4bit_main ad3( .a(a[3]), .b(b[3]),.cin(c3), .s(sum[3]), .cout(c4));
assign cout = c4;
endmodule
// Test bench for above 4-variable logic expression
module fourbit_tb;
// Inputs
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
FA_4bit uut (
.a(a),
.b(b),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
b = 4'b1111; a = 4'b1111; #500; // sum=1110 & cout=1
b = 4'b1010; a = 4'b1110; #500;
b = 4'b1110; a = 4'b1000; #500;
b = 4'b1010; a = 4'b0011; #500;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
OUTPUT WAVEFORM OF 4-BIT FULL ADDER (as per the test cases values)
Experiments-2B
Design a 4 bit full adder and subtractor and simulate the same using basic gates. (For 4-Bit Full Subtractor)
//2B: VERILOG CODE FOR 4-BIT FULL SUBTRACTOR (THIS IS MAIN MODULE)
module FS_4bit_main(
input a,b,bin,
output d,bout
);
assign d = a ^ b ^ bin;
assign bout = (~a & b) | (~(a ^ b) & bin);
endmodule
//VERILOG CODE OF 4-BIT FULL SUBTRACTOR (THIS IS SUB MODULE UNDER MAIN MODULE)
module FS_4bit(
input [3:0] a,b,
output [3:0] diff,
output bout
);
wire c1,c2,c3,c4;
FS_4bit_main ad0( .a(a[0]), .b(b[0]),.bin(0), .d(diff[0]), .bout(c1));
FS_4bit_main ad1( .a(a[1]), .b(b[1]),.bin(c1), .d(diff[1]), .bout(c2));
FS_4bit_main ad2( .a(a[2]), .b(b[2]),.bin(c2), .d(diff[2]), .bout(c3));
FS_4bit_main ad3( .a(a[3]), .b(b[3]),.bin(c3), .d(diff[3]), .bout(c4));
assign bout = c4;
endmodule
Experiments-4
Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and Full Subtractor.
4A: Half Adder 4B: Full Adder 4C: Half Subtractor 4D: Full Subtractor
-- 4A: Half Adder code
module HA_ISE(
input A,B,
output SUM, CARRY
);
assign SUM = A ^ B;
assign CARRY = A & B;
endmodule
// 4A: Test bench for Half Adder
module HA_ISE_TB;
// Inputs
reg A;
reg B;
// Outputs
wire SUM;
wire CARRY;
// Instantiate the Unit Under Test (UUT)
HA_ISE uut (
.A(A),
.B(B),
.SUM(SUM),
.CARRY(CARRY)
);
initial begin
// Initialize Inputs
B = 0; A = 0; #100;
B = 0; A = 1; #100;
B = 1; A = 0; #100;
B = 1; A = 1; #100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
-- 4B: Full Adder code
module FA_ISE(
input a,b,cin,
output sum,carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a) ;
endmodule
// 4B: Test bench for Full Adder
module FA_ISE_TB;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
FA_ISE uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry)
);
initial begin
// Initialize Inputs
cin = 0; b = 0; a = 0; #100;
cin = 0; b = 0; a = 1; #100;
cin = 0; b = 1; a = 0; #100;
cin = 0; b = 1; a = 1; #100;
cin = 1; b = 0; a = 0; #100;
cin = 1; b = 0; a = 1; #100;
cin = 1; b = 1; a = 0; #100;
cin = 1; b = 1; a = 1; #100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
4B: OUTPUT WAVE for Full Adder
-- 4C: Half Subtractor code
module HS_ISE(
input a, b,
output D, B
);
assign D = a ^ b;
assign B = ~a & b;
endmodule
// 4C: Test bench for Half Subtractor
module HS_ISE_TB;
// Inputs
reg a;
reg b;
// Outputs
wire D;
wire B;
// Instantiate the Unit Under Test (UUT)
HS_ISE uut (
.a(a),
.b(b),
.D(D),
.B(B)
);
initial begin
// Initialize Inputs
b = 0; a = 0; #100;
b = 0; a = 1; #100;
b = 1; a = 0; #100;
b = 1; a = 1; #100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
4C: OUTPUT WAVE for Half Subtractor
-- 4D: Full Subtractor code
module FS_ISE(
input a, b, Bin,
output D, Bout
);
assign D = a ^ b ^ Bin;
assign Bout = (~a & b) | (~(a ^ b) & Bin);
endmodule
// 4D: Test bench for Full Subtractor
module FS_ISE_TB;
// Inputs
reg a;
reg b;
reg Bin;
// Outputs
wire D;
wire Bout;
// Instantiate the Unit Under Test (UUT)
FS_ISE uut (
.a(a),
.b(b),
.Bin(Bin),
.D(D),
.Bout(Bout)
);
initial begin
// Initialize Inputs
Bin = 0; b = 0; a = 0; #100;
Bin = 0; b = 0; a = 1; #100;
Bin = 0; b = 1; a = 0; #100;
Bin = 0; b = 1; a = 1; #100;
Bin = 1; b = 0; a = 0; #100;
Bin = 1; b = 0; a = 1; #100;
Bin = 1; b = 1; a = 0; #100;
Bin = 1; b = 1; a = 1; #100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
4D: OUTPUT WAVE for Full Subtractor
Experiments-5
Design Verilog HDL to implement Decimal adder.
// Verilog code of DECIMAL ADDER
module ise_DA(
input [3:0] A,
input [3:0] B,
output [3:0] Sum
);
assign Sum = A + B;
endmodule
// Test bench for DECIMAL ADDER
module DA_tb;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire [3:0] Sum;
// Instantiate the Unit Under Test (UUT)
ise_DA uut (
.A(A),
.B(B),
.Sum(Sum)
);
initial begin
// Initialize Inputs
A = 4; B = 7; #600;
A = 9; B = 8; #600;
A = 3; B = 3; #600;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
5: OUTPUT WAVE for DECIMAL ADDER
Experiments-6A / 2:1 MULTIPLEXER
Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.
//6A: VERILOG CODE FOR 2:1 MULTIPLEXER
module ise_mux_2to1(
input D0, D1, S,
output Y
);
assign Y = (S) ? D1:D0;
endmodule
// Test bench for 2:1 MULTIPLEXER
module mux_2to1_tb;
// Inputs
reg D0;
reg D1;
reg S;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
ise_mux_2to1 uut (
.D0(D0),
.D1(D1),
.S(S),
.Y(Y)
);
initial begin
// Initialize Inputs
D0 = 1'b0;
D1 = 1'b0;
S = 1'b0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #40 D0 = ~ D0;
always #20 D1 = ~ D1;
always #10 S = ~ S;
always@(D0 or D1 or S)
$monitor("At time = %t, Output = %d", $time, Y);
endmodule
OUTPUT WAVEFORM OF 2:1 MULTIPLEXER
Experiments-6B / 4:1 MULTIPLEXER
Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.
//6B: VERILOG CODE FOR 4:1 MULTIPLEXER
module ise_mux_4to1(
input a,b,c,d,
input s0,s1,
output out
);
assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule
// Test bench for 4:1 MULTIPLEXER
module mux_4to1_tb;
// Inputs
reg a;
reg b;
reg c;
reg d;
reg s0;
reg s1;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
ise_mux_4to1 uut (
.a(a),
.b(b),
.c(c),
.d(d),
.s0(s0),
.s1(s1),
.out(out)
);
initial begin
// Initialize Inputs
a = 1'b0;
b = 1'b0;
c = 1'b0;
d = 1'b0;
s0 = 1'b0;
s1 = 1'b0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #40 a = ~a;
always #20 b = ~b;
always #10 c = ~c;
always #5 d = ~d;
always #80 s0 = ~s0;
always #160 s1 = ~s1;
always@(a or b or c or d or s0 or s1)
$monitor("At time = %t, Output = %d", $time, out);
endmodule
OUTPUT WAVEFORM OF 4:1 MULTIPLEXER
Experiments-6C / 8:1 MULTIPLEXER
Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.
//6C: VERILOG CODE FOR 8:1 MULTIPLEXER
module mux8_1(
input D0, D1, D2, D3, D4, D5, D6, D7,
input S0, S1, S2,
output out
);
assign S1bar=~S1;
assign S0bar=~S0;
assign S2bar=~S2;
assign out =
(D0 & S2bar & S1bar & S0bar)
| (D1 & S2bar & S1bar & S0)
| (D2 & S2bar & S1 & S0bar)
+ (D3 & S2bar & S1 & S0)
+ (D4 & S2 & S1bar & S0bar)
+ (D5 & S2 & S1bar & S0)
+ (D6 & S2 & S1 & S0bar)
+ (D7 & S2 & S1 & S0);
endmodule
// Test bench for 8:1 MULTIPLEXER
module mux8_1_tb;
// Inputs
reg D0;
reg D1;
reg D2;
reg D3;
reg D4;
reg D5;
reg D6;
reg D7;
reg S0;
reg S1;
reg S2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
mux8_1 uut (
.D0(D0),
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.D5(D5),
.D6(D6),
.D7(D7),
.S0(S0),
.S1(S1),
.S2(S2),
.out(out)
);
initial begin
// Initialize Inputs
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b0;
D4 = 1'b0;
D5 = 1'b0;
D6 = 1'b0;
D7 = 1'b0;
S0 = 1'b0;
S1 = 1'b0;
S2 = 1'b0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #10 D0 = ~D0;
always #20 D1 = ~D1;
always #30 D2 = ~D2;
always #40 D3 = ~D3;
always #50 D4 = ~D4;
always #60 D5 = ~D5;
always #70 D6 = ~D6;
always #80 D7 = ~D7;
always #90 S0 =~ S0;
always #100 S1 = ~S1;
always #200 S2 = ~S2;
always@(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S0 or S1 or S2)
$monitor("At time = %t, Output = %d", $time, out);
endmodule
OUTPUT WAVEFORM OF 8:1 MULTIPLEXER
