ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Vision of the Institute

Preparing Competent Engineering and Management Professionals to Serve the Society.

Mission of the Institute

1. Providing Students with a Sound Knowledge in Fundamentals of their branch of Study.

2. Promoting Excellence in Teaching, Training, Research and Consultancy.
3. Exposing Students to Emerging Frontiers in various domains enabling Continuous Learning.
4. Developing Entrepreneurial acumen to venture into Innovative areas.
5. Imparting Value based Professional Education with a sense of Social Responsibility.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Vision of the Department

To achieve academic excellence in Electronics and Communication engineering by imparting quality technical
education and facilitating research activities

Mission of the department

M1: Establishing state of the art laboratory facilities and infrastructure to develop the spirit of
innovation and entrepreneurship
M2: Nurturing the students with technical expertise along with professional ethics to provide solutions
for societal needs
M3: Encourage lifelong learning and research among the students and faculty

Program Educational Objectives:

After successful completion of the program,
PEO1: Graduates of the program will have successful technical and professional career in engineering,
technology and multidisciplinary environments.
PEO2: Graduates of the program will utilize their knowledge, technical and communication skills to propose
optimal solutions to problems related to society in the field of Electronics and Communication.
PEO3: Graduates of the program will exhibit good interpersonal skills, leadership qualities

Dept. of ECE SJCIT 1

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

INSTRUCTIONS:
1) Test the components/devices before starting experiment.

2) After rigging up the circuits do not switch on the power supply, show the circuit to

lab in-charge and then start the experiment.

3) Conduct the experiment as per procedure.

4) Record the readings as per instructions.

5) Confirm successful completion of experiments by plotting the relevant graphs and

calculations.

6) After completion of experiment replace the components in their respective positions.

7) Negligence of one candidate will result in penalty for the whole group/batch.

8) Keep components and test Devices in good condition. Replace probes, wires and

components at the first sign of deterioration.

9) Don’t work on equipment before you know proper procedure.

10) Keep the lab Clean.

Dept. of ECE SJCIT 2

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

CONTENTS
EXP. TOPIC
NO
Experiments (All the experiments has to be conductd using discrete components)
1. Design and set up the BJT common emitter voltage amplifier with and without
feedback and determine the gain- bandwidth product, input and output impedances
2. Design and set-up BJT/FET i) Colpitts Oscillator, and ii) Crystal Oscillator.
3. Design and set-up the circuit using Op-Amp
i)Adder, ii)Integrator, iii)Differentiator, iv)Comparator
4. Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary input
using toggle switches (ii) by generating digital inputs using mod-16
5. Design and implement
(a) Half Adder & Full Adder using (i) basic logic gates and (ii) NAND gates.
(b) Half subtractor & Full subtractor using (i) basic logic gates and (ii) NAND
gates. (c) 4-variable function using IC 74151(8:1 MUX).
6. Realize
i)Binary to Gray code conversion & vice-versa (74139)
ii) BCD to Excess-3 code conversion and vice-versa
7. a) Realize using NAND Gates
i) Master-Slave JK Flip Flop, ii) D Flip Flop & iii) T Flip-Flop.
b)Realize the following shift registers using IC7474/IC 7495
(a) SISO (b) SIPO (c) PISO (d) PIPO (e) Ring and (f) Johnson counter.
8. Realize i) Design Mod – N Synchronous Up Counter & Down Counter using 7476
JK Flip-flop (ii) Mod-N Counter using IC7490 / 7476
(iii) Synchronous counter using IC74192
Demonstration Experiments ( For CIE )
9 Design and Test the second order Active Filters and plot the frequency response,
i) Low pass and High pass Filter ii) Band pass and Band stop Filter
10. Design and test the following using 555 timer
i) Monostable Multivibraator ii) Astable Multivibrator
11. Design and Test a Regulated Power supply
12. Design and test an audio amplifier by connecting a microphone input and observe
the output using a loud speaker.

Dept. of ECE SJCIT 3

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]
Experiment No: 1
Design and set up the BJT common emitter voltage amplifier
with and without feedback and determine the gain- bandwidth
product, input and output impedances
AIM: Design and set up the BJT common emitter voltage amplifier with and without
feedback and determine the gain- bandwidth product, input and output impedances.
OBJECTIVES:
1. To understand the frequency response characteristics of a BJT common emitter voltage
amplifier.
2. To understand the effect of negative feedback on gain-bandwidth product,
input and output impedances.

COMPONENTS REQUIRED:

Sl. No Component Name Quantity

1 Power supply: 0-30V 1
2 CRO: 20MHz 1
3 Signal generator: 1-1MHz 1
4 Resistors: 680Ω, 2.2KΩ, 10KΩ, 47KΩ 1 each
5 Capacitors: 0.1 µF, 1 µF, 22µF 1 each
6 Transistors: SL100/BC107 1
7 Bread board 1
8 CRO Probes and connecting wires Few

THEORY: The BJT common emitter amplifier is a general-purpose BJT-based amplifier that
it typically used for voltage amplification. It offers great voltage gain and ok current gain.
The input impedance is moderate but unfortunately it has high output impedance. The
output is inverted with respect to the input. It is commonly followed with a buffer circuit such
as a common-collector amplifier to reduce the output impedance. The common emitter
amplifier find use in audio and RF applications.

Dept. of ECE SJCIT 4

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]
CIRCUIT DIAGRAM:

Figure 1a: BJT amplifier without feedback

Figure 1b: BJT amplifier with feedback

DESIGN:
Let Vcc = 12V; IC = 2mA; VE = 1.5V; VCEQ = 6V; hfe (βDC) = 100.
1. To find RE:
Given VE = 1.5V.
Therefore, RE = VE / IE = VE / IC = 750 Ω RE = 680 Ω (standard)
2. To find RC:
From the collector loop writing KVL we get

VCC = ICRC + VCE +VE

RC = (VCC – VCE – VE) / IC
RC = 2.25 kΩ Therefore, RC = 2.2kΩ (standard)

Dept. of ECE SJCIT 5

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]
3. To find R1 and R2:
The base current IB = IC / hfe = 2mA / 100 =
0.02mA

Let I1 be current through R1 and I1 be 10

times of IB. Writing the base loop KVL we get,
VB = VE + VBE = 1.5 + 0.6= 2.1V Therefore, VB = 2.1V

Now, R1 = (VCC – VB) / 10I1

R1 = (12 - 2.1)/10x0.02m = 49.5kΩ Therefore, R1 = 47 kΩ (standard)

Also, R2 = VBE+VRE / 9 IB
R2 = 0.6+1.5 /9x0.02m =11.66 kΩ Therefore, R2 = 10 kΩ (standard)

4. Input impedance (Zin):

To calculate the input impedance first calculates the value of Zin (base). Zin (base) =
βre where re is the resistance of emitter diode.
RE = VE / IE = 1.5 / 2.02 = 720Ω
Zin(base) = βRE = 100 * 720 = 72KΩ
The input impedance of an amplifier is the input impedance seen by the A.C.
source driving the amplifier. Therefore, the biasing resistor R1 and R2 are
included as follows-
Zin = (1+βRE) || R1 || R2 Zin = 8.3 kΩ
5. Output impedance (Zo):
The output impedance is given by, Zo =
RC || RL
Let RL = 10 kΩ
Therefore, Zo =1.8k Ω
6. To find CC1, CC2 and CE:
Let FL = 100Hz (Lower cut-off
frequency)

Input coupling capacitor:

CC1 = 1 / (2*π*Zin*FL)
CC1 = 1/ (2*π*8.3k*100) =0.19µF Therefore, CC1= 0.1µF (standard)

Output coupling capacitor:

CC2 = 1 / (2*π*(RC + RL) *Fin)
CC2 =1/ (2*π*(2.25k + 10k) *100) = 0.98µF Therefore, CC2= 1µF

Dept. of ECE SJCIT 6

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

7. Design of bypass capacitors, CE:

XCE ≤ RE/10=720/10=72
Emitter bypass capacitor, CE = 1 / (2*π*f * XCE)
CE = 1/ (2*π* 100 * 72) =22.10µF Therefore, CE =22 µF (standard)

PROCEDURE:
1. Rig up the circuit as per the given circuit diagram.
2. Switch on the D.C. power supply = 12V is given to the circuit.
3. Check the D.C. conditions without any input signal and record in table 1.
4. Select sine wave input and set the input signal amplitude to 10mV frequency at
1kHz constant and observe the input / output waves on the CRO and adjust the
input amplitude such that the output is undistorted waveform. Calculate mid-
band gain using AV = Vo(p-p) / Vin(p-p).
5. Keeping the input amplitude constant, vary the frequency from 100Hz to 2MHz
and note down the corresponding output voltage (p-p) in the table 2.
6. Calculate gain in dB and plot the frequency response curve and find the bandwidth.

OBSERVATIONS:
Table 1: DC Conditions:
VCE VBE
Parameter
(in volts) (in volts)
Theoretical 6 0.7
Practical

Table 2: Frequency response without feedback and Vin (p-p) = 10mV

Frequency Vo(p- p) AV AV (dB) = Frequency Vo(p- p) AV = AV(dB)

= Vo /Vin =
(Hz) (V) 20*log(AV) (Hz) (V)
Vo/Vin 20*log (AV)
100 50K
200 100K
300 300K
500 500K
700 600K
1K 700K
3K 800K
5K 900K
10K 1M
20K 2M

Dept. of ECE SJCIT 7

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Table 3: Freque ncy response with feedback and Vin (p-p) = 10mV

Frequency Vo(p- p) AV AV (dB) = Frequency Vo(p- p) AV = AV(dB)

= Vo /Vin =
(Hz) (V) 20*log(AV) (Hz) (V)
Vo/Vin 20*log (AV)
100 50K
200 100K
300 300K
500 500K
700 600K
1K 700K
3K 800K
5K 900K
10K 1M
20K 2M

Measurement of Input Impedance:

Figure 1b: Measurement of Input Impedance, Zi

PROCEDURE:
1. Connect the circuit as shown in above figure.
2. Set the following:
a. DRB to zero.
b. Input (Vin) sine wave amplitude of 10mV.
c. Input sine wave frequency to any mid band frequency (say,100 KHz).
3. Measure Vo(p-p).
4. Increase DRB till VO = Vo(p-p)/2.
5. The corresponding DRB value gives the input impedance Zi.

Dept. of ECE SJCIT 8

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]
Measurement of Output Impedance:

Figure 1c: Measurement of Output Impedance, Zo

PROCEDURE:
1. Connect as in Figure (2).
2. Set the following:
a. DRB to maximum value
b. Input (Vin) sine wave amplitude to 10mV.
c. Input sine wave frequency to any mid band frequency (say, 100 KHz)
3. Measure Vo(p-p).
4. Decrease DRB till Vo = Vo(p-p)/2.
5. The corresponding DRB value gives the output impedance Zo.

MODEL GRAPH:

Bandwidth= fl-fh
Figure of Merit =Bandwidth x Mid-band Gain

Dept. of ECE SJCIT 9

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]
RESULTS:

With CE (Without feedback): Without CE: (With feedback):

Av (Mid-band) =. . . . . . Av (Mid-band) =. . . . . .
Bandwidth = ........ Hz Bandwidth = ....... Hz
Input impedance =........ Ω Input impedance = ........ Ω
Output impedance = ..... Ω Output impedance = ..... Ω
Figure of Merit=………….. Figure of Merit=………….
The RC-coupled amplifier was designed and rigged up and the parameters were found.

Dept. of ECE SJCIT 10

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Experiment No: 2
Design and set up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator

2A. BJT COLPITTS OSCILLTOR

AIM: To design and construct a BJT Colpitts oscillator at the given operating frequency.
Components Required:

Sl.No Components Range Quantity

1 Transistor BC107 1
2 18K, 1.8KΩ,
Resistors each1
3.9K,470Ω
3 Inductor 5mH 1
4 Capacitors 1000pF,0.1 µF 2

Theory: Colpitts oscillator is very popular and is commonly used as local oscillator in
radio receivers. The collector voltage is applied to the collector through inductor L whose
reactance is high compared with X2 and may therefore be omitted from equivalent
circuit, at zero frequency. The circuit operates as Class C. the tuned circuit determines
basically the frequency of oscillation.

CIRCUIT DIAGRAM:

Dept. of ECE SJCIT 11

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Design:
Let Vcc = 12V; IC = 2mA; VE = 1.5V; VCEQ = 6V; hfe (βDC) = 100.
1. To find RE:
Given VE = 1.5V.
Therefore, RE = VE / IE = VE / IC = 750 Ω RE = 680 Ω (standard)
2. To find RC:
From the collector loop writing
KVL we get

VCC = ICRC + VCE +VE

RC = (VCC – VCE – VE) / IC
RC = 2.25 kΩ Therefore, RC = 2.2kΩ (standard)
3. To find R1 and R2:
The base current IB = IC / hfe =
2mA / 100 = 0.02mA

Let I1 be current through R1 and

I1 be 10 times of IB. Writing the
base loop KVL we get,
VB = VE + VBE = 1.5 + 0.6= 2.1V Therefore, VB = 2.1V

Now, R1 = (VCC – VB) / 10I1

R1 = (12 - 2.1)/10x0.02m = 49.5kΩ Therefore, R1 = 47 kΩ (standard)

Also, R2 = VBE+VRE / 9 IB
R2 = 0.6+1.5 /9x0.02m =11.66 kΩ Therefore, R2 = 10 kΩ (standard)
4. To find CC1, CC2 and CE:
Let FL = 100Hz (Lower
cut-off frequency)

Input coupling capacitor:

CC1 = 1 / (2*π*Zin*FL)
CC1 = 1/ (2*π*8.3k*100) =0.19µF Therefore, CC1= 0.1µF (standard)

Output coupling capacitor:

CC2 = 1 / (2*π*(RC + RL) *Fin)
CC2 =1/ (2*π*(2.25k + 10k) *100) = 0.98µF Therefore, CC2= 1µF

Dept. of ECE SJCIT 12

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

DESIGN OF TANK CIRCUIT

Assume = fo = 100 KHz
where
Ceq = C1+C2
Assume C1 = C2 = 1000 pF
𝑓0 =
2𝜋√𝐿𝐶𝑒𝑞
Ceq = 0.05*10- 6 On solving L = 5 mH (Use decade inductance box)

PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Before connecting the feedback network, check the circuit for biasing
conditions i.e. check VCE, and VRE.
3. After connecting the feedback network. Check the output.
4. Check for the sinusoidal waveform at output. Note
down the frequency of the output waveform and check for
any deviation from the designed value of the frequency.
5. To get a sinusoidal waveform adjust 22KΩ potentiometer.
6. DCB/DIB can be varied to vary the frequency of the output waveform.

IDEAL WAVEFORM:

RESULT: The Colpitt‟s oscillator is designed and constructed for the given
frequency.

Dept. of ECE SJCIT 13

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

2 B. BJT-CRYSTAL OSCILLATOR

AIM: Testing for the performance of the BJT- crystal oscillator for fo> 4MHz.

COMPONENTS REQUIRED:

Sl.No Components Range Quantity

1 Transistor BC107 1
2 Resistors each1
3 Potentiometer 22KΩ 1
4 Capacitors 47µF,0.1 µF 2

THEORY: A crystal oscillator is basically a tuned oscillator using a

piezoelectric crystal as a resonant circuit. The crystal has a greatest stability
in holding consent charge at whatever frequency the crystal is originally cut
to operate. Crystal oscillators are used whenever great stability is required,
such as communication, transmitters and receivers.
Characteristics of a Quartz crystal: A quartz crystal exhibits the property
that whenever mechanical stress is applied across one set of its faces, a
difference of potential develops across the opposite faces. This property of a
crystal is called piezoelectric effect. Similarly, a voltage applied across one
set of faces of the crystal causes mechanical distortion in the crystal shape.
When alternating voltage is applied to a crystal, mechanical vibrations are
set up- these vibrations having a natural resonating frequency dependent on
the crystal.
The inductor L and the capacitor C represent electrical equivalents of crystal
mass and compliance respectively, whereas resistance R is an electrical
equivalent of the crystal structures internal friction. The shunt capacitance
CM represents the capacitance due to mechanical mounting of the crystal.
Because the crystal loses, represented by R, are small, the equivalent crystal
Q factor is high typically 20,000. Values of Q up to almost 106 can be
achieved by using crystals. The crystal has two resonant frequencies. One
resonant condition occurs when the reactance‟s of the series RLC leg are
equal.

Dept. of ECE SJCIT 14

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

CIRCUIT DIAGRAM:

PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Before connecting the feedback network, check the circuit for biasing
conditions i.e. check VCE, and VRE.
3. After connecting the feedback network. Check the output.
4. Check for the sinusoidal waveform at output. Note down the
frequency of the output waveform and check for any deviation from
the designed value of the frequency.
5. To get a sinusoidal waveform adjust 22KΩ potentiometer

IDEAL WAVEFORM:

RESULT: The crystal oscillator is designed and constructed for the

given frequency.

Dept. of ECE SJCIT 15

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Experiment No: 3
Design and set up the circuits using Op-Amp i)Adder, ii) Integrator,
iii) Differentiator, iv) Comparator

3 i) Inverting Adder
AIM: Design an Inverting Adder using Op-Amp(µA741).

Components required:

Sl.No. Particulars Specification Quantity

1. OP AMP µA741 01
2. Resistors 1KΩ 04

Theory:

Adder is one of the linear applications of the Op-Amp. A circuit

whose output is the sum of several input signals is called a
summer (Adder).

Circuit Diagram

Procedure:

1. Connections are made as shown in the circuit diagram.

2. Apply DC input V1 ,V2 and V3 of various values and tabulate the

output V0

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 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Tabular Column:

V1 V2 V3 Theoretical o/p (Vth) Practical o/p[V0= -(V1+V2+V3)]

0.5v 0.5v 1v -2V
1v 1v 2v -4V
1v 0.5v 1.5v -3V
0.5v 2v 2.5v -5V

3 ii) Integrator
AIM: To design and test the performance of integrator and differentiator
circuits using Op-amp.

COMPONENTS REQUIRED:

Sl.No. Particulars Specification Quantity

1. Op Amp µA741 01
2. Resistor 15KΩ 01
3. Capacitor 0.01µF 01

THEORY:
Integrator: In an integrator circuit, the output voltage is integral of the
input signal. The output voltage of an integrator is given by Vo = -1/R1Cf ∫t
Vidt

At low frequencies the gain becomes infinite, so the capacitor is fully

charged and behaves like an open circuit. The gain of an integrator at
low frequency can be limited by connecting a resistor in shunt with
capacitor.

DESIGN:
Given :
Ri= 10 KΩ ; f= 1 kHz
Cf = 1/ (2πRf)
Rf = 10 R = 10*10 KΩ = 100 KΩ
Cf = 1/ (2π * 100*103 * 103)= 0.001µF

Dept. of ECE SJCIT 17

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Circuit Diagram

Differentiator: In the differentiator circuit the output voltage is the

differentiation of the input voltage. The output voltage of a differentiator is
given . The input impedance of this circuit
decreases with increase in frequency, thereby making the circuit sensitive to
high frequency noise. At high frequencies circuit may become unstable.

Given:

Ci = 0.01uF fi = 1kHz
Rf = 1/ (2πCifi) = 1/ [2π*(0.01*10-6)*(1*103 )] = 15.9kΩ Standard 15.kΩ

Dept. of ECE SJCIT 18

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Circuit Diagram

Input and output Waveforms:

PROCEDURE:

Integrator:
1.Connections are made as per the circuitdiagram.
2.Apply the square or sine input signal at high frequency usingAFO.
3.Note the corresponding output waveforms and plot thegraph.
Differentiator:
1. Connections are made as per the circuitdiagram.
2. Apply the square or sine input signal at low frequency usingAFO.
3. Note the corresponding output waveforms and plot thegraph.

Dept. of ECE SJCIT 19

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Comparator circuit

Result: Output waveforms are observed on CRO

Viva questions :

1. What are the limitations of the basic differentiator circuit?

2. Mention the Applications of Integrator/Differentiator
3. How Op-amp works as Integrator/Differentiator?

Dept. of ECE SJCIT 20

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Experiment No: 4
Design 4-bit R-2R Op-Amp Digital to Analog Converter
i) for a 4-bit binary input using toggle switches
ii) by generating digital inputs using mod-16

4 i) Design 4 bit R–2R Op-Amp Digital to Analog Converter

using Toggle Switches
AIM: To verify the working of R-2R DAC for a 4-bit binary input using toggle
switches (Vref=5V).
COMPONENTS REQUIRED :

Sl.No Particulars Specification Quantity

1 OP AMP uA741 01
2. Resistors as per design as per design
Theory:
In electronics, a Digital-to-Analog converter (DAC, D/A, D–A, D2A, or D-to-A) is
device that converts a digital signal into an analog signal. An analog-to-digital
converter (ADC) performs the reverse function. DACs are commonly used in
music players to convert digital data streams into analog audio signals. They are
also used in televisions and mobile phones to convert digital video data into
analog video signals which connect to the screen drivers to display monochrome
or color images.
An R–2R Ladder is a simple and inexpensive way to perform digital-to-analog
conversion, using repetitive the non-repetitive reference network arrangements
of precise resistor networks in a ladder-like configuration. In a basic R–2R
resistor ladder network Bit a1 (most significant bit, MSB) through bit a0 (least
significant bit, LSB) are driven from digital logic gates. Ideally, the bit inputs are
switched between V = 0 (logic 0) and V =Vref(logic1).The R–2R network causes
these digital bits to be weighted in their contribution to the output voltage Vout.
Depending on which bits are set to 1 and which to 0, the output voltage (Vout)
will have a corresponding stepped value between 0 and Vref minus the value of
the minimal step, corresponding to bit. The actual value of Vref(and the voltage
of logic 0) will depend on the type of technology used to generate the digital
signals.

Dept. of ECE SJCIT 21

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

CIRCUIT DIAGRAM

In this circuit the 7493 IC simply provides digital inputs to DAC. It is a counter
IC and not an integral part of the DAC circuit. You can apply any combinations
of binary inputs to D3D2D1D0.

Design:
4 bit R-2R DAC for an O/P voltage of 5 V when the input is DoD1D2D3
R f Vref  D3 D2 D1 D0 
V0    2  4  8  16  ,Assume Rf =2R and R= 10K, Vref=5V
R  
TABULAR COLUMN
Binary Inputs Analog O/P Analog O/P
Decimal D3 D2 D1 D0 Vo(volts)
Value Vo(volts)
(MSB) (LSB) Theoretical values Practical values
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Dept. of ECE SJCIT 22
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4 ii) Design 4 bit R–2R Op-Amp Digital to Analog Converter using IC7493

AIM: To verify the working of R-2R DAC for a 4-bit binary input IC7493

COMPONENTS REQUIRED :

Sl.No Particulars Specification Quantity

1 OP AMP uA741 01
2 Counter IC 7493 01
3 Resistors as per design as per design

CIRCUIT DIAGRAM

In this circuit the 7493 IC simply provides digital inputs to DAC. It is a counter
IC and not an integral part of the DAC circuit. You can apply any combinations
of binary inputs to D3D2D1D0.

IDEAL WAVEFORM

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Procedure:

1. Connections are made as shown in the circuit diagram.

2. Digital input data is given at D3, D2, D1, D0 and corresponding Vo is
observed in CRO.
3. Note down the Step Size and Full Scale Values .

Calculations:
Step Size = -----------V Full Scale =----------V

Result:
Practical values are calculated and compared with theoretical values

Viva Questions

1. Mention different types of digital to analog converters (DAC).

2. Describe types of analog to digital converters (ADC)
3. List out differences between R2R and successive approximation converter.
4. What is IC 7493 used for?

Dept. of ECE SJCIT 24

 ANALOG & DIGITAL SYSTEM DESIGN LAB [BECL305]

Experiment No: 5
Design and implement a) Half Adder & Full Adder using Basic gates and
NAND gates, b) Half Subtractor & Full Subtrator using NAND gates, c) 4
Variable function using IC74151 (8:1 MUX).

AIM: To Design and implement Half Adder & Full Adder using (i) basic gates and
(ii) NAND gates.

COMPONENTS REQUIRED:-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 AND gate 7408
2 OR gate 7432
3 Not gate 7404
4 EX-OR gate 7486
5 NAND gate 7400
6 Patch chords
Trainer Kit

A i) HALF-ADDER:
THEORY:
A combinational logic circuit that performs the addition of two data
bits, A and B, is called a half-adder. Addition will result in two output bits;
one of which is the sum bit, S, and the other is the carry bit, C. The
Boolean functions describing the half-adder are:
Design

Logic Diagram
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i) Basic Gates:

ii) NAND Gates:

A ii) FULL–ADDER
The half-adder does not take the carry bit from its previous stage into
account. This carry bit from its previous stage is called carry-in bit. A
combinational logic circuit that adds two data bits, A and B, and a carry-in
bit, Cin, is called a full-adder.

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Design:
Boolean Expression:

K-Map

Logic Diagram:

i) Basic Gates

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ii) NAND Gates

Truth Table:

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PROCEDURE:
1. Make connections as shown in the circuit diagram.
2. Connect Vcc and GND to respective pins of IC
3. Switch on the trainer kit.
4. Apply inputs using toggle switches and verify the truth
table.

B i) Half-Subtractor
Subtracting a single-bit binary value B from another A (i.e. A B) produces
a difference bit D and a borrow out bit B-out. This operation is called half
subtraction and the circuit to realize it is called a half subtractor. The Boolean
functions describing the half- Subtractor are:

Design:
Boolean Expression:

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Diff = AB+AB =A B
Borrow = A . B

K – MAP Simplification:

Br

Logic Diagram:

TRUTH TABLE:

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B ii) FULL SUBTRACTOR:

Subtracting two single-bit binary values, B, Cin from a singlebit value A
produces a difference bit D and a borrow out Br bit. This is called full
subtraction.

TRUTH TABLE:

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Boolean Expression

Logic Diagram:

PROCEDURE:

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1. Make connections as shown in the circuit diagram.

2. Connect Vcc and GND to respective pins of IC
3. Switch on the trainer kit
4. Apply inputs using toggle switches and verify the truth
table.

RESULT: Full adder, Full Subtractor circuits are realized using logic gates
and the truth tables are verified.

C) 4-variable function using IC74151 (8:1 MUX)

 PIN DETAILS OF 74151:

Theory:
 Multiplexer is a combinational circuit that is one of the most widely used
in digital design.
 The multiplexer is a data selector which gates one out of several inputs to
a single o/p. It has n data inputs & one o/p line & m select lines where
2m= n shown in fig a.
 Depending upon the digital code applied at the select inputs one out of n
data input is selected & transmitted to a single o/p channel.
 Normally strobe (G) input is incorporated which is generally active low
which enables the multiplexer when it is LOW. Strobe i/p helps in
cascading.
 IC 74151A is an 8: 1 multiplexer which provides two complementary
outputs Y & Y. The o/p Y is same as the selected i/p & Y is its
complement. The n: 1 multiplexer can be used to realize a m variable
function. (2m= n, m is no. of select inputs).

TRUTH TABLE:

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Logic Diagram:

PROCEDURE:
1. Make connections as shown in the circuit diagram.
2. Connect Vcc and GND to respective pins of IC.
3. Switch on the trainer kit.
4. Apply inputs using toggle switches and verify the truth table.

RESULT:
The Operation of Multiplexer has been realized and verified with the truth table.
Experiment No: 6
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Realize i) Binary to Gray Code conversion Vic-versa

(IC74139), ii) BCD to Excess-3 code conversion and vice versa

i) Binary to Gray Code conversion Vice-versa

Binary to Gray code conversion & vice-versa (74139)

COMPONENTS REQUIRED:-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 NAND gate(2 7400
2 pin) NAND
3 gate(4 pin) 74139
4 DEMUX 7404
5 Not gate
6 Patch chords
Trainer Kit

TRUTH TABLE:
BINARY CODE GRAY CODE

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
LOGIC DIAGRAM FOR THE FOLLOWING FUNCTION USING IC 74139:

 G0 = m (1,2,5,6)
 G1 = m (2,3,4,5)
 G2 = m (4,5,6,7)

GRAY TO BINARY CODE CONVERSION USING IC74139

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TRUTH TABLE:

GRAY CODE BINARY CODE

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 1 0 1 0
0 1 0 0 1 1
1 1 0 1 0 0
1 1 1 1 0 1
1 0 1 1 1 0
1 0 0 1 1 1

LOGIC DIAGRAM FOR THE FOLLOWING FUNCTION USING IC 74139:

 B0 = m (1,2,4,7)
 B1 = m (2,3,4,5)
 B2 = m (4,5,6,7)

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Procedure:
1) Rig up the circuit using NAND gates and then with IC74139 as shown in
figure.
2) Verify the output with the truth table Value
3) The output obtained practically should match the required result.

Result: Operation of Decoder and their applications in Code

Converters has been realized and verified.

Viva Questions:
1. Define Demux& Decoder.
2. What are the different methods of indicating active low signals?
3. What is the difference between Demux and Decoder?

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B. BCD to Excess-3 code conversion and vice-versa.

COMPONENTS REQUIRED:-

Sl. No Name of the IC Number

Component
1 EXOR 7486
2 gate Patch
3 chords
4 Trainer 7483
Kit
4 bit parallel
adder/subtractor

Theory: Code converter is a combinational circuit that translates the input

code word into a new corresponding word.
The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit
adder feed BCD-code to the 4-bit adder as the first operand and then feed
constant 3 as the second operand. The output is the corresponding excess-
3 code. To make it work as a excess-3 to BCD converter, we feed excess- 3
code as the first operand and then feed 2‟s complement of 3 as the second
operand. The output is the BCD code.

TRUTH TABLE FOR BCD TO EXCESS -

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RUTH TABLE FOR EXCESS – 3 TO BCD:-

Logic Diagram using IC7483 FOR BCD TO EXCESS – 3 & VICE VERSA:-

PROCEDURE:

RESULT: Realized BCD code to Excess-3 code conversion and vice versa
using 7483 IC

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VIVA QUESTIONS:

1. What are the different methods of representing –ve numbers,

which type is preferred and why?
2. Procedure for 1‟s complement method of subtraction
3. Procedure for 2‟s complement method of subtraction
4. State different methods of subtraction using complementary
methods
5. Why complementary methods are preferred?
6. What are the advantages of 2‟s complement method?
7. Internal diagram of IC 7483, what is the significance of Cin and
Cout pins.
8. Types of Adders, advantages and disadvantages of different
types, Explain Look ahead carry adder.
9. What is the internal structure of 7483 IC?
10. What do you mean by code conversion?
11. What are the applications of code conversion?
12. How do you realize a subtractor using full adder?
13. What is a ripple Adder? What are its disadvantages?

B. BCD to Excess-3 code conversion and vice-versa.

COMPONENTS REQUIRED:-

Sl. No Name of the IC Number

Component
1 EXOR 7486
2 gate Patch
3 chords
4 Trainer 7483
Kit
4 bit parallel
adder/subtractor

Theory: Code converter is a combinational circuit that translates the input

code word into a new corresponding word.
The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit
adder feed BCD-code to the 4-bit adder as the first operand and then feed
constant 3 as the second operand. The output is the corresponding excess-
3 code. To make it work as a excess-3 to BCD converter, we feed excess- 3
code as the first operand and then feed 2‟s complement of 3 as the second
operand. The output is the BCD code.

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TRUTH TABLE FOR BCD TO EXCESS -

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TRUTH TABLE FOR EXCESS – 3 TO BCD:-

Logic Diagram using IC7483 FOR BCD TO EXCESS – 3 & VICE VERSA:-

PROCEDURE:

RESULT: Realized BCD code to Excess-3 code conversion and vice versa
using 7483 IC

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VIVA QUESTIONS:

1. What are the different methods of representing –ve numbers, which

type is preferred and why?
2. Procedure for 1‟s complement method of subtraction
3. Procedure for 2‟s complement method of subtraction
4. State different methods of subtraction using complementary
methods
5. Why complementary methods are preferred?
6. What are the advantages of 2‟s complement method?
7. Internal diagram of IC 7483, what is the significance of Cin and
Cout pins.
8. Types of Adders, advantages and disadvantages of different
types, Explain Look ahead carry adder.
9. What is the internal structure of 7483 IC?
10. What do you mean by code conversion?
11. What are the applications of code conversion?
12. How do you realize a subtractor using full adder?
13. What is a ripple Adder? What are its disadvantages?

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Experiment No: 7
a) Realize using NAND Gates i) Master-Slave JK Flip-flop, ii) D Flip-flop, iii) T
Flip-flop
b) Realize the shift registers using IC 7474/7495: i) SISO ii)SIPO iii) PISO iv)
PIPO v) Ring Counter and vi) Johnson Counter.

AIM: - Realize Master-Slave JK, D & T Flip-Flops using NAND Gates.

COMPONENTS REQUIRED:-

Sl.No NAME OF THE IC NUMBER

COMPONENT
1 3 Input NAND gate 7410
2 2 Input NAND gate 7400
3 NOT gate 7404
4 Patch chords
5 Trainer Kit
THEORY:
JK flip-flop provides the solution for SR flip-flop problem.
Compared to SR flipflop, JK flip flop has two new connections from the Q
and Q outputs back to the original input gates. JK flip-flop behaves like
the SR flip-flop except for input condition 1 and 1. Its output toggles for
every clock pulse input unlike SR flip-flop. Although JK flip-flop circuit is
an improvement on the clocked SR flip-flop it still suffers from timing
problems called "race". This problem can be solved by Master slave flip-
flop.

MS JK Flip Flop: The Master-slave JK flip-flop is basically two JK bitable

flip-flops connected together in a series configuration with the outputs
form Q and Q‟ from the slave flip-flop being fed back to the inputs of the
Master with the outputs of the Master flip-flop being connected to the two
inputs of the slave flip-flop. The circuit accepts input data when the clock
signal is “HIGH”, and passes the data to the output on the fallingedge of
the clock signal. In other words, the Master-Slave JK flip-flop is a
“Synchronous” device as it only passes data with the timing of the clock
signal. The master slave over comes the race around condition.

T - Flip Flop: MS JK FF is converted to T – FF by shorting J and K inputs.

The output of a T – FF changes every time it is triggered at its T – input
called Toggle input.
D - Flip Flop: MS JK FF is converted to D – FF by connecting J and K
inputs through a NOT gate. The data bit present on the d-input is

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transferred to the Q – output every time it is clocked.

PIN DETAILS OF 7410:

i)MASTER-SLAVE JK FLIP-FLOP:

 SYMBOL OF M S-JK FF

 TRUTH TABLE:

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REALIZATION OF MASTER SLAVE J K FLIP FLOP USING NAND

GATES:

Logic Diagram of Master Slave J K Flip – Flop Using NAND Gates

ii)MASTER-SLAVE D FLIP-FLOP:

 SYMBOL OF M S-D FF:

MS
D
FF

 TRUTH TABLE:

CLK D Q+ Comment
Q+

0 X Q No Change
Q

1 0 0 1 Reset

1 1 1 0 Set

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REALIZATION OF MASTER SLAVE D FLIP FLOP USING NAND GATES:

Logic Diagram of Master Slave D Flip – Flop Using NAND Gates

c) MASTER-SLAVE JK FLIP-FLOP:

 SYMBOL OF M S-T FF:

MS
T
FF

TRUTH TABLE:

CLK T Q+ Comment
Q+

0 X Q No Change
Q

1 0 Q No Change
Q

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1 1 Q Toggle
Q

REALIZATION OF MASTER SLAVE T FLIP FLOP USING NAND GATES:

Logic Diagram of Master Slave T Flip – Flop Using NAND Gates

Procedure:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

Result:Thus the truth table for Master Slave JK FF was verified, D and T
FF were realized using MS JK FF.

Viva Questions:

1. Distinguish between the combinational & sequential circuits.

2. What are the two types of sequential circuits?
3. What is a Flip-Flop & Distinguish between the flip-flop & Latch?

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4. A Flip-flops is a Divide By _____ Counter.

5. Can we use SR Flip-flops as a D Flip-flops?

7B. Realize the following shift registers using IC7474/IC 7495

(a) SISO (b) SIPO (c) PISO (d) PIPO (e) Ring and (f) Johnson
counter.

COMPONENTS REQUIRED:-
Sl.No NAME OF THE
COMPONENT IC NUMBER

7495
1 Shift register
2 Trainer kit
3 Patch Chords

THEORY:
A Shift register is a storage device that can be used for temporary storage
of binary data he basic building block in all shift registers is the flip-flop, mainly
a D-type flip-flop. Based on the method by which data can be loaded onto and
read from shift registers, they are classified. The IC 7495 is a 4-bit shift
registers, allowing
• Serial in serial out (SISO)
• Serial in parallel out (SIPO)
• Parallel in serial out (PISO)
• Parallel in parallel out (PIPO) above all four are shift right operation
and also can do Shift left operation.

PIN DIAGRAM OF IC 7495:

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 A, B, C and D : Parallel Data Inputs of shift

register
 QA, QB, QC and QD : Parallel Data Output of shift register
 Mode SER = Serial Data Input
 CK1: Loading Serial Input Data, for shift right.
 CK2: Loading Parallel Input Data, for shift left .
 M = Mode Control: 1/0
 (If M= 1, CK2 is enabled, M= 0, CK1 is enabled)

a)SERIAL IN SERIAL OUT (SISO):

The input applied is in serial form as and the Clk pulse is applied at the data
moves by one position for every single Clk Input and the output obtained is
in the serial form from the 4th pulse.

 LOGIC DIAGRAM OF SISO:

TRUTH TABLE FOR SISO:

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Procedure
1. Connections are made as per logic diagram.
2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data „d0‟ appears at QD.
4. Apply another clock pulse; the second data „d1‟ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data „d3‟ to appear at QD.
Thus the data applied serially at the input comes out serially at QD

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b) SERIAL IN PARALLEL OUT (SIPO):

Data is applied at the serial input and the output is obtained in the parallel
form after full data word has been shifted.

 LOGIC DIAGRAM OF SIPO:

 TRUTH TABLE FOR SIPO:

Procedure

1. Connections are made as per logic diagram.

2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to
QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the
shift register.

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c) PARALLEL IN SERIAL OUT (PISO):

Data is loaded in parallel and can be shifted out in serial form.

 LOGIC DIAGRAM OF P ISO:

 TRUTH TABLE FOR PISO

SERIAL

Procedure
1. Connections are made as per logic diagram.
2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at A, B, C
and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the data
coming out serially at QD.

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d) PARALLEL IN PARALLEL OUT (PIPO):

Data is loaded in parallel and read out in parallel form.

 LOGIC DIAGRAM OF PIPO:

 TRUTH TABLE FOR PIPO:

Procedure

1. Connections are made as per logic diagram.

2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

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e) RING COUNTER:
Ring counter is also called as shift register counter where the FF 1S are coupled as
in a shift register and the last FF is coupled back to the first ,which gives the array
of ff ‟ the shape of ring . Counting sequence of such counter will depend upon initial
state, the desired initial state should provided by parallel loading before counting
begin, loading can be done by placing a single „1‟ or single „0‟ for allowed counting
sequence. The logic „1‟ or „0‟ will advance by one flip-flop around the ring for each clk
pulse and return to original FF after exactly four clk pulses as there are 4FF , the
standard ring counter requires n FF‟s to derive a modulo (n+1) counter.
LOGIC DIAGRAM OF RING COUNTER:

 TRUTH TABLE FOR RING COUNTER:

PROCEDURE:
1. Connections are made as per the logic diagram.
2. Apply the data 1000 at A, B, C and D respectively.
3. Keeping the mode M = 1, apply one clock pulse.
4. Now the mode M is made 0 and clock pulses are applied one by one and the
truth table is verified.

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f) JOHNSON RING COUNTER:
Johnson counter is similar to ring counter that the complement of the output
of last stage is connected to the input of first stage therefore it is called as twisted
ring counter .it requires n/2 FF,s for a modulo n counter.

 LOGIC DIAGRAM OF JOHNSON RING COUNTER:

 TRUTH TABLE FOR JOHNSON RING COUNTER:

PROCEDURE:

1. Connections are made as per the logic diagram.

2. Apply the data 1000 at A, B, C and D respectively.
3. Keeping the mode M = 1, apply one clock pulse.
4. Now the mode M is made 0 and clock pulses are applied one by one and the
truth table is verified.

RESULT: All the outputs are verified with the truth table.

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Experiment No: 8
Realize (a) Design Mod-N Synchronous Up counter & Down Counter using
7476 JK flip-flop (b) Mod-N counter using IC7490/7476 (c) Synchronous
counter using IC74192
AIM:
1. To realize Mod-N Synchronous Up counter & Down Counter using 7476
JK flip-flop
2. To realize Mod-N counter using IC7490/7476
3. To realize Synchronous counter using IC74192

COMPONENTS REQUIRED:

Sl. No. Component Name Quantity

1. IC 7476,7490,74192,7408 Each 1
2. Patch cards few
3. IC Trainer Kit 1

(a) Design Mod-N Synchronous Up counter & Down Counter using 7476 JK flip-flop

THEORY:
Counters: counters are logical device or registers capable of counting
the no. of states or no. of clock pulses arriving at its clock input where
clock is a timing parameter arriving at regular intervals of time, so
counters can be also used to measure time & frequencies. They are
made up of flip flops. Where the pulse is counted to be made of it goes
up step by step & the o/p of counter in the flip flop is decoded to read
the count to its starting step after counting n pulse in case of module
counters.

Counters are of two types:

1) Asynchronous counter 2) Synchronous counter.
Asynchronous counter commonly called ripple counter, the first flip-
flop is clocked by the external clock pulse & then each successive flip-
flop is clocked by the Q or Q‟ output of the previous flip- flop.
Therefore, in an asynchronous counter the flip-flops are not clocked
simultaneously. When counter is clocked such that each flip flop in the

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counter is triggered external clock at the same time, the counter is
called as synchronous counter. Ex: - Ring counter & Johnson counter

Types of synchronous counter:

1) Up counter 2) Down counter.
Decision for number of flip-flops

Example: If we are designing mod N counter and m number of flip-flops

are required then m can be found out by this equation.
N <= 2m
Here we are designing Mod-7 counter Therefore, N= 7 and
number of Flip flops or bits (m) required is, for m =3, 7<=8,
which is TRUE.

3-bit Synchronous up counter:

The up-counter counts from 0 to7 (000 - 111) for this MS JK flip flop IC
74LS76 is used, 2 MS J-K flip flops are available. It is observed that the
AND gate inputs are fed by the non-complement outputs of FFA and
FFB. The clock pulse is given at pin 1 & 6 of the 1st IC & pin 1 of 2nd
IC, respectively to apply clock to all flip flop at a time.

3-bit Synchronous down counter:

This is used to count from 7 to 0 (111-000) for this also 2 IC‟s of
74LS76 are required & hence we use 3 MS JK flip flops. It is observed
that the AND gate inputs are fed by the complement outputs of FFA and
FFB. The clock pulse is given at pin 1 & 6 of the 1st IC & pin 1 of 2nd
IC, respectively to apply clock to all flip flop at a time.

UP COUNTER CIRCUIT DIAGRAM:

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OUTPUT WAVEFORMS:

DOWN COUNTER CIRCUIT DIAGRAM:

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PROCEDURE:
1. Connect the circuit as shown in the diagram.
2. Connect 𝑃𝑅𝐸 ¯¯¯¯¯¯ input to the logic 1 (+5V).
3. Connect 𝐶𝐿𝑅 ¯¯¯¯¯¯ input to the logic 0 (0V) or ground to reset counter.
4. Connect 𝐶𝐿𝑅 ¯¯¯¯¯¯ input to the logic 1.
5. Apply the clock pulse to CLK input.
6. Observe the output and verify the observation table.

(b) Mod-N counter using IC7490

 PIN DIAGRAM OF IC 7490:

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INTERNAL DIAGRAM OF IC 7490:

 Conditional Table:

R1 R2 S1 S2 Qa Qb Qc Qd
H H L X L L L L
H H X L L L L L
X L H H 1 0 0 1
L X L X MOD-2 COUNTER
X L X L MOD-5 COUNTER
L L L L MOD-10 COUNTER

LOGIC DIAGRAM OF MOD-8 COUNTER USING IC 7490 :

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 TRUTH TABLE:

 LOGIC DIAGRAM OF MOD-6 COUNTER USING IC 7490

 TRUTH TABLE:
CLOCK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 0 0 0
PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the logic diagram.
4. Verify the Truth Table and observe the outputs.

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(C) Synchronous Counter Using IC 74192

 PIN DIAGRAM OF IC 74192:

Note: Carry and borrow are mainly used for cascading the counters.
 FUNCTION TABLE:

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 LOGIC DIAGRAM OF IC 74192 AS PRE-SETTABLE UP COUNTER TO

COUNT FROM 5 TO 8 (Preset Value = 5 & N= 4) :

 TRUTH TABLE:

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 LOGIC DIAGRAM OF IC 74192 AS PRE-SETTABLE DOWN
COUNTER TO COUNT FROM 8 TO 5 (Preset Value = 8 & N= 4) :

TRUTH TABLE:

CLK QD QC QB QA
0 1 0 0 0
1 0 1 1 1
2 0 1 1 0
3 0 1 0 1
4 1 0 0 0

PROCEDURE:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the logic diagram.
4. Verify the truth Table and observe the outputs.

Result: Thus the modulo counter using IC 7490 & IC 74192 were designed,
constructed and verified.

Viva Questions:

1. Define MOD of a counter?

2. What is a difference between a Synchronous & Asynchronous Counters?
3. Name the IC‟s which are used as a Synchronous Counters?
4. Define Triggering in the Counters?

Dept. of ECE SJCIT 65

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Demonstration Experiments

Experiment No: 09
Design and test the second order Active Filters and plot the
frequency response,
i) Lowpass and Highpass Filter
ii) Bandpass and Bandstop Filter

Design active second order Butterworth low pass and high

pass filters

AIM:To design and obtain the frequency response of

i) Second order Low Pass Filter (LPF)
ii) Second order High Pass Filter (HPF)
iii) Second order Band Pass Filter(BPF)
iv) Second order Band Reject Filter(BRF)

Components required:
Sl.NO DESCRIPTION RANGE QUANTITY
1 IC 741 1
2 Resistors 10k ohm,5.86K 1
Ohm
16kΩ
1
3 Capacitors 0.01μf 1

THEORY:
LPF:
A LPF allows frequencies from 0 to higher cut of frequency, fH.
At fH the gain is 0.707 Amax, and after fHgain decreases at a
constant rate with an increase in frequency. The gain decreases
20dBeach time the frequency is increased by 10. Hence the rate at
which the gain rolls off after fHis 20dB/decade or 6 dB/ octave,
where octave signifies a twofold increase in frequency.The frequency
f=fHis called the cut off frequency because the gain of the filter at this
frequency is down by 3 dB from 0 Hz. Other equivalent terms for
cut-off frequency are -3dB frequency, break frequency, or corner
frequency.

Dept. of ECE SJCIT 66

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]
HPF:
The frequency at which the magnitude of the gain is 0.707 times
the maximum value of gain is called low cut off frequency. Obviously,
all frequencies higher than fL are pass band frequencies with the
highest frequency determined by the closed –loop band width all of
the op-amp.

Circuit Diagram: Second Order Active Butterworth Low Pass Filter

Design:
Choose a Cut-off frequencyfc=1 kHz
Choose C=C1=C2=0.01µfHence R=R2=R3=16KΩ
Assume pass band gain Av=1.586,
Choose R1=10K Ω. Hence Rf=5.86 kΩ

Tabular Column:Input voltage=Vin= ..... Vp-p

Frequency in Output Vo
Hz voltage
V
(f) in Volts(Vo) Gain in dB= 20 log i
n
100
200

10K

Dept. of ECE SJCIT 67

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Circuit Diagram: Second Order Butterworth HighPass Filter

Design : choose a Cutoff frequency fc=10kHz

choose C=C1=C2=0.01µf HenceR=R2=R3=1.6KΩ Assume pass band gain

Av=1.586,

Choose R1=10K Ω. Hence Rf=5.86 kΩ

Tabular Column:Input voltage=Vin= Vp-p

Frequency in Hz Output voltage Vo
V
(f) in Volts(Vo) Gain in dB= 20 log in
100
200

10K

Model graphs:

Frequency response characteristicsofLPF Frequency response characteristics

ofHPF

Dept. of ECE SJCIT 68

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

SECOND ORDER ACTIVE BAND PASS FILTER

Aim: Design a second order active Band pass filter for the given cut-off
frequencies
fc1=1 kHz and fc2=6 kHz and to verify the bandwidth.
Components Required:
OPAMP µA741 02
Capacitors 0.01µf 02
Resistors 5.86kΩ 02
10kΩ 02
2.65kΩ 02
15.9kΩ 02
Connecting wires ------- 20
Connecting Board ------- 01
CRO Probes ------- 02
Theory: A band pass filter is basically a frequency selector. It allows one
particular band of frequencies to pass and attenuates frequency outside this
band. There are two types band pass filters which are classified based on the
Quality factor (Q). If Q < 10 such filters are called wide band filters and if Q >
10 such filters are called narrow band filters.
Procedure:
1. Before wiring the circuit, check all the components using millimetre and
IC tester.
2. Connect the circuit as shown in circuit diagram.
3. Set the signal generator amplitude say 1V peak to peak (1 kHz) and apply
this voltage at input of the filter circuit.
4. Vary the frequency of the input signal from 100Hz to 100 kHz and note
down the corresponding output voltage from the CRO.
5. Tabulate the readings in a tabular column and calculate the in dB.
6. Plot the graph with frequency along X-axis and gain of dB along Y-axis.
7. Calculate the cut-off frequencies fc1 and fc2 (fc2>fc1), the difference
between these two cut-off frequencies is called bandwidth.
8. Also find the Quality factor Q = , where fc = √ .

Dept. of ECE SJCIT 69

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Circuit Diagram:

Design: Choose a lower cut-off frequency fc1=1 kHz.

fc1 = , Choose C1=C2=0.01µf => R2= R3= 15.9kΩ.
√
Choose a higher cut-off frequency fc2=6 kHz.
fc2 = , Choose C3=C4=0.01µf => R4= R5= 2.65kΩ
√
Assume pass band gain Av= 1.586. Av= 1+ , Choose R1=10kΩ => Rf =5.86kΩ

Tabular Column: Input Voltage = 1Vp-p

Frequency in Output Gain in dB = 20
Hz Voltage in
volts
100
200
....
....
1k
2k
....
100k

Dept. of ECE SJCIT 70

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Result: The second order band pass filter is designed and verified.
Theoretical value of bandwidth= 5 kHz.
Theoretical value of Quality factor =0.04453
Practical value of bandwidth = ________ kHz.
Practical value of Quality factor = _________

SECOND ORDER ACTIVE BAND REJECT FILTER

Aim: Design a second order active Band reject filter for the given cut-off
frequencies fc1=5
kHz and fc2=9 kHz and to verify the bandwidth.
Components Required:
OPAMP µA741 02
Capacitors 0.01µf 02
Resistors 5.86kΩ 02
10kΩ 05
3.3kΩ 03
1.8kΩ 02
Connecting wires ------- 20
Connecting Board ------- 01
CRO Probes ------- 02
Theory: Band stop filters are also called as Band Elimination filters. Band
elimination filters perform in an exactly opposite way compared to Band pass
filters. That is, band elimination filters reject a specified band of frequencies
while passing all frequencies outside the band.
Procedure:
1. Before wiring the circuit, check all the components using millimetre and
IC tester.
2. Connect the circuit as shown in circuit diagram.
3. Set the signal generator amplitude say 1V peak to peak(1 kHz) and apply
this voltage at input of the filter circuit.
4. Vary the frequency of the input signal from 100Hz to 100 kHz and note
down the corresponding output voltage from the CRO.
5. Tabulate the readings in a tabular column and calculate the in dB.
6. Plot the graph with frequency along X-axis and gain of dB along Y-axis.
7. Calculate the cut-off frequencies fc1 and fc2(fc2>fc1), the difference
between these two cut-off frequencies is called bandwidth.
8. Also find the Quality factor Q = , where fc=√ .

Dept. of ECE SJCIT 71

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Circuit Diagram:

Design:
Choose a higher cut-off frequency fc2=9 kHz.
fc2 = , Choose C1=C2=0.01µf => R2= R3= 1.76kΩ. Choose R4= R5==
√
1.8kΩ.
Choose a lower cut-off frequency fc1=5 kHz.
fc1 = , Choose C3=C4=0.01µf => R4= R5= 3.18kΩ, Choose R2= R3=
√
3.3kΩ
Assume pass band gain Av= 1.586. Av= 1+
Choose R1=R6=10kΩ => Rf =5.86kΩ
Summer: Choose all values of R= 10kΩ.

Dept. of ECE SJCIT 72

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]
Tabular Column: Input Voltage = 1Vp-p
Frequency in Output Gain in dB = 20
Hz Voltage in
volts
100
200
10k
20k
....
....
100k

Result: The second order band stop filter is designed and verified.
Theoretical value of bandwidth= 4 kHz.
Theoretical value of Quality factor = 1.677.
Practical value of bandwidth = _______ kHz.
Practical value of Quality factor = ______

Dept. of ECE SJCIT 73

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Experiment No: 10
Design and test the following using 555 timer
iii) Monostable Multivibrator
iv) Astable Multivibrator

AIM: To design/build monostable multivibrators using 555 IC and verify their

operation using measurements by observing waveforms.
APPARATUS:
Analog board of AB28.
DC power supplies + 5V, from external source or ST2612 Analog Lab.
2 mm patch cords.
Ohm meter.
Function generator
THEORY: Basically, 555 timers is a highly stable circuit capable of functioning
as an accurate time-delay generator and as a free running multivibrator. The
555 timer is highly stable device for generating accurate time delay or
oscillation. The device consists of two comparators that drive the set (S) and
reset (R) terminals of a flip-flop, which in turn controls the 'on' and 'off cycles of
the discharge transistor Q1. The comparator reference voltages are fixed at 2/3
Vcc for comparator C1 and Vcc/3 for comparator C2 by means of the voltage
divider made up of three series resistors (R). These reference voltages are
required to control the timing. The timing can be controlled externally by
applying voltage to the control voltage terminal
Circuit diagram:

IC 555 as Monostable multivibrator Functional Diagram

Dept. of ECE SJCIT 74

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

IC 555 as Monostable multivibrator with internal structure diagram.

Design: t = 1.1*R*C seconds…

expected waveforms:

Dept. of ECE SJCIT 75

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]
Procedure:
1) Connect power supply + 5V from ST2612 or any external source.
2) Connect point a to point b using a 2mm patch cord.
3) Connect point c to point d/e using a 2mm patch cord.
4) Keep the pot (R2 1M) to fully anticlockwise direction.
5) Apply a pulse signal of 5Vpp and 1 KHz (keep duty cycle of pulse 50%) at pin
2 of IC 555 i.e. to the point e/g on AB28 board. Observe the same on
oscilloscope CHI.
6) Connect pin 3 of IC55 i.e. output socket to the oscilloscope CHII.
7) Vary the pot and observe the variation of output pulse duty cycle with the
change in resistance R (where, R=R1+R2).
8) For any value of R measure the ON time of output pulse.
9) Calculate the same by following equation for theoretically calculating the
output pulse „On‟ time. TP = 1.1 * R1C1 Note : For calculating the value of R,
disconnect the +5V supply and connection between point a and b. Connect
ohmmeter between point a and TP1. The ohmmeter will read the value of R.
10) Verify theoretical and practical values of TP. Note : The two values of TP
(theoretical and practical values) will match only for time for which input pulse
is High i.e. only for „On‟ 'time of input pulse. To verify this vary the duty cycle of
input signal and check the output pulse duty cycle by varying R (R=R1+R2).
11) Repeat above procedure for different values of R.
OBSERVATION TABLE:

Sr. No. R C Tp Theoritical Tp Practical

CONCLUSION:

Dept. of ECE SJCIT 76

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]
ASTABLE MULTIVIBRATOR
AIM: To design an Astable Multivibrator using IC555 and compare it‟s
theoretical and practical time period and duty cycle.
APPARATUS:

Bread Board

CRO Probes

Connecting wires

555 Timer

Resistors

Capacitors

THEORY: An Astable multivibrator, often called a free-running Multivibrator, is

a rectangular-wavegenerating circuit. Unlike the Monostable multivibrator, this
circuit does not require an external trigger to change the state of the output,
hence the name free running. However, the time during which the output is
either high or low is determinate by the Two resistors and a capacitor, which
are externally connected to the 555 timer. Figure 1 shows the 555 timer
connected as an Astable multivibrator. Initially, when the output is high,
capacitor C starts charging towards Vcc through RA and RB. However as soon
as voltage across the capacitor equals 2/3 Vcc, comparator 1 triggers the flip-
flop, and the output switches low. Now the capacitor C starts discharging
through RB and the transistor Q 1. When the voltage across C equals 1/3 Vcc,
comparator 2‟s output triggers the flip-flop, and the output goes high. Then the
cycle repeats. The output voltage and the capacitor voltage waveforms are
shown in the following figures. As shown in this figure, the capacitor is
periodically charged and discharged between 2/3 Vcc and 1/3 Vcc,
respectively. The time during which the capacitor charges from 1/3 Vcc to 2/3
Vcc is equal to the time the output is high and is given by
Tc = 0.69 (RA + RB) C
Similarly, the time during which the capacitor discharges from 2/3 Vcc to 1/3
Vcc is equal to the time the output is low and is given by
Td = 0.69 (RB)C
Thus the total time period of the waveform is
T = Tc + Td = 0.69(RA + 2RB)
Therefore the frequency of oscillation is fo = 1/T = 1.45/(RA + 2RB)C and
% Duty Cycle = (Tc/T) *100

Dept. of ECE SJCIT 77

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

PROCEDURE:
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Connect channel-1 of CRO to the output (Pin 3).
4. Observe the output voltage and note down the time period and duty cycle.
5. Now connect channel-2 of CRO across capacitor and observe the voltage
across the capacitor and note it down.
6. Compare the practical time period and duty cycle.

Dept. of ECE SJCIT 78

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]
CALCULATIONS:
THEORETICAL
Time Periods Tc = 0.69 (RA + RB) C
Td = 0.69 (RB)C
Total Time Period Of The Waveform, T = Tc + Td
% Duty Cycle = (Tc / T) *100
PRACTICAL
(From Output Waveforms) Time Period, T =
% Duty Cycle =

RESULT:

Dept. of ECE SJCIT 79

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Experiment No: 11
Design and test a Regulated Power Supply

AIM: Design a Regulated Power Supply

Components Required:

Sl.NO DESCRIPTION RANGE QUANTITY

1 Diode 1N4007 4
2 Transformer 12-0-12 1
3 LM7812 - 1
1000uF 1
4 Capacitor
1uF 1

Circuit Diagram:

Result : The Regulated Power Supply is designed and tested.

Dept. of ECE SJCIT 80

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

Experiment No: 12
Design and test an audio amplifier by connecting a microphone input
and observe the output using a loud speaker

AIM: Design and test an audio amplifier by connecting a microphone

input and observe the output using a loud speaker.
OBJECTIVES:

1. To understand the working of microphone

2. To understand the response of audio amplifiers

COMPONENTS REQUIRED:
1. LM386
2. 10uF /
16V
capacitor
3. 470uF
/ 16V
4. 0.047uF / 16V Polystar Flim Capacitor
5. 10R ¼ Watt
6. 12V Power Supply unit
7. 8 Ohms / .5 Watt Speaker
8. Capsule or Electret Microphone
9. 0.1uF capacitor
10. 10k 1/4th Watt Resistor
11. Bread Board
12. Hook up wires

CIRCUIT DIAGRAM

Dept. of ECE SJCIT 81

 ANALOG & DIGITAL SYSTEMS DESIGN LAB [BECL305]

THEORY:
In the circuit diagram, the Amplifier is shown with the respective pin
diagrams. The amplifier will provide 200 x gains at output depending
on the input. The 10uF capacitor across pin 1 and pin 8 is responsible
for the 200x gain of the amplifier. We did not change the gain of the
amplifier in our circuit construction. Also, the 250uF capacitor is
connected across the Speaker. We have changed the value and used
470uF instead of 250uF capacitor. There is a 0.05uF capacitor along
with a 10R resistor. This RC combination is called snubber or clamp
circuit which protects the amplifier from back EMF, produced by the
speaker. We used a common but close value of 0.047uF instead of
0.05uF. Other circuitry and connections remain the same in our
construction.

Also, the power amplifier can drive a wide range of loads, from 4 Ohms
to 32 Ohms and can be powered using 5V to 12V. We need to be
careful about this rating otherwise we could damage the power
amplifier or the output speaker.

PROCEDURE:
1. Rig up the circuit as per the given circuit diagram.
2. Switch on the D.C. power supply
3. Provide voice input.
4. Observe the amplified voice output.

RESULT: Design and test an audio amplifier by connecting a

microphone input and observe the output using a loud speaker is
Verified.

Dept. of ECE SJCIT 82