IJSRD - International Journal for Scientific Research & Development| Vol.

5, Issue 05, 2017 | ISSN (online): 2321-0613

Implementation of Direct Digital Synthesizer using Cordic Processor

Ms. Madhu Priyanka1 Asst. Prof. Shree Prasad2
1
Student (VLSI and Embedded System) 2Assistant Professor
1,2
Department of Electronics & Communication Engineering
1,2
PESIT, Bengaluru India
Abstract— This paper presents the Design and The operation can be anticipated more easily by
Implementation of Direct Digital Synthesizer using Rotation analyzing at the way that phases moves step by step over the
mode Pipelined CORDIC (CO-ordinate Rotation Digital course of one cycle of the waveform. This can be visualized
Computer) algorithm. Direct Digital Synthesizer (DDS) is as the phase progressing around a circle [6]. As the
heart of many Digital Communication Systems such as phase advances around the circle, this corresponds to
Digital Radio and Modems, modulators, mixers, sound advances in the waveform.
synthesizers, Digital Down/Up converters etc. The algorithm
used in this paper uses dynamic transformation instead of
ROM static addressing which reduces area requirement and
improves the performance. The pipelined architecture enables
us to calculate continuous input with high throughput. In this
paper, DDS design is designed using verified Verilog HDL
and then stimulated and optimized using Questasim 10.1. The
Verilog code is then synthesized using Xilinx 12.1 for
hardware realization. The power report for the design is Fig. 2: Operation of phase accumulator in DDS
generated using Cadence tool The Designs are verified on After the phase is determined it is important to
Xilinx Spartan6 FPGA Development Platform. convert phase into a digital representation of the waveform.
Key words: CORDIC, Direct Digital Synthesizer, FPGA, This is performed using a waveform map. Waveform map is
Verilog a memory which stores a number analogous to the voltage
required for every value of phase on the waveform. In this
I. INTRODUCTION type of synthesizer, it behaves as a sine look up table for the
The Coordinate Rotation Digital Computer (CORDIC) requirement of sine wave. In most of the cases, the memory
algorithm was developed by J.E. Volder [1] in 1959. It is is either a ROM (read only memory) or PROM
commonly used when no hardware multiplier is available (programmable read only memory). This memory contains a
(e.g. in simple microcontrollers and FPGAs) as it requires huge number of points on the waveform, much more than that
only few operations such as addition, subtraction, bit shift and are accessed every cycle. A very large number of points are
table lookup. It is being used in applications such as digital needed in order to increment the phase accumulator by a
signal processing, graphics, image processing, and kinematic certain number of points to set the required frequency.
processing. The advances in the VLSI technology have A Direct Digital Synthesizer produces a sinusoidal
extended the application of CORDIC algorithm recently in wave at a given frequency. This frequency relies on three
biomedical signal processing, neural networks and wireless factors; the reference-clock frequency fclk and the binary
communications. number loaded into the phase register (frequency control
Direct digital synthesis (DDS) is a strong technique word, M), length of n-bit accumulator. The binary number
used in generating radio frequency (RF) signals for wide present in the phase register generates the main input to the
application such as signals generators, radio receivers, and phase accumulator [7].
many more. This technique has become highly popular in To generate a fixed-frequency sinusoidal wave, a
recent years with the evolution in VLSI technology that constant value phase increment that is decided by the M
requires very high speeds to be handled which further needs (binary number) is added to the phase accumulator with every
incorporation of high frequency DDS chips to be clock cycle. Phase accumulator depends on phase increment.
manufactured [2]. A direct digital synthesizer functions by If the phase increment is more, the phase accumulator will
storing the points of a waveform in digital representation, and step rapidly and instantly generate a high frequency sine
then using them to generate the waveform. The basic block wave. On the contrary, when the phase increment is less, the
diagram is shown in Fig 1, but before analyzing the operation phase accumulator will consume many more steps as well as
of the direct digital synthesizer it is important to understand time, therefore leading to a slower waveform. M is the digital
the basic concept behind the system. word in the phase register which represents the amount by
which the phase accumulator is incremented each clock cycle.
With fclk as the clock frequency, the frequency of the output
sine wave is equal to:
fout= M*fclk/2n (1)
This equation is called as the DDS "tuning
equation." The frequency resolution of the system is given by
fclk/2ⁿ. In a general practical Direct Digital Synthesizer, all
Fig. 1: Block Diagram of basic DDS the bits coming out of the phase accumulator are not passed
on to the Look up table, but are truncated, leaving only the

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 Implementation of Direct Digital Synthesizer using Cordic Processor
(IJSRD/Vol. 5/Issue 05/2017/266)

π π
first 13 to 15 MSBs. This leads to reduction of size of the 001 <2πϕ< 0 0 1 sin cos
2 4
Look up table and hence, frequency resolution is not affected π 3π
[5]. 010 <2πϕ< 0 1 1 -sin sin
2 4
3π
011 <2πϕ<π 1 0 0 -cos sin
4
II. OVERVIEW OF DIRECT DIGITAL SYNTHESIZER 3π
100 -π<2πϕ< 1 1 0 -cos -sin
Here, the detailed optimization and analysis of architecture of 4
−3π
DDS along with its performance is explained [18]. The <2πϕ<
101 2 1 1 1 -sin -cos
−π
combination of DDS with CORDIC has many advantages
2
associated with it like high data rate, high precision etc. The −π −π
implemented DDS architecture consists of radian converter, 110 <2πϕ< 1 0 1 sin -cos
2 4
−π
phase accumulator, sine and cosine generator, output stage. 111 <2πϕ<0 0 1 0 cos -sin
4
A. Phase Accumulator Table 1: control signals for quadrant used by output stage
Figure 2 represents a phase accumulator having a n- bit adder C. Sine/Cosine Generator
for accumulating the phase angle value by frequency control Here, the sine/cosine generator do mapping from phase to
word recursively. We can define the phase accumulator amplitude in sinusoidal waves format. For example, the
output at time = t as, output resolution of 16 bits, the sine/cosine generator
ϕ = (t · FCW)/2n (2) generates output sinusoidal waves by performing cordic
The sine and cosine generator provides: computation which can be given as:
Sin ((t · FCW)/2n) (3) i
x i  1  K i .[ x i  y i .d i . 2 ]
And i
y i  1  K i .[ y i  x i .d i . 2 ]
Cos ((t · FCW)/2n) (4) (5)
Frequency control word is loaded into register by
using load control signal. The phase accumulator content is
initialized to zero by using reset signal.

Fig. 3: Block diagram of Phase accumulator

B. Radian Converter
For converting phase accumulator output into binary
representation (in radians), few steps has to be considered. In Fig. 5: CORDIC processor
these steps, first two most significant bits (MSBs) depicts the
D. Output Stage
quadrant of angle and the third most significant bit (MSB)
shows half portion of the quadrant. Therefore, the starting Here, mapping of calculated sin θ and cos θ to required sin ϕ
three most significant bit (MSBs) of the phase are used to and cos ϕ is performed. This mapping is achieved by simple
regulate the negation and interchange operation in the output interchange and negation operations as explained above [10].
stage. It is explained in figure, the angles of ϕ in the 2nd, 3rd, As shown below in figure 6, control signals xinv, yinv and swap
4th quadrants can be easily mapped to the 1st quadrant by are obtained from MSBs of phase ϕ depicted in Table 1. Here,
keeping the MSBs to zero (00). Further radian conversion is swap performs interchange operation and negation is
required in which ϕ’ is  = (π/4) ϕ. This radian conversion performed by xinv, yinv.
can be done using simple adders and shifters [18].

Fig. 4: Shows symmetry based mapping of phase (angle) in Fig. 6: Output stage
first quadrant
MSB xin yin swa cos2π sin2π E. Proposed DDS Architecture
ϕ
s of ϕ v v p ϕ ϕ Hence, using above basics block the proposed architecture of
π direct digital synthesizer is given by,
000 0<2πϕ< 0 0 0 cos sin
4

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 Implementation of Direct Digital Synthesizer using Cordic Processor
(IJSRD/Vol. 5/Issue 05/2017/266)

This matrix operation can be expressed by

mathematical operations as follows
(7)
(8)
Rearrange as

(9)

Fig. 6: Proposed DDS architecture (10)

Two components:
III. INTRODUCTION TO CORDIC ALGORITHM 1) cos (): Reduces the magnitude of the vector.
Cordic is known as Coordinate Rotation Digital Computer 2) tan (): Rotates the vector and break  into a series of
introduced by Jack E. Volder [1]. It is an iterative algorithm shrinking angles ai such that:
which is capable of calculating trigonometric, logarithmic, tan (ai) =2-i (11)
and exponential and various other functions. In this algorithm Rewrite in terms of ai: (0  i  n)
we use an adder or subtractor, a shifter and a small look up
table to calculate the trigonometric functions. The major
advantage of Cordic algorithm over other algorithms is that it (12)
does not need division or multiplication blocks, instead it It can be again rewritten as:
operates only with a shifter, adder/subtractor and a small
lookup table which reduces the area requirement. Moreover,
(13)
this decreases the hardware requirement drastically and
Where,
provides a satisfactory good speed.
The major constraint in System on chip design is the (14)
amount of on chip memory and this particular constraint is
(15)
equally valid in System on chip prototype using
Let the multiplications aggregate to:
programmable logic. Hence using Cordic Algorithm we can
minimize the memory requirements [8].
A. Mathematical equations for Cordic Algorithm (16)
There are two methods of representing a Cordic Algorithm.
Vectoring and Rotation mode. In vectoring mode, the Multiplication with K can be avoided by considering
coordinates (x0, y0) are rotated until y0 converges to zero. In it as a multiplication factor for all the iterations. Therefore,
the rotation mode the coordinates (x0, y0) are initially aligned for n iterations K is given by the product of each i.
with the x- axis and they are rotated by an angle of θi every To simplify the hardware:
cycle until it reaches the target angle or close to the target First rotate by , then rotate by –di.ai to get 0
angle [3]. Algorithm: (z is the current angle)
For the Architecture proposed we have used the  Mode: rotation: “at each step, try to make z zero”
rotation mode for mapping phase to amplitude values.  Initialize x=0.607253,y=0,z=
Suppose that we have a point on a unit circle then by Fig 7.  For i=0 n
We can conclude that the coordinates can be given by (cosθ,  di = 1 when z>0, else -1
sinθ) where θ is the angle made by the line joining the point  xi+1= xi – di . 2-i. yi
and the center with the x-axis.  yi+1 = yi + di . 2-i. xi
 zi+1 = zi – di . ai
 Result: xn=cos(), yn=sin()
 Precision: n bits (tan-1(2-i)  2-i)
Therefore we can rewrite the equation as,
i
x i  1  K i .[ x i  y i .d i . 2 ]
i
y i  1  K i .[ y i  x i .d i . 2 ]
(17)

Fig. 7: A point on unit circle rotated by an angle θ IV. PIPELINED ARCHITECTURE

Therefore, the angle for which we want to know the Efficiency of Pipelined cordic architecture is very good and
sine and cosine value can be obtained by simply rotating the it provides a very fast result [4]. The main advantage of
point to the target angle. The rotation can be in a single step pipelined architecture is minimization of critical path.
or series of small steps which can be either clock wise or Pipelined CORDIC circuits have been mainly used for high-
anticlockwise. The rotation of a point in 2-dimensional space throughput implementation of fixed and adaptive filters,
can be given as: sinusoidal wave generation, discrete orthogonal transforms
and many signal processing applications. The pipelined
(6) architecture is shown in Fig 8. This architecture consists of n

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 Implementation of Direct Digital Synthesizer using Cordic Processor
(IJSRD/Vol. 5/Issue 05/2017/266)

stages of CORDIC units in which each of the pipelined stages The output of the top module confirms the correct
consists of a basic CORDIC mechanism as explained in Fig. phase increment of the phase accumulation step. The output
8. The number of shifts to be done by the shifters at different frequency (fout) is as obtained as 2 MHZ. In the proposed
stages is fixed in case of pipelined CORDIC. The shift design, the amplitude of output is represented using 16 bits.
operations could be hardwired with adders and therefore Therefore, the amplitude quantization level is 2 15 since the
shifters are eliminated in the pipelined implementation. The MSB (most significant bit) represents the sign of the
critical path of pipelined CORDIC therefore amounts to the amplitude
time required by add or subtract operations in each of the The design in coded in Verilog HDL and stimulated
stages. in Questasim 10.0c.The output obtained matches the
theoretical value.

Fig. 11: Simulation result of DDS

The design of CORDIC algorithm is simulated
separately. The 32 bit angle is given as input and 16 bit output
of each sine and cosine amplitude is obtained after 16
iterations. The simulated result is checked and verified with
theoretical value.
Fig. 8: Pipelined Cordic architecture

V. IMPLEMENTATION AND RESULT

As explained above, the architecture of design is pipelined
which perform mapping of phase into amplitude with very
high efficiency. The clock frequency (fclk) is taken as 50
MHZ. The phase accumulator has a size of 18 bits, in which
the MSB (most significant bit) signifies the sign of the input.
The output of phase accumulator is passed to mapped Fig. 12: Simulation result of cordic algorithm
CORDIC block, which further performs a mapping CORDIC fixed point sine/cosine value is compared
mechanism that maps the pipelined CORDIC over the whole with theoretical value in MATLAB and a graph is plotted for
2π range. 12 iterations with red line signifying the error value.

Fig. 9: RTL view

Fig 9 shows RTL view of DDS implementation
based on cordic algorithm.
The cadence tool is used to generate power, timing Fig. 13: Error graph of CORDIC sine
report. The RTL of top module of our design for ASIC
implementation is also generated using cadence tool.

Fig. 14: Error graph of CORDIC cosine

Fig. 10: RTL of design using cadence for ASIC

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 Implementation of Direct Digital Synthesizer using Cordic Processor
(IJSRD/Vol. 5/Issue 05/2017/266)

The Verilog code is synthesized using XILINX 12.1 [7] Wenmiao Song, Qiongqiong Yao, “Design and
and the design is tested using device XC3S200–FT256 with Implement of QPSK Modem Based on FPGA”, North
speed grade: -4 of Spartan 6 family. Table I shows the china Electric power University,Baoding, china IEEE,
hardware utilization of the proposed design when 2010.
implemented on Xilinx FPGA. [8] CORDIC, http://en.wikipedia.org/wiki/CORDIC,
Logic utilization Used Available Utilization accessed on April 2015.
Number of slice [9] Verilog, http://en.wikipedia.org/wiki/Verilog, accessed
841 17,344 4% on April 2015.
Flip- Flops
Number of 4 [10] “Optimization and implementation of scaling free
1,710 17,344 9% CORDIC-based Direct Digital Frequency Synthesizer
input LUTs
Number of for Body Care Area Network” Systems,Ying-Shen
951 951 100% Juang,1 Lu-Ting Ko,2 Jwu-E. Chen,2 Tze-Yun Sung,3
occupied Slices
Total Number of and Hsi-Chin Hsin4
1,751 17,344 10%
4 input LUTs
Table 1: Device utilization summary of design

VI. CONCLUSION
This paper presents a design of direct digital synthesizer
(DDS), also known as numerically controlled oscillator
(NCO).The implemented design is designed based on
pipelined CORDIC architecture used for phase to amplitude
mapping.
Moreover, the proposed design produces high
throughput which have better efficiency thus making the
design more useful for most of the communication systems.
Hence, the technique of generating frequencies digitally
using DDS provides more accuracy & phase continuation for
modern communication.
The paper focuses on combining the concept of DDS
& CORDIC algorithm and therefore provides the simulation
in Verilog using concept of the CORDIC algorithm.
CORDIC algorithm reduces the area utilization
when compared with other techniques like Look up table,
Taylor Series. The simple design of DDS in combination with
pipelined CORDIC is always is better choice as
implementing this in circuits such as receivers, digital
converters is lesser complex in terms of hardware utilization.
The higher width of phase accumulator data reduces the phase
quantization error. Thus, the accuracy of the output waveform
in respect of amplitude is improved.

REFERENCES
[1] J. E. Volder, “The CORDIC trigonometric computing
technique, “IRE Trans. Electron. Comput., vol. EC – 8,
pp. 330 – 334, Sep.
[2] A. L. Bramble, “Direct digital frequency
synthesis,”Proc.35th Annu Preq. Contr. Symp.,
USERACOM (Ft. Monmouth, NJ),pp 406 – 414, May
1981.
[3] J. S. Walther, “A Unified Algorithm for Elementary
Functions,” Proc. Joint Spring Comput. Conf., vol. 38,
pp. 379 – 385, Jul. 1971.
[4] Ray Andraka, "A survey of CORDIC algorithms for
FPGA based computers," FPGA '98, in ACM/ SIGDA
International Symposium on Field Programmable Gate
Arrays, pp 191- 200 (1998).
[5] A Technical Tutorial and specification on Digital Signal
Synthesis by Analog devices.
[6] Intel “Introduction to direct digital synthesis” technical
staff, March 1990, revised June 1991.

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