TPS92642-Q1

SLUSE50 – NOVEMBER 2023

TPS92642-Q1 Automotive Synchronous Buck Infrared LED Driver

1 Features by setting the IADJ voltage. PWM dimming of
LED current is achieved by directly modulating the
• AEC-Q100 qualified for automotive applications
UDIM input pin with desired duty cycle. The device
– Grade 1: –40°C to 125°C ambient operating
incorporates an internal pulse monitoring circuit that
temperature
limits the maximum pulse duty cycle.
– Device HBM classification level H1C
– Device CDM classification level C5 The TPS92642-Q1 incorporates advanced diagnostic
• Functional Safety-Capable and fault protection featuring: cycle-by-cycle switch
– Documentation available to aid functional safety current limit, bootstrap undervoltage, LED open, LED
system design short and thermal shutdown.
• Input voltage range: 5.5 V to 36 V The TPS92642-Q1 is available in a 6.6-mm × 5.1-mm
– Operation down to 5.15 V after start-up thermally-enhanced 16-pin HTSSOP package with
• Up to 5-A pulsed output current with 4% accuracy 0.65-mm lead pitch.
• Adaptive on-time current control
Device Information
– Low offset high-side current sense amplifier (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– Stable with any combination of ceramic, and
aluminum capacitors TPS92642-Q1 HTSSOP (16) 6.60 mm × 5.10 mm
• Programmable switching frequency from 100 kHz (1) For all available packages, see the orderable addendum at
to 2.2 MHz the end of the data sheet.
• Advanced dimming operation RCS
– 1000:1 precision PWM dimming L
LED+
– 15:1 precision analog dimming COUT
1 SW PGND 16
• Internal maximum duty cycle limit GND
2 SW
• Cycle-by-cycle switch overcurrent protection CIN1
• Open-drain fault indicator output CBST RBST VIN 15
3 BST VIN
– LED short circuit, open circuit and cable CVCC VIN 14
4 VCC
harness fault indication RON RUV2 RUV1
5 IADJ
• Thermal shutdown protection CCOMP
RON 13
6 COMP UDIM 12
2 Applications 7 AGND CSP 11 PWM
CSN 10
• Driver Monitoring Systems (DMS) CPLMT
8 PLMT FLT 9
• IR LED and laser driver
3 Description
Typical Buck LED Driver Application Schematic
The TPS92642-Q1 is a monolithic, synchronous Buck
LED driver with a wide 5.5-V to 36-V operating
input voltage range and 40-V tolerance that supports
load dump for duration of 400 ms. The TPS92642-
Q1 implements an adaptive on-time average current
mode control based on inductor valley current
detection. The adaptive on-time control provides
near constant switching frequency that can be set
between 100 kHz and 2.2 MHz. Inductor current
sensing and closed-loop feedback enables better than
±4% accuracy over wide input, output and ambient
temperature.
The high-performance infrared LED driver can LED Pulse Limit
independently modulate LED current using both
analog or PWM dimming techniques. Linear analog Ch1: UDIM input Ch2: PLMT voltage Ch4: LED current
dimming range with over 15:1 range is obtained

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.4 Device Functional Modes..........................................25
2 Applications..................................................................... 1 7 Application and Implementation.................................. 26
3 Description.......................................................................1 7.1 Application Information............................................. 26
4 Pin Configuration and Functions...................................3 7.2 Typical Application.................................................... 31
5 Specifications.................................................................. 4 7.3 Power Supply Recommendations.............................35
5.1 Absolute Maximum Ratings........................................ 4 7.4 Layout....................................................................... 35
5.2 ESD Ratings............................................................... 4 8 Device and Documentation Support............................37
5.3 Recommended Operating Conditions.........................5 8.1 Receiving Notification of Documentation Updates....37
5.4 Thermal Information....................................................5 8.2 Support Resources................................................... 37
5.5 Electrical Characteristics.............................................6 8.3 Trademarks............................................................... 37
5.6 Typical Characteristics................................................ 8 8.4 Electrostatic Discharge Caution................................37
6 Detailed Description......................................................10 8.5 Glossary....................................................................37
6.1 Overview................................................................... 10 9 Revision History............................................................ 37
6.2 Functional Block Diagram......................................... 11 10 Mechanical, Packaging, and Orderable
6.3 Feature Description...................................................12 Information.................................................................... 38

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4 Pin Configuration and Functions

SW 1 16 PGND
SW 2 15 VIN
BST 3 14 VIN
VCC 4 13 RON
IADJ 5 12 UDIM
COMP 6 11 CSP
AGND 7 10 CSN
PLMT 8 9 FLT

Figure 4-1. PWP Package, 16-Pin HTSSOP with PowerPAD, Top View

Table 4-1. Pin Functions

PIN
I/O DESCRIPTION
NO. NAME
Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground,
7 AGND —
GND, to complete return path.
Supply input for high-side MOSFET gate drive circuit. Connect a ceramic capacitor between BST and
3 BST I
SW pins. An internal diode is connected between VCC and BST pins.
Output of internal transconductance error amplifier. Connect an integral compensation network to
6 COMP O
ensure stability.
Negative input (–) of internal rail-to-rail transconductance error amplifier. Connect directly to the
10 CSN I
negative node of the LED current sense resistor, RCS.
Positive input (+) of internal rail-to-rail transconductance error amplifier. Connect directly to the positive
11 CSP I
node of the LED current sense resistor, RCS.
9 FLT O Open-drain fault indicator. Connect to VCC with a resistor to create an active low fault signal output.
Analog adjust input. Input below 100 mV disables the output. The analog input can be varied between
5 IADJ I 140 mV to 2.4 V to set current reference from 10 mV to 175 mV. Connect a 0.1-μF capacitor from pin
to AGND.
16 PGND — Ground returns for low-side MOSFETs
Pulse limit pin. Connect a capacitor from the PLMT pin to GND to set minimum period allowed of the
8 PLMT I
external PWM pulse.
On-time programming pin. Connect a resistor to VIN based on the desired pseudo-fixed switching
13 RON I
frequency.
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to the power
1,2 SW I
inductor.
Undervoltage lockout and external PWM dimming input. Connect to VIN through a resistor divider to
12 UDIM I implement input undervoltage protection. Diode couple external PWM signal to enable dimming. Do
not float.
VCC bias supply pin. Locally decouple to AGND using a 2.2-μF to 4.7-μF ceramic capacitor located
4 VCC O
close to the controller.
Power input and connection to high-side MOSFET drain node. Connect to the power supply and
14,15 VIN I bypass capacitors CIN. The path from the VIN pin to the high frequency bypass capacitor and PGND
must be as short as possible.
The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This
PowerPAD —
PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN –0.3 36 V
Input Voltage
VIN (< 400 ms) 40 V
Bias supply
VVCC –0.3 5.5 V
voltage, VCC

Boot voltage, BST to SW –0.3 5.5 V

BST BST to GND –0.3 41.5 V
VSW to GND –0.5 36 V
Switch node
VSW to GND (< 400 ms) –0.5 40 V
voltage
VSW to GND (< 10 ns) –3.5 40 V
CSP, CSN –0.5 36 V
RON –0.1 36 V
IRON 500 µA
Inputs V(CSP-CSN) –0.3 0.3 mV
UDIM to GND –0.3 VVIN V
IADJ –0.1 5.5 V
COMP, PLMT –0.3 5.5 V
Outputs FLT –0.3 20 V
PGND to AGND –0.5 0.5 V
Ground
PGND to AGND (< 10 ns) –3.5 3.5 V
TJ Junction temperature –40 150 °C
Tstg Storage temperature –40 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±2000
Corner pins (SW, DLMT, FLT and
V(ESD) Electrostatic discharge Charged device model (CDM), per ±750 V
PGND)
AEC Q100-011
Other pins ±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVIN Input Voltage 5.5 36 V
V(CSP-CSN) Sensed inductor current ripple voltage 10 mV
dVCSP/dt CSP slew-rate 10 V/µs
ILED LED Current (Pulse < 4 ms) 5 A
VUDIM Digital PWM Input –0.3 VVIN
FLT Fault Output –0.3 18
fSW Switching Frequency 400 2200 kHz
TA Ambient temperature –40 125 °C
TJ Junction temperature –40 150 °C

5.4 Thermal Information

DEVICE
THERMAL METRIC(1) PKG (HTSSOP) UNIT
PINS
RθJA Junction-to-ambient thermal resistance 38.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.3 °C/W
RθJB Junction-to-board thermal resistance 19.9 °C/W
ΨJT Junction-to-top characterization parameter 0.7 °C/W
ΨJB Junction-to-board characterization parameter 19.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.5 Electrical Characteristics

–40°C < TJ < 150°C, VIN = 14V, VUDIM = 5V, VIADJ = 2.1V, CVCC = 2.2μF, CBST = 1nF, CCOMP = 1nF, RCS = 100mΩ, RON =
401kΩ, , CPLMT = 680nF, fSW = 200 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VDO LDO dropout voltage IVCC = 20 mA, VVIN = 5 V 315 mV
ISW Input switching current 10 17.6 mA
IOP Input operating current Not switching, VIADJ = VVCC 2 4 mA
BIAS SUPPLY (VCC)
VCC(UVLO-RISE) Rising threshold VCC rising threshold, VVIN = 8 V 4.40 4.58 V
VCC(UVLO-FALL) Falling threshold VCC falling threshold, VVIN = 8 V 3.9 4.2 V
VCC(UVLO-HYS) Hysteresis 200 mV
VCC(REG) Regulation voltage No Load 4.75 5.00 5.25 V
ICC(LIMIT) Supply current Limit VVCC = 0 V 45 56 76 mA
HIGH-SIDE FET (SW, BOOT)
RDS(ON-HS) High-side MOSFET on resistance ILED = 100 mA 65 130 mΩ
VBST(UV) Bootstrap gate drive UVLO V(BST-SW) rising 3.24 3.4 3.54 V
VBST(HYS) Bootstrap gate drive UVLO hysteresis Hysteresis 175 207 240 mV
IQ(BST) Bootstrap pin quiescent current VSW = 0V, VUDIM = 0 V, VBOOT = 5 V 215 280 350 µA
LOW-SIDE FET (SW)
RDS(ON-LS) Low-side MOSFET on resistance ILED = 100 mA 67 130 mΩ
HIGH SIDE FET CURRENT LIMIT
ILIM(HS) High-side current limit threshold 6.1 8.6 10.3 A
t(HS-BLANK) High-side current sense blanking period 60 ns
LOW SIDE FET CURRENT LIMIT
ISINK(LS) Sinking current limit 2.0 3.2 4.3 A
tBLANK Blanking time 71 ns
ERROR AMPLIFIER (CSP, CSN, COMP)
VIADJ = VCC, VCSP = 3 V, ICOMP = 0 V 168 175 182 mV
V(CSP-CSN) Current sense threshold
VIADJ = 2.1 V, VCSP = 3 V, ICOMP = 0 V 150 mV
ICSP CSP bias current VIADJ = 150 mV 10 µA
gM Transconductance 450 µA/V
ICOMP(SRC) COMP current source capacity VIADJ = 2.5 V, V(CSP-CSN) = 0 V 200 µA
ICOMP(SINK) COMP current sink capacity VIADJ = 150 mV, V(CSP-CSN) = 300 mV 140 µA
VCOMP(RISE) COMP startup threshold Rising 2.45 V
VCOMP(HYS) COMP startup comparator hysteresis 440 mV
EA(BW) Bandwidth Unity gain bandwidth 3 MHz
ICOMP(LKG) Comp leakage current VUDIM = 0 V 2.5 nA
VCOMP(RST) COMP pin reset voltage VVCC dropping from 5 V to 0 V 100 mV
RCOMP(DCH) COMP discharge FET resistance 230 Ω
VCOMP(OV) COMP overvoltage protection threshold 2.9 3.2 V
COMP overvoltage protection
VCOMP(OV-HYS) 60 mV
hysteresis
Falling 1.5 V
VCSP(SHORT) Output short circuit detection threshold
Rising 1.6 V

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–40°C < TJ < 150°C, VIN = 14V, VUDIM = 5V, VIADJ = 2.1V, CVCC = 2.2μF, CBST = 1nF, CCOMP = 1nF, RCS = 100mΩ, RON =
401kΩ, , CPLMT = 680nF, fSW = 200 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG ADJUST INPUT (IADJ)
VIADJ(CLAMP) IADJ internal clamp voltage 2.45 V
VIADJ(DIS) Disable threshold voltage Rising 133 mV
VIADJ(DIS) Disable threshold voltage Falling 100 mV
VALLEY CURRENT COMPARATOR
gM(LV) Level shift amplifier transconductance 50 µA/V
tDEL V(CSP-CSN) falling to gate rising delay 65 ns
ON-TIME GENERATOR (RON)
tON(MIN) Minimum on-time 85 101 117 ns
VVIN = 14 V, VCSP = 5 V, RON = 35 kΩ 150 ns
VVIN = 10 V, VCSP = 8 V, RON = 35 kΩ 336 ns
tON Programmed on-time
VVIN = 14 V, VCSP = 3 V, RON = 400 kΩ 0.95 µs
VVIN = 10 V, VCSP = 8 V, RON = 400 kΩ 3.55 µs
MINIMUM OFF-TIME
tOFF(MIN) Minimum off-time V(CSP-CSN) = 0 V, VCOMP = 2.5 V 63 78 93 ns
PWM DIMMING and PROGRAMMABLE UVLO INPUT (UDIM)
IUDIM(DO) UDIM source current (UVLO hysteresis) VUDIM > 2.45 V 6.5 10 13 µA
VUDIM(EN,RISE) Undervoltage lockout rising threshold VUDIM rising 1.22 1.27 V
VUDIM(EN,FALL) Undervoltage lockout falling threshold VUDIM falling 1.075 1.120 V
tUDIM(RISE) UDIM to SW pin rising delay 1200 ns
tUDIM(FALL) UDIM pin SW pin falling delay 105 ns
DUTY CYCLE LIMIT
RPLMT(PU) PLMT Pull-Up Resistor 19.2 22.7 28.3 kΩ
RPLMT(PD) PLMT Pull-Down Resistor 75.0 91.8 110.0 kΩ
RPLMT(DIS) PLMT Discharge Resistor 48 Ω
VPLMT(PK) PLMT Peak Voltage 2.340 2.439 2.540 V
VPLMT(VAL) PLMT Valley Voltage 786 819 851 mV
FAULT INDICATION (nFLT)
R(FLT) Fault pin pull-down resistance IFLT = 20 mA 2.5 7 Ω
TOC Hiccup retry delay time 5.5 ms
TUC(BLANK) Undercurrent reporting blanking period 20 µs
I FLT(LKG) Fault pin leakage current 100 nA
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C
TSD(HYS) Thermal shutdown hysteresis 15 °C

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5.6 Typical Characteristics

–40°C < TJ < 150°C, VIN = 14 V, VUDIM = 5 V, VIADJ = 2.1V , CVCC = 2.2 μF, CBST = 1 nF, CCOMP = 1 nF, RCS = 100 mΩ, RON =
401 kΩ, , CPLMT = 680 nF, fSW = 200 kHz

5.01 120

High-side MOSFET on resistance (m)

5.008
110
5.006
VCC Regulation Voltage (V)

100
5.004
5.002 90

5 80
4.998
70
4.996
60
4.994
4.992 50
4.99
40
-40 -20 0 20 40 60 80 100 120 140 160
-40 -20 0 20 40 60 80 100 120 140 160
Te mperature (C)
Te mperature (C)
Figure 5-1. VCC Regulation Voltage vs Temperature Figure 5-2. High-Side MOSFET On Resistance vs Temperature
9.2 120

Low-side MOSFET on resistance (m)

High-side current limit threshold (A)

9 110

8.8 100

8.6 90

8.4 80

8.2 70

8 60

7.8 50

7.6 40
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Te mperature (oC) Te mperature (C)
Figure 5-3. High-Side Current Limit Threshold vs Temperature Figure 5-4. Low-Side MOSFET On Resistance vs Temperature
3.375 2.451

3.325
Low-side sinking current limit (A)

2.4505
IADJ internal clamp voltage (V)

3.275

3.225 2.45

3.175
2.4495
3.125

3.075 2.449

3.025
2.4485
2.975

2.925 2.448
-40 -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 140 160
Te mperature (C) Te mperature (C)

Figure 5-5. Low-Side Sinking Current Limit vs Temperature Figure 5-6. IADJ Internal Clamp Voltage vs Temperature

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5.6 Typical Characteristics (continued)

–40°C < TJ < 150°C, VIN = 14 V, VUDIM = 5 V, VIADJ = 2.1V , CVCC = 2.2 μF, CBST = 1 nF, CCOMP = 1 nF, RCS = 100 mΩ, RON =
401 kΩ, , CPLMT = 680 nF, fSW = 200 kHz

V(CSP-CSN) threshold error (%)

2

-2

-4

-6
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75
Figure 5-7. V(CSP--CSN) Sense Threshold vs Temperature VIADJ (V)
Figure 5-8. V(CSP--CSN) Sense Error vs IADJ Setpoint

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6 Detailed Description
6.1 Overview
The TPS92642-Q1 is a wide input, synchronous buck LED driver. The device can deliver up to 5 A of
continuous current and power a single string of one to 10 series-connected LEDs. The device implements
an adaptive on-time current regulation control technique to achieve fast transient response. This architecture
uses a comparator and a one-shot on-timer that varies inversely with input and output voltage to maintain a
near-constant frequency. The integrated low offset rail-to-rail error amplifier enables closed-loop regulation of
LED current and ensures better than 4% accuracy over a wide input, output, and temperature range. The LED
current reference is set by the IADJ pin and is programmed by a voltage divider to achieve over a 15:1 linear
analog dimming range. The high impedance IADJ input simplifies LED current binning and thermal protection.
The TPS92642-Q1 device incorporates an internal pulse generator to implement a maximum LED pulse duty
cycle limit. The maximum PWM duty cycle, DPLMT, is internally fixed to 13.6% (typical) of the PWM period. This
PWM period is set using external capacitor, CPLMT, connected from the PLMT pin to GND. The LED current can
be pulse width modulated by the external pulsed signal connected to the UDIM input for any duration less than
the limit, tPWM_ON(LMT), set by the internal pulse generator circuit. The maximum on-time, tPWM_ON(LMT)is fixed
at DPLMT × tPLMT where tPLMT is the period set by the external CPLMT capacitor. In addition, the internal pulse
generator also behaves as a one-shot timer and blocks any subsequent UDIM pulses until the end of the period,
tPLMT. The internal pulse generator circuit and maximum duty cycle limit function can be disabled by connecting
PLMT pin to GND. This device optimizes the inductor current response and is capable of responding to an input
PWM signal with a minimum pulse width of 10 µs.
The device incorporates enhanced fault features, including the following:
• Cycle-by-cycle switch overcurrent limit
• Input undervoltage protection
• Boot undervoltage protection
• Comp overvoltage warning
• LED short-circuit indication
In addition, thermal shutdown (TSD) protection is implemented to limit the junction temperature at 175°C
(typical).

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6.2 Functional Block Diagram

5V LDO
VIN VCC
Regulator
2.45 V
Internal
References 1.22 V
Thermal
UVLO
Limit
Standby BST

+
BST UVLO VIN
RON On-time

VIN On-Time Min on-time

Generator Min off-time
VCSP
LEB
10
A

HS Limit Current
UDIM
Limit
PWM(DIM) + Circuit
UVLO and VBST(UV) –
PWM detection
SW

Current
Logic LS Limit Limit
COMP Circuit
100 mV Short VCC LEB
Reset
Logic Fault

+ CompUV PGND
VCOMP(RISE) + CompOV
VCOMP(OV) FLT
+ Short
VCSP(SHORT) CompOV and Short Fault

Valley Current
CSP Control VCC

R R

R VCC
CSN + 2
+ Q
Q R
Error Amplifier Int. PWM
IADJ + PLMT
PWM(DIM) Q S
Q
+ VCC
6 4R
VIADJ(CLAMP) 14R

AGND Fault

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6.3 Feature Description

6.3.1 Internal Regulator
The TPS92642-Q1 incorporates a 36-V rated linear regulator to generate the 5-V (typical) VCC bias supply and
other internal reference voltages. The VCC output is monitored internally to by a UVLO circuit. Operation is
enabled when VCC exceeds the VCC(UVLO) rising threshold and is disabled when VCC drops below VCC(UVLO)
falling threshold. The comparator provides 200 mV of hysteresis to avoid chatter during transitions. The VCC
UVLO thresholds are internally fixed and cannot be adjusted. An internal current limit circuit is implemented
to protect the device during VCC pin short-circuit conditions. The VCC supply powers the internal circuitry, the
low-side gate driver and the bootstrap supply for high-side gate driver. Place a bypass capacitor (4.7 μF to 10
μF) between VCC pin and AGND as close to the device as possible. The capacitor must be five times larger
than the bootstrap capacitor, CBST to support proper operation. The regulator operates in dropout when input
voltage, VIN, falls below 5 V, forcing VCC to be lower than VIN by VDO for a 20-mA supply current. The VCC is a
regulated output of the internal regulator and is not recommended to be driven from an external power supply.
6.3.2 Buck Converter Switching Operation
The following operating description of the TPS92642-Q1 refers to the Functional Block Diagram and the
waveforms in Figure 6-1. The main control loop of the TPS92642-Q1 is based on an adaptive on-time pulse
width modulation (PWM) technique that combines a constant on-time control with an inductor valley current
sense circuit for pseudo-fixed frequency operation. This proprietary control technique enables closed-loop
regulation of LED current and fast dynamic response necessary to meet the requirements for driver monitoring
systems (DMS) using infrared and laser diodes.

V(CSP-CSN)

IL × RCS

VVAL

t
VSW
VIN

0
t
tON tOFF tSW
Figure 6-1. Adaptive On-Time Buck Converter Waveforms

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In steady state, the high-side MOSFET is turned on at the beginning of each cycle. The on-time duration of
this MOSFET is controlled by an internal one-shot timer and the high-side MOSFET is turned off after the timer
expires. The one-shot timer duration is set by the output voltage measured at the CSP pin, VCSP, and the input
voltage measured at the VIN pin, VIN, to maintain a pseudo-fixed frequency. During the on-time interval, the
inductor current increases with a slope proportional to the voltage applied across its terminals (VIN – VCSP).
The low-side MOSFET is turned on after a fixed dead time and the inductor current then decreases with the
constant slope proportional to the output voltage, VCSP. Inductor current measured by the external sense resistor
is compared to the valley threshold, VVAL, by an internal high-speed comparator. This MOSFET is turned off
and the one-shot timer is initiated when the sensed inductor current falls below the valley threshold voltage. The
high-side MOSFET is turned on again after a fixed dead time.
The internal rail-to-rail error amplifier sets the valley threshold voltage and regulates the average inductor
current based on a reference value set by VIADJ pin. A simple integral loop compensation circuit consisting of a
capacitor connected from the COMP pin to GND provides a stable and high-bandwidth response. As the inductor
current is directly sensed by an external resistor, the device operation is not sensitive to the ESR of the output
capacitors and is compatible with common multilayered ceramic capacitors (MLCC).
6.3.3 Bootstrap Supply
The TPS92642-Q1 contains both high-side and low-side N-channel MOSFETs. The high-side gate driver works
in conjunction with an internal bootstrap diode and an external bootstrap capacitor, CBST. During the on-time
of the low-side MOSFET, the SW pin voltage is approximately 0 V and CBST is charged from the VCC supply
through the internal diode and external RBST resistor. TI recommends a 33-nF to 100-nF capacitor between the
BST and SW pins.

VCC

BST

+
BST UVLO VIN

LEB
CBST
HS Limit Current
Limit
+ Circuit
VBST(UV) –
SW

Figure 6-2. Bootstrap Network

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6.3.4 Switching Frequency and Adaptive On-Time Control

The TPS92642-Q1 uses an adaptive on-time control scheme and does not have a dedicated on-board oscillator.
The one-shot timer is programmed by the RON resistor. The on-time is calculated internally using Equation 1
and is inversely proportional to the measured input voltage, VIN, and directly proportional to the measured CSP
voltage, VCSP.

VCSP
tON = 10 × 10−12 × RON × VIN (1)

Given the duty ratio of the buck converter is VCSP/VIN, the switching period, TSW, remains nearly constant over
different operating points. Use Equation 2 to calculate the switching period.

V
TSW = tON × V IN = 10 × 10−12 × RON (2)
CSP

The switching frequency is calculated internally using Equation 3.

1
f SW = (3)
10 × 10−12 × RON

The minimum or maximum duty cycle is limited to finite minimum on-time, TON(MIN) and minimum off-time,
TOFF(MIN), respectively. As on-time is constant, the frequency is also a dependent on the efficiency of the device,
ηREG, excluding inductor and sense resistor losses.

1
f SW = (4)
10 × 10−12 × RON × ηREG

TI recommends a switching frequency setting between 100 kHz and 2.2 MHz.
6.3.5 Minimum On-Time, Off-Time, and Inductor Ripple
Buck converter operation is impacted by minimum on-time, minimum off-time, and minimum peak-to-peak
inductor ripple limitations. The converter reaches the minimum on-time of 96 ns (typical) when operating with
high input voltage and low-output voltage. In this control scheme, the off-time continues to increase and the
switching frequency reduces to regulate the inductor current and LED current to the desired value.

VOUT MIN
f SW MIN = T ; t = tON MIN (5)
ON MIN × VIN MAX ON

The converter reaches the minimum off-time of 91 ns (typical) when operating in dropout (low input voltage and
high output voltage). As the on-time and off-time are fixed, the duty cycle is constant and the buck converter
operates in open-loop mode. The inductor current and LED current are not in regulation.
The behavior and response of valley comparator is dependent on sensed peak-to-peak voltage ripple,
ΔV(CSP-CSN), and is a function of current sense resistor, RCS, and peak-to-peak inductor current ripple,
ΔiL(PK-PK). To ensure periodic switching, the sensed peak-to-peak ripple must exceed the minimum value. At
high (near 100%) or low (near 0%) duty cycles, the inductor current ripple may not be sufficient to ensure
periodic switching. Under such operating conditions, the converter transitions from periodic switching to a burst
sequence, forcing multiple on-time and off-time cycles at a rate higher than the programmed frequency. Although
the converter may not operate in a periodic manner, the closed-loop control continues regulating the average
LED current with a larger ripple value corresponding to higher peak-to-peak inductor ripple. TI recommends
choosing an inductor, output capacitor, and switching frequency to ensure minimum sensed peak-to-peak ripple
voltage under nominal operating condition is greater than 8 mV. The Application and Implementation section
summarizes the detailed design procedure.

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6.3.6 LED Current Regulation and Error Amplifier

The reference voltage, VIADJ, set by the VIADJ and is internally scaled by a gain factor of 1/14 through a resistor
network. An internal rail-to-rail error amplifier generates an error signal proportional to the difference between the
scaled reference voltage (VIADJ / 14) and the inductor current measured by the differential voltage drop between
CSP and CSN, V(CSP-CSN). This error drives the COMP pin voltage, VCOMP, and directly controls the valley
threshold of the inductor current. Zero average DC error and closed-loop regulation is achieved by implementing
an integral compensation network consisting of a capacitor connected from the output of the error amplifier to
GND. As a good starting point, TI recommends a capacitor value between 1 nF and 10 nF between the COMP
pin and GND. The choice of compensation network must ensure a minimum of 60° of phase margin and 10 dB
of gain margin.

CSP1

CSN1
Current Sense Amplifier
Valley Current 10k
500 uS
Control
10k
+
COMP1
2.45 V Division by 14

V-I Converter
DAC VIADJ
+
IADJ1 0 V to 2.45 V

140k

Figure 6-3. Closed-Loop LED Current Regulation

LED current is dependent on the current sense resistor, RCS. Use Equation 17 to calculate the LED current.

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TI recommends a Schottky diode connected from PGND to SW placed close to the device for LED current
greater than 4-A and operating frequency is above 1-MHz. The diode reduces the impact of high frequency noise
on PGND from impacting the valley detection circuit. The diode only conducts for a brief period of time and
hence the impact on efficiency is negligible.

VIN

DFP

SW LED+

DSW COUT DRP

PGND
Recommended LED

ILED > 4 A

Figure 6-4. Switch node Schottky diode connection

LED current accuracy is a function of the tolerance of the external sense resistor, RCS, and the variation
in the sense threshold, V(CSP-CSN), caused by internal mismatch and temperature dependency of the analog
components. The TPS92642-Q1 incorporates low offset rail-to-rail amplifiers, and is capable of achieving LED
current accuracy of ±4% over common-mode range and a junction temperature range of –40°C to 150°C.

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6.3.7 Start-Up Sequence

The start-up circuit allows the COMP pin voltage to gradually increase, thus reducing the LED current overshoot
and current surges. The switching operation is initiated after the COMP pin voltage exceeds 2.45 V. A 440-mV
hysteresis window allows the device to operate when COMP voltage is within the expected operating range of
2.2 V to 2.7 V. Switching is disabled on detection of low COMP voltage to avoid excessive negative inductor
current.
The duration of soft start, tss, depends on the size of the compensation capacitor and the error amplifier source
current, ICOMP(SRC).

2.45 × C
COMP
tSS = I (6)
COMP SRC

The source current, ICOMP(SRC) is a function of the transconductance, gM, of the error amplifier and error
generated between the reference and the current sensed voltage.

VIADJ
ICOMP SRC = gM × 14 − V CSP − CSN (7)

With no current flowing through the LEDs, the soft start duration depends on the choice of compensation
capacitor, CCOMP, and the reference voltage, VIADJ.
VIADJ

0.1

VUDIM

2.45

VCOMP
2.45
440 mV

t
VSW
VIN

0
t
ILED

Figure 6-5. Soft-Start Sequence

The open drain fault indicator, FLT, is set low when the COMP voltage deviates from the nominal range
and exceeds VCOMP(OV) threshold. This setting indicates a fault condition where the converter is operating in
open-loop and the LED current is out of regulation. The device can be disabled by setting IADJ input below 100
mV or controlling the UDIM input.

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6.3.8 Analog Dimming and Forced Continuous Conduction Mode

Analog dimming is accomplished by the voltage on IADJ pin, VIADJ. The TPS92642-Q1 improves the linear
range of analog dimming by supporting forced continuous conduction mode of operation. With synchronous
MOSFETs, the inductor current is allowed to go negative for part of the switching cycle, thus enabling linear
dimming with over 15:1 dimming range. TI recommends a 10-nF capacitor from IADJ pin to AGND pin to
improve noise sensitivity.
6.3.9 External PWM Dimming and Input Undervoltage Lockout (UVLO)
The UDIM pin is a multifunction input that features an accurate input voltage detection based on band-gap
thresholds with programmable hysteresis as shown in Figure 6-6. This pin functions as the external PWM
dimming input for the LEDs and monitors VIN to detect dropout and undervoltage conditions. When the rising pin
voltage exceeds the 1.22-V threshold, 10 µA (typical) of current is driven out of the UDIM pin into the resistor
divider providing programmable hysteresis. TI recommends a bypass capacitor value of 1 nF between the UDIM
pin and GND to improve noise immunity.

VIN
Standard PWM and PWM
PWM Dropout
Detec on Dropout

V5A
RUV2 VBG
DDIM + 10
A
RUVH UDIM 10 k

RUV1
CUDIM

Inverted QDIM
PWM
Figure 6-6. External PWM Dimming

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The brightness of LEDs can be varied by modulating the duty cycle of the signal directly connected to the
UDIM input. In addition, either an n-channel MOSFET or a Schottky diode can be used to couple an external
PWM signal when using UDIM input in conjunction with UVLO functionality. With an n-channel MOSFET, the
brightness is proportional to the negative duty cycle of the external PWM signal. With a Schottky diode, the
brightness is proportional to the positive duty cycle of the external PWM signal.
Dropout and input undervoltage protection is achieved by connecting the resistor divider network from VIN
to UDIM pin and UDIM pin to GND. Dropout protection is activated when UDIM pin voltage drops below
VUDIM(EN, FALL) threshold. The minimum input voltage, below which drop protection is activated is programmed
using Equation 8.

RUVH + 10 × 103 × RUV1 + RUV2

VIN DO, FALL = VIN DO, RISE − IUDIM DO × RUV2 + RUV1 (8)

R + RUV2
VIN DO, RISE = VUDIM EN, RISE × UV1
RUV1 (9)

Additional hysteresis to internal 100 mV is programmed by connecting an external resistor, RUVH in series with
UDIM pin. This connection allows the standard resistor divider to have smaller values, minimizing PWM delays.
Input undervoltage protection is triggered when UDIM pin voltage drops below VUDIM(EN) thresholds. The
device responds to very low VIN voltage or to the external PWM input signal by disabling the error amplifier,
disconnecting the COMP pin and tri-stating the switch node. With switch disabled, inductor current and the LED
current drops to zero and the charge on the compensation network is maintained. On rising edge of PWM or
when VIN exceeds the internal hysteresis of 100 mV, the converter resumes switching operation. The inductor
current quickly ramps to the previous steady-state value.

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6.3.10 Pulse Duty Cycle Limit Circuit

The TPS92642-Q1 features an internal analog circuit to impose a limit on the on-time, tPWN(ON) and off-time,
tPWM(OFF), of the output current, ILED. As illustrated in Figure 6-7, the device is controlled by external UDIM
pulses with widths less than tPWM_ON(LMT). Any external UDIM pulses that are longer than tPWM(LMT) are
truncated to maintain a maximum fixed duty ratio of DPLMT. The device also rejects any spurious pulses that
can be present on the external UDIM input by blanking the UDIM signal during the PLMT off time. The off time
is a function of the period, tPLMT, set by the external capacitor, CPLMT. This mechanism is designed to help
limit overexposure to infrared lights due to error conditions in DMS applications. The relationship between tPLMT,
tPWM_ON(LMT) and DPLMT is given in Equation 10.

tPWM_ON LMT = DPLMT × tPLMT (10)

VUDIM
Spurious
pulse

t
VPLMT

tPLMT

t
ILED

t
tUDIM DPLMT × tPLMT
tPWM
Figure 6-7. Duty Cycle Limit Function Using Internal Pulse Generator

The desired pulse period, tPLMT, is set by external capacitor, CPLMT.

tPLMT = 1.168 × 105 × CPLMT (11)

The maximum pulse on-duration, tPWM_ON(LMT), and minimum off-duration, tPWM_OFF(LMT), is given in Equation 12
and Equation 13.

tPWM_ON LMT = 0.6931 × RPLMT PU × CPLMT (12)

tPW\M_OFF LMT = 1.1 × RPLMT PD × CPLMT (13)

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For LED current set point greater than 2.5 A, the maximum pulse-duration is impacted due to the switching noise
in the system. The maximum pulse-duration as a function of LED current is given in Equation 14. Because the
off-duration, tOFF, does not change, the duty cycle ratio reduces with increase in LED current.

tPWM_ON LMT = 0.6931 × RPLMT PU × CPLMT − 1.76 × 10−2 × ILED − 2.5 × tPLMT (14)

As an alternative, the PLMT pin can be externally driven by an external pulse generator or microcontroller to set
the maximum on-duration and minimum off-duration, independent of the external UDIM input. In this case, the
circuit functionality remains unchanged, however ,the pulse parameters are set by external pulse signal driving
PLMT pin. The relationship between external PLMT signal and UDIM signal is shown in the following figure.

VUDIM
Spurious
pulse

t
VPLMT
VCC
6 tPLMT
VCC
2 t
ILED

t
tUDIM tPWN_ON(LMT)
tPWM
Figure 6-8. Duty Cycle Limit Function Using External Pulse Generator

The pulse duty cycle limit function is disabled by connecting PLMT pin to GND. The LED current is controlled
directly by the PWM signal connected to UDIM input.

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6.3.11 Output Short and Open-Circuit Faults

The TPS92642-Q1 monitors the CSN voltage to detect output short circuit faults. A short failure is indicated
by open drain FLT output when the CSN voltage drops below 1.5 V (typical). The device continues to regulate
current and operate without interruption in case of short circuit. A short-circuit fault does not impact the device
behavior. The device continues to operate and regulate current without interruption.
An LED open-circuit fault ultimately causes the output voltage to increase and settle close to the input
voltage. When this event occurs, the TPS92642-Q1 switching operation is then controlled by the fixed on-time
and minimum off-time resulting in a duty cycle close to 100%. The COMP pin voltage exceeds the COMP
overvoltage threshold, VCOMP(OV), and the fault in indicated by FLT output. However, during open circuit, the
dynamic behavior of the device and buck converter is influenced by the input voltage, VIN, and the output
capacitor, COUT, value. The device response to open circuit can be categorized into the following two distinct
cases.
Case 1: For a Buck converter design with a small output capacitor, the switching operation in open load condition
excites the tank resonance forcing the output voltage to oscillate. The frequency and amplitude of the oscillation
are based on the resonant frequency and Q-factor of the second order tank network.
VCSN
VIN

VCOMP tOC t

VCOMP(OV)
t

Figure 6-9. Open-Circuit Condition with Output Voltage Oscillation

Case 2: For a buck converter design with large output capacitor the inductor Q-factor and resonant frequency
are much lower than the switching frequency. In this case, output voltage rises to input voltage and the converter
continues to switch with minimum off-time.
VCSN
VIN

t
Figure 6-10. Open-Circuit Condition with Minimum Off-Time Operation

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The voltage transient imposed on CSP and CSN inputs during short circuit and open circuit is dependent on the
output capacitance and is influenced by the cable harness impedance. The inductance associated with a long
cable harness resonates with the charge stored on the output capacitor and forces CSP and CSN voltage to
ring above VIN and below ground. The magnitude of the voltage overshoot above VIN and below ground are
dependent on the parasitic cable harness inductance and resistance.

CSN

CSP

VIN

LPAR
RCS LED+ tOC(+)
SW

tSH
COUT
LPAR
tOC( )
PGND
LED

Figure 6-11. Cable Harness Parasitic Inductance

When using a long cable harness, TI recommends diodes to clamp the voltage across CSP and CSN input, as
shown in Figure 6-12. TI recommends a low forward voltage Schottky diode or a fast recovery silicon diode with
reverse blocking voltage rating greater than the maximum output voltage. The diode is required to be placed
close to the output capacitor.

VIN

DFP

SW LED+

COUT DRP

PGND
LED

Figure 6-12. Transient Protection Using an External Diode

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6.3.12 Overcurrent Protection

The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side and
the low-side MOSFETs.
The device turns off the high-side MOSFET and discharges the COMP capacitor when the drain current exceeds
7.7-A typical. The low-side switch is turned on to discharge the inductor current and output capacitor.
When the low-side switch is turned on, the switch current is also sensed and monitored. The device turns off
both high-side and low-side MOSFETs and discharges the COMP capacitor when the drain current (from drain to
PGND) exceeds 3.2-A typical.
IL
7.7 ILIM(HS)

iL
tON tOFF
0.0 (t)
-3.2 ISINK(LS)

Figure 6-13. Overcurrent Protection Thresholds

The device employs hiccup mode overcurrent protection. In hiccup mode, the device shuts itself down and
attempts to start after TOC. Hiccup mode helps reduce the device power dissipation under severe overcurrent
conditions.
6.3.13 Thermal Shutdown
Thermal shutdown prevents the device from extreme junction temperatures by turning off the internal switches
when the IC junction temperature exceeds 175℃ (typical). Thermal shutdown does not trigger below 158℃.
After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature
drops to approximately 160℃. When the junction temperature falls below 160℃ (typical), the device attempts to
start up.

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6.3.14 Fault Indicator and Diagnostics Summary

Table 6-1 summarizes the device behavior under fault conditions.
Table 6-1. Fault Description
FAULT DETECTION DESCRIPTION

The thermal protection is activated in the event the maximum MOSFET temperature
Thermal protection TJ > 175°C exceeds the typical value of 175°C. This feature is designed to prevent overheating
and damage to the internal switching MOSFETs.

VCC undervoltage VCC(RISE) < 4.4 V The device enters the Undervoltage Lockout (UVLO). The switching operation is
lockout VCC(FALL) < 4.2 V disabled, the COMP capacitor is discharged.

VIN undervoltage The device disables switching operation for the corresponding channel. Switching is
VUDIM < 1.12 V
lockout enabled when the input voltage rises above the turn-on threshold, VIN(DO,RISE) .

VBST(RISE) < 3.4 V The device turns off the high-side MOSFET and turns on the low-side MOSFET for
BST undervoltage
the corresponding channel. Normal switching operation is resumed after the bootstrap
lockout VBST(FALL) < 3.2 V voltage exceeds 3.2 V.

The FLT flag is set low to indicate that the COMP voltage exceeded the normal
COMP overvoltage VCOMP > 3.2 V
operating range. This condition indicates output open-circuit fault.

The FLT flag is set low to indicate an output short-circuit condition based on sensed
Short output VCSN < 1.5 V
CSN voltage.

The device turns off the high-side MOSFET, turns on low-side MOSFET and
High-side switch
IHS > 8.6 A discharges the COMP capacitor. The device attempts to restart after a delay of 5.5
current limit
ms.

Low-side switch The device turns off both high-side and low-side MOSFETs and discharges the COMP
ILS > 3.2 A
current limit capacitor. The device attempts to restart after a delay of 5.5 ms.

Output open and short circuit faults force the FLT pin low when biased through an external resistor and
connected to a 5-V supply. The FLT output can be used in conjunction with a microcontroller or system basis
chip (SBC) as an interrupt and aid in fault diagnostics.
6.4 Device Functional Modes
This device has no additional functional modes.

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

Figure 7-1 shows a schematic of a typical application for the TPS92642-Q1.
RCS
L
LED+
D1
1 SW COUT
PGND 16
2 SW GND
CIN1 D2
CBST 3 BST VIN 15
VIN
VIN 14
4 VCC
RON RUV2 RUV1
CIADJ
5 IADJ RON 13
RIADJ2 UDIM 12
CCOMP
6 COMP CSP 11 PWM
CVCC CUDIM
7 AGND CSN 10
RIADJ1
CPLMT FLT 9
8 PLMT

Figure 7-1. Typical Application Schematic

The TPS92642-Q1 controller is suitable for implementation of step-down LED driver topology. Use the following
design procedure to select component values for the TPS92642-Q1 device. This section presents a simplified
discussion of the design process for the Buck converter.

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7.1.1 Duty Cycle Considerations

The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In
steady state, the duty cycle is defined using Equation 15:

V
D = VCSN (15)
IN

The buck converter maximum operating duty cycle, DMAX, at minimum input voltage, VIN,MIN and maximum LED
voltage, VCSN,MAX.

V
DMAX = VCSN, MAX (16)
IN, MIN

There is no limitation for small duty cycles, because at low duty cycles, the switching frequency is reduced
as needed to always ensure current regulation. The maximum duty cycle attainable is limited by the minimum
off-time duration and is a function of switching frequency.
7.1.2 Switching Frequency Selection
Nominal switching frequency is set by programming the RON resistor. The switching varies slightly over operating
range and temperature based on converter efficiency. Table 7-1 shows common switching frequencies and
corresponding RON resistor values.
Table 7-1. Switching Frequency Setting
RON (kΩ) SWITCHING FREQUENCY (kHz)

267 400

243 435

221 480

50 2000

44.2 2200

7.1.3 LED Current Programming

The LED current is set by the external current sense resistor, RCS, and the analog adjust voltage, VIADJ. The
LED current can be programmed by varying VIADJ between 140 mV to 2.3 V. The LED current can be calculated
using Equation 17:

VIADJ
ILED = 14 × R (17)
CS

The LED current can be programmed by varying VIADJ between 140 mV and 2.3 V. TI recommends a 10-nF
capacitor from IADJ pin to AGND pin to filter high frequency switching noise.

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7.1.4 Inductor Selection

The inductor is sized to meet the ripple specification at maximum operating duty cycle. TI recommends a
minimum sensed peak-to-peak voltage ripple (ΔV(CSP-CSN)) of 8 mV and typical voltage ripple of 20 mV to ensure
periodic switching operation under.

∆ V CSP − CSN = ∆ iL × RCS (18)

Use Equation 19 to calculate the inductor value.

V − VCSN, MAX V
L = IN, MIN
∆ iL × f SW × VCSN, MAX (19)
IN, MIN

The maximum inductor current ripple occurs at 50% duty cycle. Use Equation 20 to calculate the maximum
peak-to-peak inductor current ripple, ΔiL(MAX).

VIN TYP
∆ iL MAX = 4 × L × f (20)
SW

Use Equation 21 and Equation 22 to calculate the RMS and peak currents through the inductor. Make sure that
the inductor is rated to handle these currents.

2
2 ΔIL MAX
iL RMS = ILED MAX + 12 (21)

ΔiL MAX
iL PK = ILED MAX + 2 (22)

7.1.5 Output Capacitor Selection

The output capacitor value depends on the total series resistance of the LED string, rD, and the switching
frequency, fSW. The capacitance required for the target LED ripple current, ΔiLED, is calculated using Equation
23.

ΔiL MAX
COUT = 8 × f (23)
SW × rD × ΔiLED

When choosing the output capacitors, consider the ESR and ESL characteristics because they directly impact
the LED current ripple. Ceramic capacitors are the best choice due to the following:
• Low ESR
• High ripple current rating
• Long lifetime
• Good temperature performance
With ceramic capacitor technology, consider the derating factors associated with higher temperature and DC
bias operating conditions. TI recommends an X7R dielectric with a voltage rating greater than maximum LED
stack voltage.

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7.1.6 Input Capacitor Selection

The input capacitor buffers the input voltage for transient events and decouples the converter from the supply. TI
recommends a 10-µF input capacitor across the VIN pin and PGND placed close to the device, and connected
using wide traces. X7R-rated ceramic capacitors are the best choice due to the low ESR, high ripple current
rating, and good temperature performance.
In addition, a small case size 100-nF ceramic capacitor must be used across VIN to PGND, immediately
adjacent to the device. This usage provides a high-frequency bypass for the control circuits internal to the
device. These capacitors also suppress SW node ringing, which reduces the maximum voltage present on the
SW node and EMI.
The capacitance can be increased to further limit the input voltage deviation during PWM dimming operation.
7.1.7 Bootstrap Capacitor Selection
The bootstrap capacitor biases the high-side gate driver during the high-side FET on-time. TI recommends that
a 100-nF capacitor rated for 10 V or higher is used. The VBSTI(UV) threshold is designed to maintain proper
high-side FET switching operation. If the CBST capacitor voltage drops below VBST(UV), then the device initiates a
charging sequence, turning on the low-side FET before attempting to turn on the high-side FET. For a very low
PWM frequency, the charging sequence is initiated on the rising edge of the PWM pulse. The duration of the
low-side switch turn-on as a function of pulse width can be tuned by increasing the value of bootstrap capacitor,
CBSTI, depending on the application.
7.1.8 Compensation Capacitor Selection
TI recommends a simple integral compensator to achieve stable operation across the wide operating range. The
buck converter behaves as a single pole system with additional phase lag caused by the switching behavior.
The gain and phase margin are, consequently determined by the choice of the switching frequency and are
independent of other design parameters. TI recommends a 1-nF to 10-nF capacitor to achieve bandwidth
between 4 kHz and 40 kHz. The choice of compensation capacitor impacts the transient response and PWM
dimming performance. TI recommends a larger compensation capacitor (lower bandwidth) to limit the LED
current overshoot on the rising edge of internal or external PWM signal.
Table 7-2. Compensation Capacitor Value
BANDWIDTH (kHz) COMPENSATION CAPACITOR (nF)
40 1
18 2.2
12 3.3
8.5 4.7
5.8 6.8
4.8 8.2
4 10

7.1.9 Input Dropout and Undervoltage Protection

Figure 7-1 shows that the undervoltage protection threshold is programmed using a resistor divider, RUV1 and
RUV2, from the input voltage, VIN to PGND. Use Equation 24 and Equation 25 to calculate the resistor values.

VIN DO, RISE VIN DO, FALL

RUV2 = I − I − 10 × 103 (24)
UDIM DO UDIM DO

VUDIM EN, RISE

RUV1 = V × RUV2 (25)
IN DO, RISE − VUDIM EN, RISE

A capacitor of 1 nF from UDIM pin to GND is placed close to device to improve noise immunity.

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7.1.10 Pulse Duty Cycle Limit Circuit

The period of internal pulse generator (tPLMT) is set by the CPLMT capacitor. The period, tPLMT defines the
minimum repetition rate of LED current pulses allowed based on external UDIM signal and is set based on
the maximum PWM frequency, fPWM(MAX). An additional margin in design is necessary to compensate for the
component tolerances and noise in the system. The tPLMT period is determined using Equation 26.

0.9
tPLMT = f (26)
PWM MAX

The pulse limit capacitor, CPLMT, capacitor is calculated using Equation 27.

tPLMT
CPLMT = (27)
1.168 × 105

Table 7-3 summarizes the TI recommended pulse limit capacitor value for different PWM frequencies. A single
capacitor or parallel combination of capacitors must be rated for 6.3 V or higher and with tolerance lower than
10%.
Table 7-3. Pulse Limit Capacitor Value
PWM DIMMING FREQUENCY (Hz) PLMT CAPACITOR (µF)
30 0.25
50 0.15
60 0.12

7.1.11 Protection Diodes

External Schottky diodes are required to protect the CSP / CSN node by clamping the voltage during short
circuit and open-circuit transients. The Schottky diode must be selected based on the length of the cable
harness and the choice of output capacitor. TI recommends a Schottky diode with low forward voltage drop at
room-temperature and non-repetitive peak surge current rating of 10 A for duration of 5 µs. The diodes from
CSN to VIN and GND to CSN must be located close to the pin.

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7.2 Typical Application

L3
R24
3.3uH 0.033 LED+
CSP CSN C24 D7
D1 25V D8
2.2uF

U3 GND
C25 C26
1 16 100nF 10µF
SW PGND
50V 50V GND
2 15
SW VIN
C27 16V VIN
VCC 3 14 R26 R27
BST VIN 47.5k 191k
100nF 4 13
VCC RON
C28 16V
5 12
IADJ UDIM PWM
C29 16V D9
10nF 6 11 CSP
COMP CSP R29
R28
57.6k 2200pF 7 10 CSN 29.4k
AGND CSN C31
C30
16V 1000pF
C32 8 9
PLMT FLT 16V
1µF
16V 0.25uF 17
PowerPAD
GND GND
R30 IADJ TPS92642QPWPRQ1 VCC
GND R31
34k GND
100k

nFLT
GND

Figure 7-2. Application Schematic

7.2.1 Design Requirements

Table 7-4. Design Parameters
PARAMETER CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 22 24 26 V
NS Number of LEDs 2
VFLED LED forward voltage drop 3.5 4.2 5.0 V
rD LED string series resistance N × rD(LED) 200 500 mΩ
VCSN Output voltage Ns × VFLED 7.0 8.4 10.0 V
ILED LED current 2500 4000 5000 mA
ΔiLED LED current ripple 80 mA
ΔV(CSP-CSN) Sensed voltage ripple 20 mV
VIN(DO,RISE) Start input voltage Input voltage rising 9 V
VIN(DO,FALL) Stop input voltage Input voltage falling 7 V
fPWM PWM frequency 29 30 31 Hz
DPWM PWM dimming duty cycle Internaly fixed by pulse duty cycle circuit 13.62 %
fSW Switching frequency 2100 kHz
TA Ambient temperature 25 °C

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7.2.2 Detailed Design Procedure

7.2.2.1 Calculating Duty Cycle

Solve for duty cycle D, DMAX, and DMIN:
VCSN MAX
DMAX = V = 10
22 = 0.4545 (28)
IN MIN

VCSN MIN 7
DMIN = V = 26 = 0.2692 (29)
IN MAX

7.2.2.2 Calculating Minimum On-Time and Off-Time

Solve for minimum on-time, tON(DMIN), at minimum duty cycle and minimum off-time, tOFF(DMAX), at maximum duty
cycle:
VCSN MAX
tON DMAX = V × f 1 = 10 1
22 × 2100 × 103 = 216 ns (30)
IN MIN sw

VCSN MIN
tON DMIN = V × f 1 = 26
7
× 1
= 128 ns (31)
IN MAX sw 2100 × 103

7.2.2.3 Minimum Switching Frequency

Confirm minimum switching frequency at tON(DMIN), fSW(MIN):
V
CSN MIN 7
f sw MIN = = = 2100 kHz (32)
tON DMIN × V 128 × 10−9 × 26
IN MAX

For the design specification, tON(DMIN) > tON(MIN) and fSW(MIN) = fSW.

7.2.2.4 LED Current Set Point

Solve for sense resistor, RCS:

VIADJ MAX
RCS = 14 × I = 142.3
× 5 = 0.0329 (33)
LED MAX

A standard resistor of 33 mΩ with tolerance better than 1% and low temperature coefficient is selected. The
power dissipated in RCS is calculated:
2
Psense = DPLMT × RCS × ILED MAX = 0.1362 × 0.033 × 52 = 0.1124 W (34)

A resistor with rated power of 250 mW and above must be selected.

A resistor divider network, with standard values 57.6 kΩ and 34 kΩ, from VCC pin to GND sets the nominal
LED current reference voltage of 1.856 V. A 10-nF capacitor from IADJ pin to AGND pin is included to filter high
frequency switching noise.

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7.2.2.5 Inductor Selection

The inductor is selected to meet the recommended peak-to-peak voltage ripple, ΔV(CSP-CSN) of 20 mV:

V − VCSN, MAX V
L = IN, MIN × VCSN, MAX = 22 − 10
× 10
22 = 3.247 × 10
−6
(35)
∆ iL × f SW IN, MIN 800 × 10−3 × 2100 × 103

The closest standard capacitor is 3.3 µH.

• Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost at the
expense of reduced efficiency and larger output capacitor.
• Higher inductance values decrease the peak-to-peak inductor current, which increases efficiency but reduces
the operating range based on minimum sense voltage ripple, ΔV(CSP-CSN) specification.

7.2.2.6 Output Capacitor Selection

The minimum output capacitance is selected to meet the LED current ripple specification:

∆ iL MAX 0.608
COUT = 8 × f = = 2.261 × 10−6 (36)
SW × rD MAX × ∆ iLED 8 × 2100 × 103 × 0.5 × 80 × 10−3

A standard 2.2-µF, 25-V X7R capacitor is selected.

7.2.2.7 Bootstrap Capacitor Selection

A standard 0.1-µF, 16-V X7R capacitor is selected to support 2100-kHz switching frequency.

7.2.2.8 Compensation Capacitor Selection

A compensation capacitor of 2.2 nF is selected to achieve balanced transient response between PWM dimming
and shunt FET dimming.

7.2.2.9 VIN Dropout Protection and PWM Dimming

The resistor divider, RUV1 and RUV2, is set to meet VIN(UVLO,RISE) and VIN(DO,FALL) thresholds.

9 7
RUV2 = − − 10 × 103 = 190 × 103 (37)
10 × 10−6 10 × 10−6

1.22 3 3
RUV1 = 9 − 1.22 × 190 × 10 = 29.8 × 10 (38)

A standard value resistors of 191 kΩ and 29.4 kΩ are selected for RUV2 and RUV1, respectively.
The external PWM dimming is achieved by controlling UDIM input. The device modulates the LED current based
on the PWM duty cycle of the external signal, coupled through external diode.

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7.2.3 Application Curves

Ch1: SW voltage (10 V/div); Ch2: Output voltage (1 V/div); Ch1: SW voltage (5 V/div); Ch2: Output voltage (2 V/div); Ch3:
Ch3: Inductor current (1 A/div); Ch4: VIN voltage (10 V/div); LED current (1 A/div); Time: 400 ns/div
Time: 5 ms/div
Figure 7-4. Normal Operation
Figure 7-3. Start-up Transient

Ch1: SW voltage (5 V/div); Ch2: Output voltage (2 V/div); Ch3: Ch1: SW voltage (5 V/div); Ch2: Output voltage (2 V/div); Ch3:
Inductor current (1 A/div); Time: 5 µs/div Inductor current (1 A/div); Time: 1 µs/div

Figure 7-5. PWM Dimming (Rising Edge) Figure 7-6. PWM Dimming (Falling Edge)

Ch2: Output voltage (4 V/div); Ch3: LED current (1 A/div); Ch2: Output voltage (4 V/div); Ch3:
Ch4: FLT voltage (2 V/div); Time: 40 ms/div LED current (1 A/div); Ch4: FLT voltage
(2 V/div); Time: 40 ms/div
Figure 7-7. Output Short-Circuit Fault
Figure 7-8. Output Open-Circuit Fault

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7.3 Power Supply Recommendations

The characteristics of the input supply must be compatible with Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded converter.
If the converter is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to
the converter or tripping UVLO. Additional bulk capacitance or an input filter can be required in addition to the
ceramic bypass capacitors to address converter stability, noise, and EMI concerns.
7.4 Layout

7.4.1 Layout Guidelines

The performance of any switching converter depends as much on the layout of the PCB as the component
selection. The following guidelines can help design a PCB with the best power converter performance.
• Place ceramic high-frequency bypass capacitors as close as possible to the TPS92642-Q1 VIN and PGND
pins. Grounding for both the input and output capacitors must consist of localized top side planes that
connect to the PGND pin.
• Place bypass capacitors for VCC close to the pins and ground the capacitors to device ground.
• Use wide traces for the CBST capacitor and RBST resistor. Place RBST and CBST network as close as possible
to BST pin and SW pin.
• Differentially route the CSP and CSN pins to sense resistor. Route the traces away from noisy nodes,
preferably through a layer on the other side of a shielding/ground layer.
• Use ground plane in one of the middle layers for noise shielding.
• Make VIN and ground connection as wide as possible. This action reduces any voltage drops on the input of
the converter and maximizes efficiency.
• Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
7.4.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt from pulsing currents in switching converters. The larger the area
covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize
radiated EMI is to identify the pulsing current path and minimize the area of the path. In buck converters, the
pulsing current path is from the VIN side of the input capacitors through the HS switch, through the LS switch,
and then returns to the ground of the input capacitor.
High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic capacitors as close as possible to the VIN and PGND pins is the key to EMI
reduction.
The PCB copper connection of the SW pin to the inductor must be as short as possible and just wide enough
to carry the LED current without excessive heating. Short, thick traces or, copper pours (shapes), must be used
for high current conduction path to minimize parasitic resistance. Place the output capacitor close to the CSN pin
and grounded closely to the PGND pin.

7.4.1.1.1 Ground Plane

TI recommends using one of the middle layers as a solid ground plane. The ground plane provides shielding for
sensitive circuits and traces. the ground plane also provides a quiet reference potential for the control circuitry.
Connect the GND, AGND and PGND pins to the ground plane using via right next to the bypass capacitors.
PGND pins are connected to the source of the internal LS switch. They must be connected directly to the
grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can
bounce due to load variations.

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7.4.2 Layout Example

1 SW PGND 32
2 SW VIN 31
3 BST VIN 30
4 VCC RON 29
5 IADJ UDIM 28
6 COMP CSP 27
7 AGND CSN 26 GND
8 PLMT FLT 25

Figure 7-9. TPS92642-Q1 Layout Example

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8 Device and Documentation Support

8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
DATE REVISION NOTES
November 2023 * Initial release

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE
PWP0016G SCALE 2.400
PowerPAD
TM
TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

C
6.6
TYP SEATING PLANE
6.2

A PIN 1 ID
AREA 0.1 C
14X 0.65
16
1

5.1 2X
4.9 4.55
NOTE 3

4X (0 -12 )

8
9
4.5 0.30
B 16X 1.2 MAX
4.3 0.17
NOTE 4 0.1 C A B

0.18
TYP
0.12

SEE DETAIL A

2X 0.56 MAX 2X 0.24 MAX

NOTE 6 NOTE 6

THERMAL
PAD 0.25
GAGE PLANE
3.29
2.71

0.15
0 -8 0.05
0.75
0.50 DETAIL A
(1) TYPICAL
2.41
1.77

4218975/C 12/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
6. Features may not present.

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EXAMPLE BOARD LAYOUT

PWP0016G PowerPAD
TM
TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(3.4)
NOTE 10
(2.41)
SOLDER MASK SOLDER MASK
OPENING DEFINED PAD
16X (1.5) SYMM SEE DETAILS

1
16

16X (0.45)

(0.95)
SYMM (5)
TYP (3.29)
SOLDER MASK
OPENING

14X (0.65)
9
8

(0.95) TYP
METAL COVERED
( 0.2) TYP
(5.8) BY SOLDER MASK
VIA

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER SOLDER MASK

SOLDER MASK METAL SOLDER MASK OPENING
OPENING

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-16
4218975/C 12/2023

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
10. Size of metal pad may vary due to creepage requirement.

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EXAMPLE STENCIL DESIGN

PWP0016G PowerPAD
TM
TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(2.41)
BASED ON
16X (1.5) 0.127 THICK
STENCIL
1
16

16X (0.45)

SYMM (3.29)
BASED ON
0.127 THICK
STENCIL

14X (0.65)
8 9
(R0.05)
SYMM
SEE TABLE FOR
METAL COVERED DIFFERENT OPENINGS
BY SOLDER MASK (5.8) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.69 X 3.68
0.127 2.41 X 3.29 (SHOWN)
0.152 2.20 X 3.00
0.178 2.04 X 2.78

4218975/C 12/2023

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

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www.ti.com 30-Nov-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS92642QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 642Q1 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
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