Project Review 1

on
“ IMPLEMENTATION OF FIR FILTER FOR NOISE REMOVAL IN ADPLL”

By Batch : B18
A. Sri Mani Prapulla (1608-21-735-090)
G. Sree Viswambhara Reddy (1608-21-735-119)
H.Uday (1608-21-735-124)
Under the Guidance of:
Mrs. J.SHAILAJA
M..E, (PhD)
Assistant Professor

Department of Electronics and Communication Engineering

(Accredited by NBA)
MATRUSRI ENGINEERING COLLEGE
(Sponsored by Matrusri Education society, Estd1980)
(Approved by AICTE, Affiliated to Osmania University)
#16-1-486, Saidabad, Hyderabad, Telangana-500059
www.matrusri.edu.in
2024-25
CONTENTS
▪ Introduction
▪ Literature Survey
▪ Problem Statement
▪ Objective
▪ Block Diagram
▪ Conclusion
▪ References
INTRODUCTION
▪ The Chips to Startup(C2S) program is an initiative by the INDIAN government to
encourage startups and entrepreneurs in the field of semiconductor design and
manufacturing.
▪ As a part of this initiative, the implementation of an All-Digital Phase-Locked Loop
(ADPLL) is a crucial component.
▪ However, noise removal is a significant challenge in ADPLL design.
LITERATURE SURVEY
S.No Author Title Year Description
1 Chia-Chen A Low-Jitter ADPLL with 2021 This work contributes to the development
Chang,YuTung Adaptive High-Order Loop of high-performance ADPLLs, enabling
Chin,Hossameldi Filter and Fine Grain Varactor improved jitter performance and robust
n A.Ibrahim,Kang Based DCO operation in various applications, including
Yu Chang, Shyh- wireless communication systems and high-
Jye Jou speed digital circuits

2 Kusum Lata and ADPLL Design and 2013 The ADPLL is designed to generate a
Manoj Kumar Implementation on FPGA stable clock signal with minimal jitter.
The ADPLL is implemented on an FPGA
using VHDL, with a focus on minimizing
area, power consumption, and jitter.

3 Kusum Lata and ALL Digital Phase-Locked 2012 The survey highlights the advantages and
Manoj Kumar Loop (ADPLL): A Survey challenges of ADPLLs, providing a
comprehensive understanding of their
design and applications.
LITERATURE SURVEY

S.No Author Title Year Description

4 Abadian, A., Lotfizad, A New Low Power and Low- 2010 The proposed ADPLL design achieves
M., Majd, N.E., Complexity All Digital PLL low power consumption, low
Ghoushchi, M.B.G (ADPLL ) complexity, and fast locking time,
and Mirzaie, H making it suitable for high-performance
and low-power applications.
5 Martin Kumm, Harald An FPGA-Based Linear All- 2010 The proposed FPGA-based linear
Klingbeil, and Peter Digital Phase-Locked Loop ADPLL design achieves notable
Zipf improvements in phase noise reduction,
locking time, and resource utilization.
6 Walter Fergusson W, Modeling and Simulation of 2007 The proposed modeling and simulation
Patel Rakesh H, Noise in Closed-Loop All-Digital approach provides a valuable tool for
William Bereza. PLLs using Verilog-A analyzing noise in closed-loop
ADPLLs, enabling the design of high-
performance and low-noise ADPLLs.
PROBLEM STATEMENT
▪ Noise in ADPLL leads to jitter, phase errors, and instability.
▪ Traditional analog filters are not suitable for ADPLL due to their analog nature in terms of
accuracy, power consumption, and area.
▪ A digital filtering approach is necessary to remove noise and ensure stable ADPLL
operation.
OBJECTIVES

▪ Investigate the design and implementation of FIR filters for noise removal in ADPLL.
▪ Analyze the performance of FIR filters in terms of noise reduction, power consumption,
and area.
▪ Compare the effectiveness of different FIR filter architectures and design techniques.
BLOCK DIAGRAM
“Vd” “Vf ”

V1 Digital Digital
Phase Loop
Detector Filter

V2’

Square
waves Digital
VCO

Fig 1.1 General block diagram of ADPLL

Fig 1.2 General block diagram of FIR filter
CONCLUSION
The proposed FIR filter design aims to effectively remove noise from ADPLL, enhancing
clock signal quality and stability. This design leverages the advantages of FIR filters,
including linear phase response and ease of implementation.
Future implementation will focus on optimizing filter
performance, integrating with other noise removal techniques, and ensuring
robustness to variations.
 REFERENCES
1. Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. IBRAHIM, Kang Yu Chang, and Shyh-Jye Jou
“A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO
IEEE 2021.
2. Kusum Lata and Manoj Kumar, “ADPLL Design and Implementation on FPGA”, IEEE 2013
International Conference on Intelligent Systems and Signal Processing (ISSP).
3. Kumar M, Lata K (2012) All digital phase locked loop (ADPLL): a survey. In: proceeding the 4th
IEEE international conference on electronics computer technology, Kanyakumari.
4. Abadian, A., Lotfizad, M., Majd, N.E., Ghoushchi, M.B.G and Mirzaie, H.: "A new low power and
low-complexity All Digital PLL (ADPLL) in 180 nm and 32 nm," IEEE International Conference
on electronics, circuits and systems, December 2010, pp.305-310.
5. Kumm, M., Klingbeil, H. and Zipf, P.: "An FPGA-based linear All-Digital Phase-Locked loop,"
IEEE Transactions on circuits and systems-I, Regular papers, vol.57, No.9, September2010,
PP.2487-2497.
6. Walter Fergusson W, Patel Rakesh H, William Bereza. Modelling and Simulation of Noise in
Closed-Loop All-Digital PLL using Verilog-A. IEEE 2007 Custom Integrated Circuits Conference
(CICC). 2007; 857–860p.
7. Watanabe, T. and Yamauchi, S.: "An All-Digital PLL for Frequency multiplication by 4 to 1022 with
seven cycle lock time," IEEE Journal of solid-state circuits, vol. 38, No.2, February 2003, pp.198-204.
8. Xin Chen, Jun Yang and Xiao-ying Deng: "A Contribution to the discrete z-domain analysis of ADPLL,"
IEEE International Conference on ASIC, October 2007, pp.185-188. 12. Bo Jiang and Tian Xia: "ADPLL
Variables Determinations based on phase-noise, spur and locking time," IEEE International SOC
Conference, September 2012, pp.39-44.
9. Bo Jiang and Tian Xia: "ADPLL Variables Determinations based on phase-noise, spur and locking time,"
IEEE International SOC Conference, September 2012, pp.39-44.
10. Lee, J., & Park, M. (2023). "Advanced FIR Filtering Techniques for Biomedical Applications." IEEE
Transactions on Biomedical Engineering, 70(3), 1234-1242.
11. C. Chung and C. Lee, “An all-digital phase-locked loop for high-speed clock generation” IEEE J. Solid-
State Circuits, vol. 38,pp.347-351,Feb. 2003.
12. Yu-Ming Chung and Chia-Ling Wei, "An All-Digital Phase-Locked loop for Digital power management
integrated chips," IEEE International Symposium on circuits and systems, May 2009, pp. 2413-2416.
13. Chang-hong Shan, Zhong-ze Chen, Yan Wang: "An All-Digital Phase-Locked loop based on Double
Edge Triggered Flip-flop," IEEE, 2006.
THANK YOU