Digital Techniques

Lecturer: Ali Jawad Kadhim Alrubaie

E-mail: ali.jawad@mustaqbal-college.edu.iq
TA: Esraa Hussein

Experiment No. 9
PN – Sequence Generation
1. Introduction
1.1 Objective:
 Familiarize students with PN – Sequence Generator and its applications.
 Learn how to find out the PN sequence for any generation from their logic circuit.

1.2 Components:
1. ST2611 Digital Circuit Development Platform trainer with power supply cord
2. DB20 – PN Sequence Generator
3. Wires

1.3 Theory:
Pseudo-Noise (PN) sequences are usually used in order to generate noise that is approximately
"white". It has applications in scrambling, cryptography, and spread-spectrum communications. It is
also commonly referred to as the Pseudo-Random Binary Sequence (PRBS). These are very widely
used in communication standards these days. The qualifier "pseudo" implies that the sequence is not
truly random. Actually, it is periodic with a (possibly large) period and exhibits some characteristics
of a random white sequence within that period. PN sequences are generated by Linear Feedback
Shift Registers (LFSR), as shown in the following Figure (1):

Figure 1: Linear Feedback Shift Registers (LFSR)

A linear feedback shift register (LFSR) is a shift register whose input bit is the output of a linear
function of two or more of its previous states (taps). An LFSR of length m consists of m stages
numbered 0,1,…,m−1, each capable of storing one bit, and a clock controlling data exchange.
From all the flip-flops of the shift register, outputs are fed to one logic circuit with one switch to
each. The output of the logic circuit is again fed to the input of the primary (left most) flip-flop.

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 Figure 2: PN Sequence

As you can see in Figure (2) there are 3 flip-flops with outputs s1, s2, s3. Therefore, the length of the
shift register is m = 3. The output of the entire system is s3. Its also can be said from Figure (2) that,
after a clock pulse is encountered, s2 = s1, s3 = s2, s1 = s1 ⊕ s3. The entire system state table is as
follows in Table (1), taking initial contents of the shift register as ‘111’.

Table 1: State Table for PN Sequence Generation

For m flip-flop the number of states is 2m and the maximum length of the period of this sequence is
N = 2m – 1. So, for the above example the number of states is 23 = 8 and the maximum length of the
period is N = 23 – 1 = 7. Hence, it is observed that after 8th clock pulse we are getting the same
initialized flip flop content ‘111’. Therefore, the output sequence depends on the number of shift-
register (m), initial state, and feedback logic. Here, we have ‘11101001’ as the PN sequence
followed by the same sequence again and again, periodically.
Note that in case that feedback logic consists entirely with modulo-2 (MOD-2) adders (XOR gate)
only, the initial state cannot be all zero state because if the state of the shift register is all zero at any
time, it remains so for all time and it will not generate new sequences. We need to ensure that this
never happens (we start with a non-zero value).
For today experiment, we are going to use the panel DB20 PN Sequence Generator. This panel as
you can see has 4 flip-flops so the m = 4. There is an OR gate between the outputs of FF1 and FF2
and another OR gate between the outputs of FF3 and FF4. The outputs of these two OR gates are the
inputs of a NOR gate. Also, the outputs of FF2 and FF4 are set to be the inputs for XOR gate. Then

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 its output with the NOR gate output are the inputs of an OR gate where we get the output of the PN
sequence.
Let’s take the initial value as ‘1000’ and from that we are going to calculate the output as follows.
F = ((S1 + S2) + (S3 + S4))’ + (S2 ⊕ S4)
F = ((1 + 0) + (0 + 0))’ + (0 ⊕ 0)
F = (1 + 0)’ + 0
F = (1)’ + 0
F=0+0
F=0
So, the output of the initial value of the DB20 PN sequence is 0 as in Table (2).
Clock Pulse Intermediate States Outputs
No. S1 S2 S3 S4
1 1 0 0 0 0
2
3
4
5
6
7
8
Table 2:DB20 PN Sequence Generator

2. Experiments:
2.1 Exercise 1 PN Sequence Generator:
1. Place the DB20 panel as shown in Figure (3) on the trainer.
2. To provide power to the board, connect +5 V pin from the trainer on the left side to +5V pin on
the DB20 using a wire.
3. Connect GND pin from the trainer on the left side to ground symbol pin on the DB20.
4. Connect the clock input from Pulser switch to the CLK IN pin on the left bottom of the DB20.
5. Connect the X pin on the left top of DB20 to Y pin on the left bottom.
6. Connect the N pin on the right top of DB20 to the Q pin of the flip-flop 2 on the bottom.
7. Connect the M pin on the right top of DB20 to the E pin on the very right side of DB20.
8. Connect PN Seq. OUT pin on the left top of the DB20 to the Oscilloscope in order to display the
output of the PN sequence.
9. Make sure all your connections are right then turn on the power supply.
10. Write down the results you get from the oscilloscope.

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 Figure 3: DB20 PN Sequence Generator Panel

3. Discussion:
1. How many states the PN sequence generator of DB20 have?
2. What is the length of PN sequence generator of DB20?
3. Calculate the outputs of each clock and put them on the Table (2).
4. What is the PN Sequence of the DB20.
5. Verify the outputs you get with the outputs from the device.

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