74LVC573A

OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS

A
Description Pin Assignments
The 74LVC573A provides eight transparent D-type latches. While
the latch-enable (LE) input is high, the Q outputs follow the data (D) (Top View ) (Top Transparent View )
terminal
inputs. When LE is taken low, the Q outputs are latched at the logic
Vcc

Vcc
1 20 index
1
OE

OE
area
levels set up at the D inputs. A buffered output-enable (OE) input
NEW PRODUCT

D1 Q1

20
2 19

1
can be used to place the eight outputs in either a normal logic state
D1 2 19 Q1
(high or low logic levels) or the high-impedance state. In the high- D2 3 18 Q2
D2 3 18 Q2
impedance state, the outputs neither load nor drive the bus lines D3 4 17 Q3 D3 4 17 Q3
significantly. The high-impedance state and increased drive provide
D4 5 16 Q4 D4 5 16 Q4
the capability to drive bus lines without interface or pullup
components. OE does not affect the internal operations of the D5 6 15 Q5 D5 6 15 Q5
latches. Old data can be retained or new data can be entered while D6 7 14 Q6
D6 7 14 Q6
the outputs are in the high-impedance state. D7 8 13 Q7
D7 8 13 Q7
D8 9 12 Q8
These devices feature inputs and outputs on opposite sides of the D8 9 12 Q8

11
10
package that facilitate printed circuit board layout. The device is

GND
LE
GND 10 11 LE
designed for operation with a power supply range of 1.65V to 3.6V.

TSSOP-20 V-QFN4525-20
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using IOFF. The IOFF circuitry disables the Applications
output preventing damaging current backflow when the device is  General Purpose Logic
powered down.  Bus Driving
 Power Down Signal Isolation
Features  Wide Array of Products such as:
 Supply Voltage Range from 1.65V to 3.6V  PCs, Notebooks, Netbooks, Ultrabooks
 Sinks or Sources 24mA at VCC = 3V  Networking Computer Peripherals, Hard Drives, CD/DVD
 CMOS Low Power Consumption ROM
 IOFF Supports Partial-Power Down Operation  TV, DVD, DVR, Set Top Box
 Inputs or Outputs Accept Up to 5.5V
 Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage
Applications
 Schmitt Trigger Action at All Inputs
 Typical VOLP (Quiet Output Ground Bounce) Less than 0.8V
with VCC = 3.3V and TA = +25°C
 Typical VOHV (Quiet Output Dynamic VOH) Greater than 2.0V
with VCC = 3.3V and TA = +25°C
 ESD Protection Tested per JESD 22
 Exceeds 200-V Machine Model (A115)
 Exceeds 2000-V Human Body Model (A114)
 Exceeds 1000-V Charged Device Model (C101)
 Latch-Up Exceeds 250mA per JESD 78, Class I
 All devices are:
 Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)
 Halogen and Antimony Free. “Green” Device (Note 3)

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen and Antimony free,
"Green" and Lead-Free.
3. Halogen and Antimony free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.

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Ordering Information A
74 LVC 573A XXX -13

Logic Device Function Package Packing

74 : Logic Prefix 573A : Octal T20 : TSSOP-20 -13 : 13” Tape & Reel
NEW PRODUCT

LVC : Low Voltage CMOS Transparent D- Q20 : V-QFN4525-20

Type Latch with
3-State Outputs

Package Package Package 13” Tape and Reel

Part Number
Code (Notes 4 & 5) Size Quantity Part Number Suffix
6.4mm X 6.5mm X 1.2mm
74LVC573AT20-13 T20 TSSOP-20 2500/Tape & Reel -13
0.65mm Lead Pitch
2.5mm X 4.5mm X 0.95mm
74LVC573AQ20-13 Q20 V-QFN4525-20 2500/Tape & Reel -13
0.50mm Lead Pitch
Notes: 4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
5. V-QFN4525-20 is a JEDEC recognized naming convention that specifies the package thickness category as V and the number 4525 describes the
package as 4.5mm X 2.5mm.

Pin Descriptions Logic Diagram Function Table

Pin Pin OE
1
(Each Latch)
Description
Number Name
11 INPUTS OUTPUT
1 OE Output Enable LE
OE LE D Q
2 D1 Data Input 2
3 D2 Data Input D1 D 19 L H H H
Q Q1
4 D3 Data Input C
L H L L
5 D4 Data Input
3 L L X Q0
6 D5 Data Input D2 D 18
Q Q2 H X X Z
7 D6 Data Input C
8 D7 Data Input
9 D8 Data Input 4
D3 D 17
10 GND Ground Q Q3
C
11 LE Latch Enable
12 Q8 Latch Output 5
13 Q7 Latch Output D4 D 16
Q Q4
14 Q6 Latch Output C
15 Q5 Latch Output
16 Q4 Latch Output 6
D5 D 15
Q Q5
17 Q3 Latch Output C
18 Q2 Latch Output
19 Q1 Latch Output 7
D6 D 14
20 VCC Supply Voltage Q Q6
C

8
D7 D 13
Q Q7
C

9
D8 D 12
Q Q8
C

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Absolute Maximum Ratings (Notes 6 & 7) A

Symbol Description Rating Unit
ESD HBM Human Body Model ESD Protection 2 kV
ESD CDM Charged Device Model ESD Protection 1 kV
ESD MM Machine Model ESD Protection 200 V
VCC Supply Voltage Range -0.5 to +7.0 V
NEW PRODUCT

VI Input Voltage Range -0.5 to +7.0 V

IIK Input Clamp Current VI < 0V -20 mA
IOK Output Clamp Current VO < 0V -50 mA
IO Continuous Output Current -0.5V < VO VCC +0.5V ±50 mA
ICC Continuous Current Through VCC 100 mA
IGND Continuous Current Through GND -100 mA
TJ Operating Junction Temperature -40 to +150 °C
TSTG Storage Temperature -65 to +150 °C
PTOT Total Power Dissipation 500 mW
Notes: 6. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should be
within recommend values.
7. Forcing the maximum allowed voltage could cause a condition exceeding the maximum current or conversely forcing the maximum current could cause a
condition exceeding the maximum voltage. The ratings of both current and voltage must be maintained within the controlled range.

Recommended Operating Conditions (Note 8)

Symbol Parameter Conditions Min Max Unit
Operating 1.65 3.6 V
VCC Supply Voltage
Data Retention Only 1.5 — V
VI Input Voltage — 0 5.5 V
VO Output Voltage — 0 VCC V
VCC = 1.65V — -4
VCC = 2.3V — -8
IOH High-Level Output Current mA
VCC = 2.7V — -12
VCC = 3.0V — -24
VCC = 1.65V — 4
VCC = 2.3V — 8
IOL Low-Level Output Current mA
VCC = 2.7V — 12
VCC = 3.0V — 24
Δt/ΔV Input Transition Rise or Fall Rate — — 10 ns/V
TA Operating Free-Air Temperature — -40 +125 °C
Note: 8. Unused inputs should be held at VCC or Ground.

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 74LVC573A

Electrical Characteristics A
TA = -40°C to +85°C TA = -40°C to +125°C
Symbol Parameter Test Conditions VCC Unit
Min Max Min Max
— 1.65V to 1.95V VCC X 0.65 — VCC X 0.65 —
High-Level Input
VIH
Voltage — 2.3V to 2.7V 1.7 — 1.7 — V
— 3.0V to 3.6V 2 — 2 —
NEW PRODUCT

— 1.65V to 1.95V — VCC X 0.35 — VCC X 0.35

Low-Level Input
VIL
Voltage — 2.3V to 2.7V — 0.7 — 0.7 V
— 3.0V to 3.6V — 0.8 — 0.8
IOH = -50μA 1.65V to 3.6V VCC-0.2 — VCC-0.3 —
IOH = -4mA 1.65V 1.2 — 1.05 —
High-Level IOH = -8mA 2.3V 1.7 — 1.65 —
VOH V
Output Voltage 2.7V 2.2 — 2.05 —
IOH = -12mA
3.0V 2.4 — 2.48 —
IOH = -24mA 3.0V 2.3 — 2.0 —
IOL = 100μA 1.65V to 3.6V — 0.2 — 0.3
IOL = 4mA 1.65V — 0.45 — 0.65
Low-Level Output
VOL IOL = 8mA 2.3V — 0.60 — 0.80 V
Voltage
IOL = 12mA 2.7V — 0.40 — 0.60
IOL = 24mA 3.0V — 0.55 — 0.80
Power Down
IOFF VI or VO = 0 or 5.5V 0V — ±10 — 20 μA
Leakage Current
Input Current
II VI = GND or 5.5V 0 to 3.6V — ±5 — ±20 μA
Control Pins
Z-State Current
Including Input VI = GND or 5.5V
IOZ 3.6V — ±5 — ±20 µA
Current VO = 0 to 5.5V
I/O Pins
ICC Supply Current VI = GND or VCC, IO = 0 3.6V — 10 — 40 μA
Additional Supply
∆ICC One Input at VCC -0.6V IO = 0A 2.7V to 3.6V — 500 — 5000 μA
Current
Input Control Pins 4.0 Typical 4.0 Typical
CI VI = GND or VCC 0V to 3.6V pF
Capacitance I/O Pins 5.5 Typical 5.5 Typical

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Switching Characteristics A
TA = -40°C to TA = -40°C to
Test TA = +25°C
Symbol Parameter VCC +85°C +125°C Unit
Conditions
Min Typ Max Min Max Min Max
1.8V ± 0.15V 5.0 2.5 — 5.0 — 5.5 —
Pulse Width 2.5V ± 0.2V 4.0 2.0 — 4.0 — 4.5 —
tW Figure 1 ns
NEW PRODUCT

LE 2.7V 3.0 1.7 — 3.0 — 3.5 —

3.3V ± 0.3V 3.0 1.5 — 3.0 — 3.5 —
1.8V ± 0.15V 4.0 2.0 — 4.0 — 4.5 —
Set-up Time DN to 2.5V ± 0.2V 3.0 1.5 — 3.0 — 3.5 —
tSU Figure 1 ns
LE 2.7V 2.0 1.0 — 2.0 — 2.5 —
3.3V ± 0.3V 2.0 1.0 — 2.0 — 2.5 —
1.8V ± 0.15V 3.0 1.5 — 3.0 — 3.5 —
Hold Time 2.5V ± 0.2V 2.0 1.0 — 2.0 — 2.5 —
tH Figure 1 ns
DN to LE 2.7V 1.5 1.0 — 1.5 — 2.0 —
3.3V ± 0.3V 1.5 1.0 — 1.5 — 2.0 —
1.8V ± 0.15V 1 6 12.2 1 12.7 1 16.9
Propagation Delay 2.5V ± 0.2V 1 3.9 7.8 1 8.3 1 8.7
tPD Figure 1 ns
DN to QN 2.7V 1 4.2 7.8 1 8.1 1 9.5
3.3V ± 0.3V 1.5 3.8 6.8 1.5 7.4 1.5 8
1.8V ± 0.15V 1 7 14.8 1 15.3 1 22.5
Propagation Delay 2.5V ± 0.2V 1 4.5 10 1 10.5 1 12.4
tPD Figure 1 ns
LE to QN 2.7V 1 5.4 8.2 1 9.5 1 12
3.3V ± 0.3V 1.5 4.4 7.2 1.5 8.5 1.5 11
1.8V ± 0.15V 1 7.8 16.5 1 17 1 18.7
Enable Time OE 2.5V ± 0.2V 1 4 9 1 9.5 1 10.3
tEN Figure 1 ns
to QN 2.7V 1 4.4 8.3 1 8.5 1 9.5
3.3V ± 0.3V 1.7 4.1 7.3 1.7 7.5 1.7 9
1.8V ± 0.15V 1 7.8 16.5 1 17 1 18.4
Disable Time OE 2.5V ± 0.2V 1 4 9 1 9.5 1 10.5
tDIS Figure 1 ns
to QN 2.7V 1 4.4 8.3 1 8.5 1 9.1
3.3V ± 0.3V 1.7 4.1 7.3 1.7 7.5 1.7 9
1.8V ± 0.15V 1 7.8 16.5 1 17 1 18.4
Disable Time OE 2.5V ± 0.2V 1 4 9 1 9.5 1 10.5
tDIS Figure 1 ns
to QN 2.7V 1 4.4 8.3 1 8.5 1 9.1
3.3V ± 0.3V 1.7 4.1 7.3 1.7 7.5 1.7 9
tsk(0) Output Skew Time — 3.3V ± 0.3V — — 1.0 — — — 1.5 ns

Operating Characteristics
TA = +25°C

Symbol Parameter Test Conditions VCC Typ Unit

1.8V ± 0.15V 9.9
Power Dissipation Capacitance per f = 10MHz
CPD 2.5V ± 0.2V 10.2 pF
Gate Outputs Enabled
3.3V ± 0.3V 10.6

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 74LVC573A

Package Characteristics A
Symbol Parameter Package Test Conditions Min Typ Max Unit
Thermal Resistance
θJA TSSOP-20 (Note 9) — 74 — °C/W
Junction-to-Ambient
Thermal Resistance
θJC TSSOP-20 (Note 9) — 15 — °C/W
Junction-to-Case
NEW PRODUCT

Thermal Resistance
θJA V-QFN4525-20 (Note 9) — 67 — °C/W
Junction-to-Ambient
Thermal Resistance
θJC V-QFN4525-20 (Note 9) — 20 — °C/W
Junction-to-Case
Note: 9. Test conditions for TSSOP-20 and V-QFN4525-20: Devices mounted on 4 layer FR-4 substrate PC board, 2oz copper, with minimum recommended
pad layout per JESD 51-7.

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 74LVC573A

A
Parameter Measurement Information
VLOAD
From Output RL S1 Open
Under Test GND
TEST S1
NEW PRODUCT

CL tPLH/tPHL Open
RL
(see Note A) tPLZ/tPZL VLOAD
tPHZ/tPZH GND

Inputs
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8V ± 0.15V VCC ≤2ns VCC/2 2 x VCC 30pF 1KΩ 0.15V
2.5V ± 0.2V VCC ≤2ns VCC/2 2 x VCC 30pF 500Ω 0.15V
2.7V 2.7V ≤2.5ns 1.5V 6V 50pF 500Ω 0.3V
3.3V ± 0.3V 2.7V ≤2.5ns 1.5V 6V 50pF 500Ω 0.3V

tW

Vl
Input VM VM
Vl
0V Output
VM
VM
Control
0V
Voltage Waveform Pulse Duration Output tPZL tPLZ
Waveform 1 VLOAD/2
S1 at VLOAD VM
(see Note B) VOL + V
Vl VOL
Input VM VM tPZH tPHZ
0V Output
Waveform 2 VOH
VOH - V
tPLH tPHL S1 at GND VM
VOH (see Note B) ≈ 0V
Output VM VM
VOL
Voltage Waveform Enable and Disable Times
tPHL tPLH Low and High Level Enabling
VOH
Output VM VM
VOL
Voltage Waveform Propagation Delay Times
Inverting and Non Inverting Outputs

Notes: A. Includes test lead and test apparatus capacitance.

B. All pulses are supplied at pulse repetition rate ≤ 10MHz.
C. Inputs are measured separately one transition per measurement.
D. tPLZ and tPHZ are the same as tDIS.
E. tPZL and tPZH are the same as tEN0
F. tPLH and tPHL are the same as tPD.

Figure 1 Load Circuit and Voltage Waveforms

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 74LVC573A

Marking Information A
(1) TSSOP-20

( Top View )

14
20 11
8
YY : Year : 08, 09,10~
NEW PRODUCT

Logo
WW : Week : 01~52; 52
Part Number 74LVC573A represents 52 and 53 week
YY WW X X X X : Internal Codes

1 7 10
7

Part Number Package

74LVC573AT20 TSSOP-20

(2) V-QFN4525-20

( Top View )

YY : Year : 08, 09,10~

Logo
WW : Week : 01~52; 52
Part Number 74LVC573A represents 52 and 53 week
YY WW X X X X : Internal Codes
terminal 1
index area

Part Number Package

74LVC573AQ20 V-QFN4525-20

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 74LVC573A

Package Outline Dimensions A

Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for the latest version.

(1) Package Type: TSSOP-20

D
TSSOP-20
NEW PRODUCT

Dim Min Max Typ

A - 1.20 -
A1 0.05 0.15 -

A2 0.80 1.05
b 0.19 0.30 -
c 0.09 0.20 -
E1 E
0.25 D 6.40 6.60 6.50
Gauge Plane
E 6.20 6.60 6.40

E1 4.30 4.50 4.40
PIN 1
ID MARK e 0.65 BSC

Seating Plane L 0.45 0.75 0.60
e L1
L 1.0 REF
DETAIL θ1 0° 8° -
L1
θ2 10° 14° 12°
θ3 10° 14° 12°
A2 A
All Dimensions in mm
b
A1

(2) Package Type: V-QFN4525-20

A1
A3
A

Seating Plane V-QFN4525-20

Dim Min Max Typ
(Pin #1 ID)
D A 0.75 0.85 0.80
e A1 0.00 0.05 0.02
A3 - - 0.15
b 0.18 0.30 0.23
Z1 D 4.45 4.55 4.50
D2 2.85 3.15 3.00
E 2.45 2.55 2.50
E E2 0.85 1.15 1.00
E2 e 0.50BSC
L 0.30 0.50 0.40
Z - - 0.385
D2 Z1 - - 0.885
L All Dimensions in mm

Z b

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 74LVC573A

Suggested Pad Layout A

Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.

(1) Package Type: TSSOP-20

X (20x)
C
NEW PRODUCT

Dimensions Value (in mm)

C 0.650
X 0.420
X1 6.270
Y1 Y2 Y 1.780
Y1 4.160
Y (20x) Y2 7.720

X1

(2) Package Type: V-QFN4525-20

X4

X3 Dimensions Value (in mm)

C 0.500
X 0.330
X1 0.600
X1
X2 3.200
X2 X3 3.830
Y3 X4 4.800
Y1 Y 0.600
Y1 1.200
Y2 0.830
Y2
Y
Y3 2.800

X C

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 74LVC573A

IMPORTANT NOTICE A
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
NEW PRODUCT

application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
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website, harmless against all damages.

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final and determinative format released by Diodes Incorporated.

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written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:

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Copyright © 2015, Diodes Incorporated

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74LVC573A 11 of 11 May 2015

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