B.E / B.Tech.
PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2023
FIFTH SEMESTER
EC 3561 - VLSI LABORATORY
(Regulations 2021)
Time : 3 Hours Answer any one Question Max. Marks 100
Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total
required/Procedure Program/Drawing & Results
20 30 30 10 10 100
Design and implement an Half Adder using HDL and simulate it using Xilinx/Altera
1
Software and also implement the logic using a suitable FPGA
Design and implement an full Adder using HDL and simulate it using Xilinx/Altera Software
2
and also implement the logic using a suitable FPGA
A) Design and implement a SR flipflop using HDL and simulate it using Xilinx/Altera
Software and also implement the logic using a suitable FPGA
3
B) Design and implement a D flipflop using HDL and simulate it using Xilinx/Altera
Software and also implement the logic using a suitable FPGA
A)Design and implement a JK flipflop using HDL and simulate it using Xilinx/Altera
Software and also implement the logic using a suitable FPGA
4
B)Design and implement a T flipflop using HDL and simulate it using Xilinx/Altera Software
and also implement the logic using a suitable FPGA
Design and implement an 8-bit Adder using HDL and simulate it using Xilinx/Altera
5
Software and also implement the logic using a suitable FPGA
Design and implement a 4-bit Multiplier using HDL and simulate it using Xilinx/Altera
6
Software and also implement the logic using a suitable FPGA.
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Design and implement an Universal Shift Register using HDL and simulate it using
7
Xilinx/Altera Software and also implement the logic using a suitable FPGA.
Design and implement two blocks Mealy FSM using HDL and simulate it using
8
Xilinx/Altera Software and also implement the logic using a suitable FPGA.
Design and implement two blocks Moore FSM using HDL and simulate it using
9
Xilinx/Altera Software and also implement the logic using a suitable FPGA.
10 Design and simulate a CMOS basic gates and generate Manual/Automatic Layout .
11 Design and simulate a CMOS basic flipflops and generate Manual/Automatic Layout .
12 Design and simulate a 4-bit synchronous counter using Flip-Flops with Manual/Automatic
Layout Generation.
13 Design and implement a 3-bit synchronous counter using HDL and simulate it using
Xilinx/Altera Software and also implement the logic using a suitable FPGA.
14 Design and implement a 4-bit asynchronous counter using HDL and simulate it using
Xilinx/Altera Software and also implement the logic using a suitable FPGA.
15 Design and implement a memories using HDL and simulate it using Xilinx/Altera Software
and also implement the logic using a suitable FPGA.
16 Design and Simulate a CMOS Inverting Amplifier circuit using EDA tool and analyze the
input impedance, output impedance, gain and bandwidth by performing Schematic
Simulations.
17 Design and simulate a basic Common Source Amplifier circuit using EDA tool and
analyze the input impedance, output impedance, gain and bandwidth by performing
Schematic Simulations.
18 Design and simulate a basic Common Gate Amplifier circuit using EDA tool and analyze
the input impedance, output impedance, gain and bandwidth by performing Schematic
Simulations.
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19 Design and simulate a basic Common Drain Amplifier circuit using EDA tool and
analyze the input impedance, output impedance, gain and bandwidth by performing
Schematic Simulations.
20 Design and simulate a 5 transistor differential amplifier circuit using EDA tool and analyze
Gain, Bandwidth and CMRR by performing Schematic Simulations.
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