1. A Stack-organised Computer uses instruction of _____.

A. Indirect addressing
B. Two-addressing
C. Zero addressing
D. Index addressing
Ans: C. Zero addressing

2. In a vectored interrupt.
A. the branch address is assigned to a fixed location in memory
B. the interrupting source supplies the branch information to the processor through an
interrupt vector.
C. the branch address is obtained from a register in the processor
D. none of the above
Ans: B. the interrupting source supplies the branch information to the processor through an
interrupt vector.
3. Data is generally coded in 8-bit units, such a unit is also called
A. k
B. Word
C. field
D. byte
Ans: Byte
4. The time required to complete one instruction is
a. Fetch time
b. Execution time
c. Control time
d. Complete time
Ans: b. Execution time
5. The program counter holds
a. Data of next instruction
b. Address next instruction
c. Counter
d. Address current instruction
e. Ans : Address next instruction

6. What is the BCD for a decimal number 559

a. 0101 0101 1001
b. 1010 1010 1001
c. 1101 1101 1101
d. 0101 1001 1001
Ans: a. 0101 0101 1001
7. Which method is used to detect double errors and pinpoint erroneous bits
a. Even Parity check method
b. Odd parity
c. Checksum
d. Error correcting code
Ans: Checksum
8. What is the main purpose of parity bits?
A) To enhance processing speed
B) To detect errors in data transmission
C) To increase memory size
D) To perform data encryption
Ans: B) To detect errors in data transmission

9. What is a common challenge in multiprocessor systems related to data consistency?

 A) Memory access speed
B) Cache Coherence
C) Processor speed
D) Disk storage capacity
Ans: B) Cache Coherence

10. Which I/O technique involves the CPU being interrupted by the I/O device to signal completion of an
operation?
A) Programmed I/O
B) Memory-Mapped I/O
C) Interrupt-Driven I/O
D) Direct Memory Access (DMA)
Ans: C) Interrupt-Driven I/O

12. Which of the following is an advantage of using DMA?

A) Slower data transfer rates compared to CPU-controlled transfers
B) Increased CPU utilization during data transfers
C) Reduced CPU overhead during data transfers
D) Higher power consumption
Ans: C) Reduced CPU overhead during data transfers
13. What is a key difference between CISC and RISC architectures?
A) CISC has fewer instructions than RISC
B) RISC uses simpler instructions that take fewer cycles to execute
C) RISC uses more memory for instruction storage
D) CISC typically executes instructions faster than RISC
Ans: B) RISC uses simpler instructions that take fewer cycles to execute
14. Which of the following is used in main memory
A) DDR
B) SRAM
C) DRAM
D) PRAM
Ans: DRAM
15. What is the main disadvantage of programmed I/O?
A) High memory consumption
B) I/O devices become non-operational
C) CPU idle time while waiting for I/O operations to complete
D) The inability to support multiple peripherals
Ans: C) CPU idle time while waiting for I/O operations to complete
16. The partial remainder is restored by adding the divisor to the negative difference.
A) In non-restoration Division
B) In restoration method
C) In comparison method
D) In decimal arithmetic method
Ans: B) In restoration method
17. 2 x 2 bit array multiplier uses ____________ AND gates and _______ half adders
A) 3 and 3
B) 4 and 2
C) 2 and 4
D) 2 and 2
Ans: B) 4 and 2
18. ____________gives a procedure for multiplying binary integers in signed-2's complement representation
A) Booth algorithm
B) Multiplication algorithm
C) Comparison algorithm
 D) Binary Search algorithm
Ans: A) Booth algorithm
19. ________polynomial code obtained from the message bits by passing them through a feedback shift
register containing a number of exclusive-OR gates, used for error-free messages.
A) Parity Check
B) Echo Check
C) longitudinal redundancy check (LRC)
D) Cyclic Redundancy Check ( CRC)
Ans: D) Cyclic Redundancy Check ( CRC)

20. ___________ method uses the same address space for both memory and I/O.
A) isolated I/O
B) Memory-Mapped I/O
C) Interrupt-Driven I/O
D) Direct Memory Access (DMA)
Ans: B) Memory-Mapped I/O
21. Which of these is required when we want to establish the communication links between a CPU and its
peripherals?
a. Memory data register
b. Memory address register
c. Instruction register
d. Index register
Answer: (a) Memory data register
22. A memory unit accessed by content is _______________
A) Associative Memory
B) Virtual Memory
C) Primary Memory
D) Cache Memory
Ans: A) Associative Memory
23. The ____________ organization consists of a number of cross points that are placed at intersections
between processor buses and memory module paths.
A) Time shared
B) Crossbar switch
C) DRAM
D) Multiport memory
Ans: B) Crossbar switch

24. A ___________is a storage device that stores information in such a manner that the item stored last is
the first item retrieved
A) stack
B) Queue
C) Array
D) Tree
Ans: A) stack
25. In CISC architecture, instructions are typically:
A) Fixed-size
B) Variable size
C) Executed in one clock cycle
D) Simple and require multiple clock cycles
Ans: B) Variable size

26. The______________, referred to as reverse Polish notation (RPN)

A) Infix notation
B) Prefix notation
 C) Prepone notation
D) postfix notation
Ans: D) postfix notation
27. In which of the following addressing modes the operand immediately follows the opcode?
1. Based
2. Direct
3. Immediate
4. Indexed
5. Answer : Immediate

28. Name of the interrupt which can be minimized

1. Time interrupt
2. Makeable interrupt
3. Maskable interrupt
4. Non-Maskable interrupt
Ans: Maskable interrupt
29. What is the hexadecimal representation of 6578?
a. D71
b. 3F
c. 1AF
d. D78
Answer: (c) 1AF

30. When we add a two’s complement, 4-bit, binary numbers 1101 and 0100, it would result in:
a. 1001 and no overflow
b. 0001 and an overflow
c. 1001 and an overflow
d. 0001 and no overflow
Answer: (d) 0001 and no overflow
31. What would be the 2’s complement representation (in hexadecimal) of (−539)10?
a. 9E7
b. DE5
c. DBC
d. ABE
Answer: (b) DE5

32. What would be the 2′ s complement representation of the -15 decimal value?
a. 10001
b. 1111111
c. 1001
d. 1111
Answer: (d) 1111
33. In the Principle of locality, there is a justification of the use of:
a. DMA
b. Cache memory
c. Threads
d. Interrupts
Answer: (b) Cache memory

34. Which of these is NOT involved in the case of a memory write operation?
a. Databus
b. MDR
 c. MAR
d. PC
Answer: (d) PC

35. Which of these memories would have the lowest access time in a system:
a. Main Memory
b. Magnetic Disk
c. Registers
d. Cache
Answer: (c) Registers
36. Which of these refers to the minimization expression for the following:
A+A’B+A’B’C+A’B’C’D
a. A+B) (C+D)
b. ABCD
c. 1
d. A+B+C+D
Answer: (d) A+B+C+D

37. In Reverse Polish notation, expression A*B+C*D is written as

a) AB*CD*+
B) A*BCD*+
c) AB*CD+* (
D) A*B*CD+
Ans: A. AB*CD*+
38. In computers, subtraction is generally carried out by
a) 9’s complement
B) 10’s complement
c) 1’s complement
d) 2’s complement
Ans : D) 2’s complement

39. The circuit used to store one bit of data is known as

A. Register
B. Encoder
C. Decoder
D. Flip Flop
Ans: Register

40. The average time required to reach a storage location in memory and obtain its contents is called the
A. seek time
B. turnaround time
C. access time
D. transfer time
Ans : Access Time

41. The idea of cache memory is based

A. on the property of locality of reference
B. on the heuristic 90-10 rule
C. on the fact that references generally tend to cluster
D. Divide and conquer rule
Ans: On the property of locality of reference
42. The addressing mode used in an instruction of the form ADD X Y, is
A. Absolute
B. indirect
C. index
D. none of these
ans :C. Index

43. ________ holds the address of the instruction to be executed next and is incremented each time an
instruction is fetched from memory
A) MAR
B) PC
C) MDR
D) IR
44. In a vectored interrupt.
A. the branch address is assigned to a fixed location in memory.
B. the interrupting source supplies the branch information to the processor through an
interrupt vector.
C. the branch address is obtained from a register in the processor
D. none of the above
ans: B. the interrupting source supplies the branch information to the processor through an interrupt
vector

45. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping.
Then each word of cache memory shall be_____.
A. 11 bits
B. 21 bits
C. 16 bits
D. 20 bits
Ans: 16 bits

46. The product of +7 and -11 is

A) 110011001
B) 110111000
C) 10110011
D) 111111100

47. A page fault can occur when:

A) The page table is full
B) The required page is not in main memory
C) The cache is full
D) The disk drive fails
Ans: B) The required page is not in main memory

49. The result of +42+(−13) in binary is

A) 00011101
B) 11110011
C) 00001101
D) 11100011
50. Convert binary number 10010110 into octal number.
A) 226 B) 224
C) 221 D) 222

51. The primary purpose of an Operating system is

A) To keep system programs employed B) To allow people to use the computer
C) To make computers easier to use D) To make the most efficient use of computer
hardware

52. 5BC Hexadecimal to the decimal system

A) 1468 B) 1648
C) 468 D) 1846

53. A ______________is a combinational circuit that receives binary information from

one of 2n input data lines and directs it to a single output line.
A) Full – Adder B) Half- Adder
C) NAND gate D) Multiplexer

54. A 4-bit register has a group of ___ flip-flops and is capable of storing any binary information of ___
A) 3,2 B) 2, 3
C) 1, 4 D) 4,4

55. Perform the subtraction with the unsigned decimal number by taking the 2's complement of the
subtrahend: 11010 – 10000
A) 10110 B) 11101
C) 01010 D) 01101

56. Which of the following is NOT a component of the Von Neumann architecture?
A) ALU B) Control Unit
C) Memory D) Network Interface Card

57. Which of the following is NOT a typical characteristic of a multiprocessor system?

A) Increased throughput B) Multiple instruction streams
C) High availability D) Centralized memory control

58. In interprocessor arbitration, what is the purpose of a "bus arbiter"?

A) To manage memory requests from the processors B) To allocate communication
resources to competing processors
C) To prioritize I/O operations D) To handle cache coherence across processors

59. Which interconnection structure provides a dedicated path between any two processors in a system?
A) Mesh topology B) Shared bus
C) Crossbar switch D) Hypercube topology

60. In a multiprocessor system, what is the purpose of synchronization?

A) To enable I/O devices to communicate with processors B) To manage the clock speeds of all
processors
C) To coordinate access to shared resources such as memory D) To initiate simultaneous
processor execution

61. In the Booth's multiplication algorithm, what is the purpose of encoding the multiplicand?
A) To speed up the division process B) To reduce the number of additions required during
multiplication
C) To simplify floating-point operations D) To handle signed multiplication

62. Convert the hexadecimal number 3A.6E₁₆ to binary.

A) 111010.01110110₂ B) 110101.11011100₂
C) 111011.01110100₂ D) 111010.11011100₂
63. Using Booth's algorithm, calculate the product of 1101₂ (13 in decimal) and 1010₂ (-6 in decimal).
A) -78₁₀ B) -68₁₀
C) 78₁₀ D) 68₁₀

64. In multiple Bus organization, the registers are collectively placed and referred as _____
A) Set registers B) Register file
C) Register Block D) Map registers

65. The method for updating the main memory as soon as a word is removed from the Cache is called ____
A) Write-through B) Write-back
C) protected write D) Intense heat radiations

66. In a micro-programmed control unit, the control memory stores

A) General-purpose data B) Micro-instructions
C) Machine instructions D) Input/Output data

67. Address sequencing in a micro-programmed control unit is essential for

A) Fetching the next machine instruction B) Determining the next micro-instruction to execute
C) Controlling the data flow between registers D) Managing interrupt requests

68. Which of the following is a type of architecture used in the computers nowadays?
a) Microarchitecture
b) Harvard Architecture
c) Von-Neumann Architecture
d) System Design