Analog Electronics I, ECE-201

Chapter 4:
Field Effect Transistors/FETs

Instructor: Abreha T. (MSc in Microelectronics Engineering)

 Contents

 4.1: FET Structure and Operation

 4.2: FET Biasing
 4.3: FET AC Analysis
4.1 FET structure and operation

FETs vs. BJTs

Similarities: Amplifiers
Switching devices
Impedance matching circuits

Differences: FETs are voltage controlled devices. BJTs are

current controlled devices.
FETs have higher input impedance. BJTs have
higher gain.
FETs are less sensitive to temperature variations
and are better suited for integrated circuits
FETs are generally more static sensitive than
BJTs.
 FET Types

JFET: Junction FET

MOSFET: Metal–Oxide–Semiconductor FET

D-MOSFET: Depletion MOSFET

E-MOSFET: Enhancement MOSFET

 JFET Construction

There are two types of JFETs:

n-channel
p-channel
The n-channel is the more widely used
of the two.

JFETs have three terminals:

The Drain (D) and Source (S)

are connected to the n-channel
The Gate (G) is connected to the p-type material
JFET Operation: The Basic Idea

JFET operation can be compared to that of a water spigot.

The source is the accumulation of
electrons at the negative pole of the
drain-source voltage.

The drain is the electron deficiency

(or holes) at the positive pole of the
applied voltage.

The gate controls the width of the n-

channel and, therefore, the flow of
charges from source to drain.
JFET Operating Characteristics

There are three basic operating conditions for a JFET:

• VGS = 0 V, VDS increasing to some positive value

• VGS < 0 V, VDS at some positive value

• Voltage-controlled resistor
JFET Characteristics: VGS=0V

Three things happen when VGS = 0 V and VDS increases

from 0 V to a more positive voltage:
• The size of the depletion region between
p- type gate and n-channel increases.

• Increasing the size of the depletion

region decreases the width of the n-
channel, which increases its resistance.

• Even though the n-channel resistance is

increasing, the current from source to
drain (ID) through the n-channel is
increasing because VDS is increasing.
JFET Characteristics: Pinch Off

• If VGS = 0 V and VDS continually

increases to a more positive voltage, a
point is reached where the depletion
region gets so large that it pinches off
the channel.

• This suggests that the current in

channel (ID) drops to 0 A, but it does
not: As VDS increases, so does ID.
However, once pinch off occurs,
further increases in VDS do not
cause ID to increase.
JFET Characteristics: Saturation

At the pinch-off point:

Any further increase in VDS
does not produce any increase
in ID. VDS at pinch-off is
denoted as Vp

ID is at saturation or maximum,
and is referred to as IDSS.
Usually Vp is the value of
VGS that makes ID=0 and it is
negative; therefore, VDS=|Vp|
JFET Operating Characteristics

As VGS becomes more

negative, the depletion
region increases.
JFET Operating Characteristics
As VGS becomes more negative:
• The JFET experiences pinch-
off at a lower voltage (VP).
• ID decreases (ID < IDSS)
even when VDS increases

• ID eventually drops to 0 A. The

value of VGS that causes this to
occur is designated VGS(off)=Vp
and is usually <0.

Note that at high levels of VDS the JFET reaches a breakdown situation. ID
increases uncontrollably if VDS > VDSmax, and the JFET is likely destroyed.
Voltage-Controlled Resistor

The region to the left of the

pinch-off point is called the
ohmic region.

The JFET can be used as a

variable resistor, where VGS
controls the drain-source
resistance (rd).

ro
rd  2
 VGS 
1   As VGS becomes more negative, the resistance (rd)
 VP  increases.
 P-Channel JFETs

The p-channel JFET

behaves the same as the
n-channel JFET. The only
differences are that the
voltage polarities and
current directions are
reversed.
P-Channel JFET Characteristics

As VGS becomes more positive:

• The JFET experiences pinch-off

at a lower voltage (VP).

• The depletion region increases,

and ID decreases (ID < IDSS)

• ID eventually drops to 0 A
(when VGS = VGSoff)

Also note that at high levels of VDS the JFET reaches a breakdown
situation: ID increases uncontrollably if VDS > VDSmax.
N-Channel JFET Symbol
JFET Transfer Characteristics

JFET input-to-output transfer characteristics are not

as straightforward as they are for a BJT.

• BJT:  indicates the relationship between IB (input) and IC

(output).

• JFET: The relationship of VGS (input) and ID (output) is a little

more complicated:

2
 V 
ID  I 
DSS 1 V
GS 

 P 
 JFET Transfer Curve

This graph shows

the value of ID for
a given value of
VGS.
Plotting the JFET Transfer Curve

Using IDSS and Vp (VGS(off)) values found in a specification sheet, the

transfer curve can be plotted according to these three steps:

1. Solving for VGS = 0 V: ID = IDSS

2
 V 
2. Solving for VGS = VGS(off): ID = 0 A ID  I 
DSS 1 V
GS 

 P 

3. Solving for VGS = 0 V to VGS(off): 0 A < ID < IDSS

 JFET Specification Sheet

Electrical
Characteristics
JFET Specification Sheet

Maximum Ratings
Case and Terminal Identification
 Testing JFETs

Curve Tracer
A curve tracer displays the ID versus VDS graph for
various levels of VGS.

Specialized FET Testers

These testers show IDSS for the JFET under test.
 MOSFETs

MOSFETs have characteristics similar to those of

JFETs and additional characteristics that make then
very useful.
There are two types of MOSFETs:

Depletion-Type

Enhancement-Type
Depletion-Type MOSFET Construction

The Drain (D) and Source (S)

connect to the to n-type regions.
These n-typed regions are
connected via an n-channel. This
n-channel is connected to the
Gate (G) via a thin insulating
layer of silicon dioxide (SiO2).

The n-type material lies on a p-

type substrate that may have an
additional terminal connection
called the Substrate (SS).
Basic MOSFET Operation

A depletion-type MOSFET can operate in two modes:

Depletion mode

Enhancement mode
Depletion Mode Operation (D-MOSFET)

The characteristics are

similar to a JFET.

When VGS = 0 V, ID = IDSS

When VGS < 0 V, ID < IDSS

The formula used to plot the 2

 V 
transfer curve for a JFET applies to ID  I 
DSS 1 V
GS 

 P 
a D-MOSFET as well:
Enhancement Mode Operation
(D-MOSFET)

VGS > 0 V, ID increases

above IDSS (ID > IDSS)

The formula used to

plot the transfer curve
still applies:

2
 V 
ID  I 
DSS 1 V
GS 
 Note that VGS is now positive
 P 
p-Channel D-Type MOSFET
D-Type MOSFET Symbols
Specification Sheet

Maximum Ratings
 Specification Sheet

Electrical
Characteristics
E-Type MOSFET Construction

The Drain (D) and Source (S) connect to the to n-type regions.
These n-type regions are connected via an n-channel

The Gate (G) connects to the p-type

substrate via a thin insulating layer of
silicon dioxide (SiO2)

There is no channel

The n-type material lies on a p-type

substrate that may have an additional
terminal connection called the
Substrate (SS)
 Why MOS (Metal-Oxide) Transistors?
 •Very small (smaller silicone area on the IC)
 •Simple to manufacture
 •No need for biasing resistors.
 •Used in VLSI (very-large-scale integration)
 •The enhancement type MOSFET is the most significant
semiconductor devise available today.
E-Type MOSFET Operation

The enhancement-type MOSFET (E-MOSFET) operates only

in the enhancement mode.
VGS is always positive

As VGS increases, ID
increases

As VGS is kept constant

and VDS is increased,
then ID saturates (IDSS)
and the saturation level
(VDSsat) is reached
Derivation of ID- vDS Relationship
 …contd

uncox is a constant determined by the processing technology and is denoted as k’n

 …contd

Saturation Region Triode Region

1 𝑤
𝑘𝑛 = 𝑘′𝑛
2 𝐿 ⅈ 𝐷 = 2𝑘𝑛 VGS − VT VDS for VDS<<1
ⅈ 𝐷 = 𝑘𝑛 VGS − VT 2

Derivation of the iD - vDS characteristic of the NMOS transistor.

 Output resistance and
channel length modulation
 In the ideal case, when a MOSFET is biased in the
saturation region, the drain
current iD is independent of drain-to-source
voltage vDS.
 In actual MOSFET iD versus vDS characteristics, a
nonzero slope does exist beyond the saturation
point.
 For vDS > vDS(sat), the actual point in the channel at
which the inversion charge goes to zero moves
away from the drain terminal.
 The effective channel length decreases,
producing the phenomenon called channel
length modulation.
 The curves can be extrapolated so that they
intercept the voltage axis at a point vDS = -VA.
 The voltage VA is usually defined as a positive
quantity.
 The slope of the curve in the saturation region
can be described by expressing the iD versus vDS
characteristic in the form, for an n-channel
device,
E-Type MOSFET Transfer Curve

To determine ID given VGS:

I D  k n (VGS  VT ) 2

where:
VT = the E-MOSFET
threshold voltage
kn, a constant, can be
determined by using
values at a specific point VDSsat can be calculated using:
and the formula:
I D(ON)
kn  VDSsat  VGS  VT
(VGS(ON)  VT) 2
p-Channel E-Type MOSFETs

The p-channel enhancement-type MOSFET is similar

to its n-channel counterpart, except that the voltage
polarities and current directions are reversed.
MOSFET Symbols
Specification Sheet

Maximum Ratings

more…
 Specification Sheet

Electrical
Characteristics
Handling MOSFETs

MOSFETs are very sensitive to static electricity.

Because of the very thin SiO2 layer between the external terminals
and the layers of the device, any small electrical discharge can
create an unwanted conduction.

Protection
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
• Apply voltage limiting devices between the gate and source,
such as back-to-back Zeners to limit any transient voltage.
 VMOS Devices

VMOS (vertical MOSFET) is a component structure that

provides greater
surface area.
Advantages
VMOS devices handle
higher currents by
providing more surface
area to dissipate the heat.

VMOS devices also have

faster switching times.
 CMOS Devices

CMOS (complementary MOSFET) uses a p-channel and

n-channel MOSFET; often on the same substrate as
shown here.
Advantages

• Useful in logic circuit designs

• Higher input impedance
• Faster switching speeds
• Lower operating power levels
Summary Table
4.2: Common FET Biasing
Circuits
JFET Biasing Circuits

• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias

D-Type MOSFET Biasing Circuits

•Self-Bias
•Voltage-Divider Bias

E-Type MOSFET Biasing Circuits

•Feedback Configuration
•Voltage-Divider Bias

49
Basic Current Relationships

For all FETs:

I G  0A
I D  IS

For JFETS and D-Type MOSFETs:

2
 V 
I D  I DSS  1  GS 
 VP 

For E-Type MOSFETs:

I D  k (VGS  VT ) 2

50
Fixed-Bias Configuration

VDS  VDD  I D RD
VS  0V
VC  VDS
VG  VGS
VGS  VGG

51
Self-Bias Configuration

52
 Self-Bias Calculations
For the indicated loop, VGS  I D R S
To solve this equation:
• Select an ID < IDSS and use the component value of
RS to calculate VGS
• Plot the point identified by ID and VGS. Draw a
line from the origin of the axis to this point.
• Plot the transfer curve using IDSS and
VP (VP = VGSoff in specification sheets) and a few
points such as ID = IDSS / 4 and ID = IDSS / 2 etc.

The Q-point is located where the first line

intersects the transfer curve. Use the value
of ID at the Q-point (IDQ) to solve for the
other voltages:
VDS  VDD  I D ( R S  R D )
VS  I D R S
VD  VDS  VS  VDD  VRD

53
 Voltage-Divider Bias

IG = 0 A

ID responds to changes in
VGS.

54
Voltage-Divider Bias Calculations
VG is equal to the voltage across
divider resistor R2:
R 2 VDD
VG 
R1  R 2

Using Kirchhoff’s Law:

VGS  VG  I D R S

The Q point is established by plotting

a line that intersects the transfer
curve.

55
 Voltage-Divider Q-point
Step 1
Plot the line by plotting two points:
•VGS = VG, ID = 0 A
•VGS = 0 V, ID = VG / RS

Step 2
Plot the transfer curve by plotting
IDSS, VP and the calculated values
of ID
Step 3
The Q-point is located where the
line intersects the transfer curve

56
Voltage-Divider Bias Calculations

Using the value of ID at the Q-point, solve for the other variables in the voltage-
divider bias circuit:

VDS  VDD  I D (R D  R S )
VD  VDD  I D R D
VS  I D R S
VDD
I R1  I R2 
R1  R 2

57
D-Type MOSFET Bias Circuits

Depletion-type MOSFET bias

circuits are similar to those
used to bias JFETs. The only
difference is that depletion-type
MOSFETs can operate with
positive values of VGS and with
ID values that exceed IDSS.

58
 Self-Bias
Step 1
Plot line for
•VGS = VG, ID = 0 A
•ID = VG/RS, VGS = 0 V

Step 2
Plot the transfer curve using IDSS, VP and
calculated values of ID

Step 3
The Q-point is located where the line
intersects the transfer curve. Use the ID at
the Q-point to solve for the other variables
in the voltage-divider bias circuit.

These are the same steps used to analyze JFET self-bias circuits.

59
 Voltage-Divider Bias
Step 1
Plot the line for
•VGS = VG, ID = 0 A
•ID = VG/RS, VGS = 0 V

Step 2
Plot the transfer curve using IDSS, VP and
calculated values of ID.

Step 3
The Q-point is located where the line intersects
the transfer curve is. Use the ID at the Q-point
to solve for the other variables
in the voltage-divider bias circuit.

These are the same steps used to analyze

JFET voltage-divider bias circuits.

60
 E-Type MOSFET Bias Circuits

The transfer characteristic for

the e-type MOSFET is very
different from that of a simple
JFET or the d-type MOSFET.

61
 Feedback Bias Circuit

IG = 0 A

VRG = 0 V

VDS = VGS

VGS = VDD – IDRD

62
 Feedback Bias Q-Point
Step 1
Plot the line using
•VGS = VDD, ID = 0 A
•ID = VDD / RD , VGS = 0 V

Step 2
Using values from the specification
sheet, plot the transfer curve with
•VGSTh , ID = 0 A
•VGS(on), ID(on)

Step 3
The Q-point is located where the line
and the transfer curve intersect

Step 4
Using the value of ID at the Q-point,
solve for the other variables in the
bias circuit
63
 Voltage-Divider Biasing

Plot the line and the transfer curve to find the

Q-point. Use these equations:

R 2 VDD
VG 
R1  R 2
VGS  VG  I D R S
VDS  VDD  I D ( R S  R D )

64
Voltage-Divider Bias Q-Point
Step 1
Plot the line using
•VGS = VG = (R2VDD) / (R1 + R2), ID = 0 A
•ID = VG/RS , VGS = 0 V

Step 2
Using values from the specification sheet, plot the transfer curve
with
•VGSTh, ID = 0 A
•VGS(on) , ID(on)
Step 3
The point where the line and the transfer curve intersect is the Q-
point.

Step 4
Using the value of ID at the Q-point, solve for the other circuit
values.

65
 p-Channel FETs

For p-channel FETs the same calculations and graphs are used,
except that the voltage polarities and current directions are reversed.

The graphs are mirror images of the n-channel graphs.

66
Applications

Voltage-controlled resistor
JFET voltmeter
Timer network
Fiber optic circuitry
MOSFET relay driver

67
4.3: FET Amplifiers AC analysis
Introduction
FETs provide:

• Excellent voltage gain

• High input impedance
• Low-power consumption
• Good frequency range

68
 FET Small-Signal Model

Transconductance

The relationship of a change in ID to the corresponding

change in VGS is called transconductance

Transconductance is denoted gm and given by:

ΔI D
gm 
ΔV GS

Where IDQ is DC component and id ac component, id=gmvgs

69
Graphical Determination of gm

70
Mathematical Definitions of gm
I D
gm 
VGS

2I DSS  VGS 
gm  1  
VP  VP 

2I DSS
Where VGS =0V g m0 
VP
 V 
g m  g m0 1  GS 
 VP 

Where 1  VGS  ID
VP I DSS

 V  ID
g m  g m0  1  GS   g m0
 VP  I DSS

For E-MOSFET

71
 FET Impedance
Input impedance:
Z i  

Output Impedance:
1
Z o  rd 
y os

where:
VDS
rd  VGS  constant
I D
yos= admittance parameter listed on FET specification sheets.

72
FET AC Equivalent Circuit

=ro

For E-MOSFET

73
 Common-Source (CS) Fixed-Bias Circuit

The input is on the gate and the

output is on the drain

There is a 180 phase shift

between input and output

74
 Calculations
Input impedance:

Zi  RG

Output impedance:

Zo  R D || rd

Zo  R D
rd  10RD

Voltage gain:
Vo
Av   g m (rd || R D )
Vi
Vo
Av   g m R D
Vi rd  10RD

75
Common-Source (CS) Self-Bias Circuit

This is a common-source amplifier

configuration, so the input is on the gate
and the output is on the drain

There is a 180 phase shift between

input and output

76
 Calculations
Input impedance:
Zi  RG

Output impedance:

Zo  rd || R D

Zo  R D
rd  10RD

Voltage gain:

A v  g m (rd || R D )

A v  g m R D
rd  10RD

77
Common-Source (CS) Self-Bias Circuit

Removing Cs affects
the gain of the circuit.

78
 Calculations
Input impedance:
Zi  RG

Output impedance:

Zo  R D
rd  10RD

Voltage gain:
Vo gm R D
Av  
Vi R  RS
1  gmRS  D
rd
Vo g R
Av    m D rd  10(R D  R S )
Vi 1  gm RS

79
Common-Source (CS) Voltage-Divider Bias

This is a common-source
amplifier configuration, so the
input is on the gate and the
output is on the drain.

80
 Impedances
Input impedance:

Z i  R 1 || R 2

Output impedance:

Zo  rd || R D

Zo  R D
rd  10RD

Voltage gain:
A v  g m (rd || R D )

A v  g m R D
rd  10RD

81
Source Follower (Common-Drain) Circuit
In a common-drain amplifier
configuration, the input is on the
gate, but the output is from the
source.

There is no phase shift between

input and output.

82
 Impedances
Input impedance:
Zi  RG

Output impedance:
1
Z o  rd || R S ||
gm
1
Z o  R S || r  10RS
gm d

Voltage gain:
Vo g m (rd || R S )
Av  
Vi 1  g m (rd || R S )
Vo gm RS
Av   r  10
Vi 1  g m R S d

83
 Common-Gate (CG) Circuit

The input is on the source

and the output is on the
drain.

There is no phase shift

between input and output.

84
 Calculations
Input impedance:

 r  RD 
Z i  R S ||  d 
 1  g m rd 
1
Z i  R S || r  10RD
gm d

Output impedance:

Zo  R D || rd
Voltage gain:
Z o  R D rd  10
 RD 
 m D
g R  
Vo  rd  A v  g m R D rd  10RD
Av  
Vi  RD 
1  
 rd 

85
D-Type MOSFET AC Equivalent

86
 E-Type MOSFET AC Equivalent

gm and rd can be found in

the specification sheet for
the FET.

87
Common-Source Drain-Feedback

There is a 180 phase shift

between input and output.

88
 Calculations
Input impedance:
R F  rd || R D
Zi 
1  g m (rd || R D )
RF
Zi  R  rd || R D , rd  10RD
1  gm R D F

Output impedance:
Zo  R F || rd ||R D

Zo  R D R F rd || R D , rd  10RD

Voltage gain:

A v  g m (R F || rd || R D )
A v   g m R D R F rd ||R D ,rd 10RD

89
Common-Source Voltage-Divider Bias

90
 Calculations
Input impedance:
Z i  R 1 || R 2

Output impedance:
Zo  rd || R D
Z o  R D rd  10

Voltage gain:
A v  g m (rd || R D )
A v  g m R D rd  10RD

91
Summary Table

more…
92
Summary Table

93
 Troubleshooting
Check the DC bias voltages:

If not correct check power supply, resistors, FET. Also check to ensure
that the coupling capacitor between amplifier stages is OK.
.
Check the AC voltages:

If not correct check FET, capacitors and the loading effect of the next
stage

94
Practical Applications
Three-Channel Audio Mixer
Silent Switching
Phase Shift Networks
Motion Detection System

95
 Example-1

 Determine Zi, Zo, and Av for the network of Fig. below:

Solution
 Example-2

 Determine the small-signal voltage gain and

input and output resistances
of a common-source amplifier.
 the parameters are: VDD = 3.3 V,
RD = 10 k, R1 = 140 k, R2 = 60 k, and RSi=4k,
VTN = 0.4 V, Kn = 0.5 mA/V2,and λ = 0.02 V-1.
Solution
AC Solution
 Example-3

 Determine Vo for the network of Fig. below if Vi = 4 mV, VGS(Th) =4 V, and

ID(on)=4 mA, with VGS(on) = 7 V and yos = 20 uS.
Solution
THANKS
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