TFT

Cst Design (Cst on Com & Cst on Gate)

Cs

Cs

Gate Line Gate Line

TFT TFT
Data Line

Data Line
Higher Open Ratio

Cs

Common

Cst on Com Cst on Gate

 Pixel Layout (Cst on Com & Cst on Gate)
Cst on Gate / Com Cst
MII & MIM

DA /DI / DK
Cst on Com
MIM

TFT
TFT
Gate-line
Gate-line Via
Via Data-line
Data-line Cst
Cst ITO
ITO

DL /DJ / DM / DN
Cst on Gate
MII
 -----MIM vs. MII
:
M – metal GE / SD / ITO
I – Insulator AS / BP Short
Cst on Com SD/GE ,
MIM
MIM MII ,
Cross -View
Cross-View MIM ,

Cst on
Gate
---
defect
,pd21 & pd11
MII
MII
Cross -View
Cross-View

Cst on Gate
ITO/GE
 Pixel
pixel (R ,G ,B )
pixel
1.TFT device Æ pixel

2. Cst Æ ,
pixel

3. ITO Æ
pixel
TFT Configuration
 Process Flow
Topside exposure---UV light

Mask

Glass TFT Cs Contact

Film AlNd (3000A) /Mo (500A)
Coating PR (1.5um) Æ Exp. Æ Develop
Etch AlNd/Mo (Wet Etch)
Stripper Remove PR (O3 +IPA )
CA / CL / CM IA / IL
Cst on Gate Cst on Com
MIM MIM
 TFT Pattern

GE Pattern

Cst Pattern
AS Pattern
SD Pattern
 ITO Pattern

BP Pattern

TFT Pattern
 W

L Wcgd
Sp

LSD
TFT
LITO

CST LGE LBP LPL

LAS
GE : 1. ( Scan line ) , AS
2. , ……..

AS : 1.Pixel , SD pixel , pixel

2.Dummy pattern,mark,numbers,…….not for circuit layout.
3. ,i.e.Repair Line cross-over pads.

SD : 1. ( Data line ), pixel

2. , ……..
BP : 1. , BP Via ,

2. ,Dummy pattern,mark,numbers,…….not for circuit layout.

ITO : 1.Pixel , , pixel
2. , , ,
, cut
 TFT ON / OFF

Source
GE OFF
Drain
Source Drain
a-Si
pixel
G-SiNx
GE

Drain Source GE ON
a-Si
Source Drain

G-SiNx
Drain a-Si Source pixel
GE
 Bottom gate (eg. BCE structure)

S/D metal Channel

G-SiNx n+ a - Si

GE

Substrate

Current

+++++

Positive voltage
GE/SD Ti
Al
n+- -Si
-Si
ITO
G-SinNx
SinNx
GE layer BP layer

AS layer
ITO layer

SD layer Array completed

GE layer BP layer

AS layer
ITO layer

SD layer Array completed

 Cst on Com
GE

AS

SD

BP

ITO
 TFT / Cst
Cross sectional view of pixel TFT

Cross sectional view of pixel Cst

 DN -
GE

GE depo GE photo

GE etch GE stripper
 AS

AS depo AS photo

Depo n+
AS stripper
a-Si
G-SiNx

Photo / Etch
n+

a-Si
G-SiNx
 SD

SD depo SD photo

SD etch SD stripper
 BP

BP depo BP photo

BP etch BP stripper
 ITO

ITO depo ITO photo

ITO etch ITO stripper

 TFT & Cst SEM Cross-View
TFT
TFT

Cst
Cst

GE :
AS : G-SiNx
a-Si
SD : SD
BP : GE SD ,

ITO :
 Topside exposure---UV light

Ti 500 A
Al 1800 A
Ti 130 A

TFT Cst Contact

Metal 1( GE )

Metal 1( GE )
 G-SiNx 3450A

TFT Cst Contact

G-SiNx
 a-Si 2000A

TFT Cst Contact

AS layer
 Topside exposure---UV light

mask pattern

TFT Cst Contact

AS Etching
 Topside exposure---UV light

Mo/AL/Mo 500/2500/250A

TFT Cst Contact

MII

Channel
 Topside exposure---UV light

PV-SiNx 2000A

TFT Cst Contact

& Through hole

 Topside exposure---UV light

ITO 400A

TFT Cst Contact

ITO Sputter

ITO Etching
TFT Cst Contact
Cell Laser Repair
3 dot in 1 pixel
Laser repair line Ag pad
Outer Shorting Bar

Inner Shorting Bar

 Cell Test Pad
V com R G B

FPC pad V com Odd Even

Cell test pad

FPC:
Flexible Printed Circuit
 COG pad
Fan In GE side

Fan In S/D side

Shorting bar

COG: Chip On Glass

Pixel Array Pixel to COG/FPC Layout
 Stepping
Stepping Overlay Stitching
Especially in gray scale!!!
“ ” !!!

Solutions:
Improve Overlay Accuracy
Increase alignment Tolerance
Solution 1:

Solution 2: Hyper Blind - Nikon

Blind , Hyper-shot Concept:
Blind: blade define
Stepper definition blade

Blind Mode:
1.Normal mode 2. Hyper-shot mode
Each blade Hyper-shot Cr
particle pattern Cr
(Stepper )
Normal Hyper-shot
define
coating 4.0 mm (
Stage 5mm) Hoper-shot coating( y overlap)
blade control( x overlap) coating
intensity
p.s:
 shot repeat shot
shot overlap 2um, ,

Normal exposure Hyper Shot

Hyper-shot overlap y
coating x
Hyper-shot mode blade x
Hyper-shot x 1 1 y
 Dose control: Improves the alignment accuracy
Overlay shift occurs:
Hyper Shot
Hyper Blind
Normal
exposure

Overlap area
Reticle Design -> Hyper shot edges:
 Stepper structure
H yper shot M ain S hutter
D ichronic m irror D ichronic m irror
B ar code reader

R aticle stage
R eticle changer

PPD E llipsoidal m irror

P rojection lens
R eticle cache
A uto focus and plate m icroscope
P late load arm
P late S tage
B ase

Vibration isolated table

 stage sensor Ystage sensor

pre-align pins

He-Ne Laser
Fiducial mark

Reference point

motor

Plate holder illuminance sensor

X motor X stage sensor

Z stage

X stage

Y stage
Stage

Base

Y motor
 Reticle blade structure
Driver
Liner guide
Digital Micrometer
YU

Lead screw
XL Hole XR
Nut
Driver
M

Driver YP

Driver
 Reticle:4-6 SHOT

Stepping 1 2 1 2 1 2
3 4 3 4 3 4

1 2 1 2 1 2
3 4 3 4 3 4
 Alignment
Detector(B phase) Detector (A phase)

Slit
PGA:Plate Global Alignment
Diffraction EGA:Enhanced Global Alignment
Laser beam
4-Point Simultaneously EGA
EGA mark
d
Plate
Plate Existence Sensor

Illumination sensor
(Uniformity check)

Sub Fidution Mark(FM2)

Main Fidution Mark
ST Center Up (8 pins )

Dose Monitor (Only used for calibration of reticle)

 Alignment Correction values
1. Shift 2. Plate Rotation 3. Reticle Rotation

4. Scaling 5. Orthogonality 6. Magnification

 Developing
Fast Dissolving
Dissolving rate
rate in
in TMAH
TMAH Exposed area
Dissolving rate for HMDS

Resin+photo
Resin reacted PAC

Unexposed area

Resin+PAC

PAC

Slow
 TFT driving curve

TFT
TFT Operation:
Operation: Id-Vd
Id-Vd curve
curve

Linear
Linearregion
region

15
 1 2
W
( )
14
13 Id = Ci µ  Vg − Vt Vd − Vd 
12
11 Vg=4V L 2 
10 Vg=6V
9
Id (mA)

Vg=8V
8 Vg=10V
7
Idsat
6 Saturation
Saturationregion:
region:
5
4 → Vg - Vt = Vd
→ Vg - Vt = Vd
3
2
1
0

µCi (Vg − Vt )2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 W
Vd (V)
Id =
2 L
 TFT characteristic
Transfer Characteristics Output Characteristics
100uA On state 20uA

1. 0uA
Vgs =25V
10uA

10nA
Vgs =15V

Vd=25V Vgs =5V

100pA 0A
Vd=15V
Off state

1. 0pA
Vd=5V
- 10uA
- 25V 0V 25V - 10V 0V 10V 20V 30V
I ( Rl oa d) I ( Rl oa d)
V_Vg V_Vd

Linear region: I ds = C0 µ FE
W
( Vgs − Vth )Vds − 1 Vds2  0 ≤ Vds ≤ Vgs − Vth
L 2  Linear region
C0 µ FE
(Vgs − Vth ) 2
W (operation range)
Saturation region: I ds = Vds ≥ Vgs − Vth ≥ 0
2 L

Sub-threshold region: 0 ≤ Vgs ≤ Vth

Off region: Vgs < 0

 TFT driving curve

T
Vcom:

100%

Vth Vth
3.5V 6.5V
V

5V
 TFT driving curve

100%

Vth Vth

V
-1.5V 5V
 TFT
W W: Channel width
Ion ∝ Cg L: Channel length
L Cg: Gate capacitor

A
Cg ∝ ε ∗
d SiNx
W  LSD _ design − ∆
  =
 L  actual LSD _ design + ∆
Cgs: Capacitor of GE/Source overlay
Cgd: Capacitor of GE/Drain overlay
Cst: Storage capacitor ∆= LSD_design-LSD_AEI
GE/ SD overlay parasitic capacitor
ITO/ Data Line parasitic capacitor
Clc: Capacitor of Liquid crystal (Pixel ITO/CF ITO)
GE : Ti/Al/Ti ----
Ti Al , Al
AS : Si , , AS
,AS= G-SiNx + a-Si , GE G-SiNx
GE G-SiNx + a-Si
SD : GE -----
BP : AS Si , pattern
ITO : , ( 80% ),
,

Conclusion:
Pixel
,

pattern
Æ OK or NG
SEM top-view
GE SEM cross-section

BP BP

SD SD
a-Si a-Si
G-SiNx G-SiNx
GE GE
TFT Channel SEM cross-section
BP

SD
BP
a-Si a-Si
G-SiNx G-SiNx
GE GE
AS island SEM cross-section

BP
a-Si AS
a-Si
G-SiNx
Glass
 Via-SD SEM cross-section

ITO ITO
BP Via Via BP
ITO ITO
SD SD

G-SiNx G-SiNx
Glass Glass
 Via-GE SEM cross-section

ITO
ITO
BP Via
Via BP
G-SiNx
ITO G-SiNx
GE ITO
GE
Glass
Glass
R G B GO GE Vcom R G B GO GE Vcom TA

R G B GO GE Vcom

A,C,D,F TA PF( Probe Frame )

,B,E IPT
panel, IPT
panel skipped,
B or E chip

R G B GO GE Vcom R G B GO GE Vcom
TEG --- TEST KEY

TEG TEG TEG

9 8 7

TEG TEG TEG

6 5 4

TEG TEG TEG

3 2 1

6 3

5 2

4 1
 v.s Panel

Test Report AOI Map Olympus FI1 Map

C F D A
F E D
B E E B
C B A
A D F C
 Operation Principle of TN LCD
• Alignment of liquid crystal molecules • Operation principles of NW mode TN LCD

NW: Normally White, TN: Twisted Nematic

 T-V curve of TN LCD

• Operation principles of NW mode • Typical T-V curve of NW mode

TFT LCD TFT LCD

turn-off

turn-on
 LCD structure and configuration

LCD
LCD configurations
configurations LCD
LCD structure
structure
 TFT

1H
Row Drivers Column Driver

Clc Cs Clc Cs Clc Cs

Clc Cs Clc Cs Clc Cs

Clc Cs Clc Cs Clc Cs

1H
 TFT Timing chart

DATA L1 L2 L3

Gate Frame Time

1H
1

N
 TFT driving principle
• Scanning at-a-line
- Vgh is applied to a gate line
- All TFTs on a gate line are turned on
- Current flows from data line to pixel and pixels on
the gate line are charged up to data voltage
- Vgl is applied to a gate line
- All TFTs on a gate line are turned off and pixels on
the gate line holds the charged voltage
– + Cst
tF = 16.7ms
G0

off off off tg (gate on time)

G1
on –V1 on +V2 on –V3

G2

off off off

G3

off off off

G(last)
 TFT resolution
Display Format Resolution Gate-on-time Pixel Size (in 15.1”)

VGA 480x640xRGB 34µs 480µm X 160µm

SVGA 600x800xRGB 27µs 384µm X 128µm

XGA 768x1024xRGB 21.7µs 300µm X 100µm

SXGA 1024x1280xRGB 16µs 234µm X 78µm

UXGA 1200x1600xRGB 13µs 192µm X 64µm

QXGA 1536x2048xRGB 10µs 150µm X 50µm

Refreshing time tF ( Frame time ) ( dominated by the Pixel design – tg )

Refreshing rate = 1/ tF
Gate switching time tg ( Gate-on time )
tg ( Gate-on time ) = tF ( Frame time ) / total Gate line ( dominated by product resolution)
For example: tg ( Gate-on time ) = 16.7 ms / 768 ( for 14.1” XGA ) = 21.7µs
 TFT resolution
•R/G/B: 6 bits , 26=64 scales
•1 dot: R/G/B 6X3=18 bits
• 218=256K scales
•Full color (True color) scale: 24 bits= 17M scales
•1M=1024K, 1K=1024bits

Pixel dimension: 88X264 mm2

Dot dimension: 264X264 mm2

•Color scale Depends on

Transmission (%)

•The charging capability

•T-V (Transmission versus Voltage) curve
•TN liquid crystal: Normally White
•TFT mobility (ie carrier mobility, )

Voltage
 Voltage Imaging

CCD
Data-feed to Image Processor
Imager

Modulator Measured
M
ILLUMINATOR Capacitance Light Trans.
Bias
Voltage
Imaging
Objective Air Gap
Capacitance

Auto- Pixel (ITO)

Modulator PZT
Gapper Voltage

E-fields coupled through air dielectric

Array Substrate
 Bias Voltage v.s Transmission

3500

3000

2500
Transmission [ADUs]

2000

1500

1000

500

0
0 50 100 150 200 250 300 350 400 450 500
Bias Voltage at 20 µm Gap
 VIOS measurement

• Four-frame measurement cycle cancels drift errors

– M = Frame_A – Frame_B – Frame_C + Frame_D
– Frame period ≅ 16.7 ms
– System changes polarity of pattern for subsequent frames
• Calibration image uses ±10V or ±15 V on bias
• Gain image = (2 * Cal_V * Cal_samples * Scale) / C
– C = value of Cal_image pixel measurement
– Scale factor @ 10 mV per A/D count
• Voltage image = Gain image * Measure image
– Normalized by number of measurement samples
– Convolved with 3 nearest CCD data for noise reduction
 VIOS Calibration
16.7ms 16.7ms

+230V

Modulator
Bias

–230V

Strobe
Time

Panel Driving
0V
(GE, GO, DE,
DO, SP)
 MPS Timing Chart for Measurement
16.7ms 16.7ms

MSYNC

FSYNC

MBIAS

STRB

Gate for measurement

GE

Safety Gate

GO

+ Vd
DE

- Vd 0V

+ Vd
DO

- Vd 0V

MSYNC: Master Sync Signal, FSYNC: Frame Sync Signal, MBIAS: Modulator Bias, STRB: Strobe Signal (Pixel votage acquisition timing signal), GO/GE: Gate Odd/Even signal,
DO/DE: Data Odd/Even Signal

MSYNC and FSYNC are the only two input signals to a pattern generator. GO/GE and DO/DE are driving signals for TFT.
 Gain Calc. & Voltage Measurement

• VM = V across LC layer
• V0 = VM without VCal
L1
• V1 = V0 + (k * VCal_Positive)
• V2 = V0 + (k * VCal_Negative)
Light Intensity

La

• Va = V0 + (k * Vpixel_Positive)
rve
cu
S-

• Vb = V0 + (k * Vpixel_Negative)
Lb • Gij = (V1 – V2) / (L1 – L2)ij
Vo
L2
• = k(VC_P + VC_N) / (L1 – L2)ij
Vb Va
• Vpixel = Gij * ∆LMij / k
V2 V1
• Normalized for k:
Vpixel = Gij * ∆LMij
V-modulator
 Pixel Voltage Measuring
Strobe time Voltage Image Capture
25V

Fr ame A & D Fr ame B & C

( 16. 000m, 8. 8906)

0V

( 32. 720m, - 11. 530)

- 25V
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms
V( Vdo: +) V( Vgo: +) V( Cs t 2: 1) V( Cs t 2: 2)
Ti me

V p = (V A − VB − VC + VD ) / 2 = [8.89 − (− 11.53) − (− 11.53) + 8.89] / 2 = 20.42V

 Checkerboard Pattern

Dot
Dotinversion
inversion Column
Columninversion
inversion Line
Lineinversion
inversion Frame
Frameinversion
inversion

1st
field

2nd
field

Positive voltage Negative voltage

 Dot Inversion Pattern

Vgh Vgl
Gate_Even

Gate_Odd

Data_Even
Vdl Vref

Data_Odd
Vdh
Spare

2 4 6 8 10 12 14 16
Vgh = +15V Vdh = +5V
Vgl = -15V Vref = 0V
tg = 100 s Vdl = -5V
 Gate Inversion Pattern

Vgh Vgl
Gate_Even

Gate_Odd

Data_Even
Vdl Vref

Data_Odd
Vdh
Spare

2 4 6 8 10 12 14 16
Vgh = +15V Vdh = +5V
Vgl = -15V Vref = 0V
tg = 100 s Vdl = -5V
 Data Inversion Pattern

Vgh Vgl
Gate_Even

Gate_Odd

Data_Even
Vdl Vref
Vdh

Data_Odd

Spare

2 4 6 8 10 12 14 16
Vgh = +15V Vdh = +5V
Vgl = -15V Vref = 0V
tg = 100 s Vdl = -5V
 Common Driving Pattern

Vgh Vgl
Gate_Even

Gate_Odd

Data_Even
Vref
Vdh

Data_Odd

Spare

2 4 6 8 10 12 14 16
Vgh = +15V Vdh = +5V
Vgl = -15V Vref = 0V
tg = 100 s Vdl = -5V
 Positive-Negative Driving Pattern

Vgh Vgl
Gate_Even

Gate_Odd

Data_Even

Data_Odd

Spare

2 4 6 8 10 12 14 16
Vgh = +15V Vdh = +10V Vdh = +15V
Vgl = -25V Vref = 0V Vref = 0V
tg = 100 s Vdl = -10V Vdl = -15V
 30V

7. 63V( I of f =1pA)
3. 33V( I of f =100pA)
- 0. 03V( I of f =1nA)

0V
- 5. 27V( I of f =100pA)
0. 00V( I of f =1nA)

- 13. 02V( I of f =1nA)

- 30V
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms
V( Vgo: +) V( Vdo: +) V( Cs t 1: 1) V( Cs t 2: 1) V( Cs t 3: 1)
Ti me

At Ioff = 1pA : V p = (V A − VB − VC + VD ) / 2 = [7.63 − (− 13.02 ) − (− 13.02 ) + 7.63] / 2 = 20.65V

At Ioff = 100pA : V p = (VA − VB − VC + VD ) / 2 = [3.33 − (− 5.27 ) − (− 5.27 ) + 3.33] / 2 = 8.60V

At Ioff = 1nA : V p = (VA − VB − VC + VD ) / 2 = [0.00 − (− 0.03) − (− 0.03) + 0.00] / 2 = 0.03V

 TFT Defect Types

TFT pixel open TFT data open

TFT gate open TFT via hole missing

Pixel-to-pixel short across gate line

Storage capacitor short

Pixel-to-data line short

Data line residue under pixel

a-Si residue under pixel

Pixel-to-pixel short across data line

High TFT off-current

Low TFT on-current
(defect feature cannot be shown)

Pixel-to-gate line short

 Defect Detection under PN pattern

Induced pixel voltage drop due to data voltage drop

Cst Cst

Cdp Cdp Cdp: capacitance of ITO-data line residue overlap

∆V p = • ∆V d Cst: capacitance of storage capacitor
C dp + C st + C gd Cgd: capacitance of TFT parasitic capacitor

Cgd Cgd
30V

Fr a me A & D Fr a me B & C

N: ( 16. 024m, 7. 5498) D2: ( 32. 717m, 10. 120)

D1: ( 16. 024m, 3. 2026)

0V
D1: ( 32. 717m, - 7. 7578)
Cst Cst D2: ( 16. 024m, - 11. 099)

N: ( 32. 717m, - 13. 194)

Cdp

- 30V
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms
V( Vgo: +) V( Vdo: +) V( Cs t 1: 1) V( Cs t 2: 1) V( Cs t 3: 1)
Cgd Cgd Ti me

N: Normal pixel
D1: Defective pixel with ITO-data line overlap
D2: Defective pixel with data-to-data short